CN107968656B - Successive approximation type analog-digital converter and application switching method thereof - Google Patents
Successive approximation type analog-digital converter and application switching method thereof Download PDFInfo
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Abstract
The invention relates to a successive approximation type analog-digital converter and an application switching method thereof, wherein the successive approximation type analog-digital converter comprises the following steps: the sampling switch circuit, the charge redistribution type digital-to-analog converter, the dynamic comparator and the SAR logic circuit are sequentially connected in series; the single-end application driving source is connected with the sampling switch circuit; the charge redistribution type digital-to-analog converter consists of a P-end capacitor array, an N-end capacitor array and a reference driving reverser; the P-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit; the N-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit. The invention can ensure the symmetry of the sampling network in single-ended application and differential application, improve the linearity of the sampling signal, further improve the accuracy of the ADC and reduce the power consumption.
Description
Technical Field
The invention relates to the field of analog-digital converters, in particular to a successive approximation type analog-digital converter and an application switching method thereof.
Background
In recent years, in order to expand various application integration more and more interface systems, a universal ADC is one of the interface systems, the requirements of the SOC system on the universal ADC are low power consumption, small area and support of single-ended differential application, the requirements on speed and precision are relatively low, along with the development of a CMOS process, the capacitance achievable on an advanced process is smaller and smaller, the matching precision is higher and higher, and the charge-type SAR ADC becomes the first choice of the universal ADC in the SOC system.
In order to meet the application requirements of a universal ADC for single-ended and differential applications, a common processing method is to make the ADC into differential sampling, connect a differential input of the ADC to an output of a fully differential VGA (variable gain amplifier), and configure the VGA into single-ended input application or differential input application, thereby implementing the single-ended differential application switching of the ADC. The processing method has high requirement on the VGA in front of the ADC input end, the VGA consumes relatively large power consumption and occupies a large area, and in order to save the VGA at the front end of the ADC, a series of processing can be carried out on a sampling switch and a capacitor array, so that the requirements of single-ended application and differential application of the general ADC are met.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in the prior art, the VGA is configured to be single-ended input application or differential input application, so that the single-ended differential application switching of the ADC is realized, and this processing method has a high requirement on the VGA in front of the input end of the ADC, and the VGA consumes relatively large power consumption and occupies a large area.
The technical scheme for solving the technical problems is as follows: a successive approximation analog-to-digital converter comprising: the sampling switch circuit, the charge redistribution type digital-to-analog converter, the dynamic comparator and the SAR logic circuit are sequentially connected in series; the single-end application driving source is connected with the sampling switch circuit; the charge redistribution type digital-to-analog converter consists of a P-end capacitor array, an N-end capacitor array and a reference driving reverser; the P-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit; the N-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit.
The invention has the beneficial effects that: the sampling switch and the capacitor array are processed in the mode, so that the occupied area is reduced, the symmetry of a sampling network can be ensured in single-ended application and differential application, the linearity of a sampling signal is improved, the achievable precision of an ADC (analog-to-digital converter) is further improved, and the power consumption is reduced.
On the basis of the technical scheme, the invention can be further improved as follows.
Furthermore, the N-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is also connected with the sampling switch circuit.
Further, the sampling switch circuit comprises a first switch, a second switch, a third switch and a fourth switch, wherein one end of the first switch is used as a vip input end, the other end of the first switch is connected with a vp input end of the dynamic comparator, one end of the second switch is used as a vin input end, the other end of the second switch is connected with a vn input end of the dynamic comparator, one end of the third switch is connected with an output end of the single-ended application driving source, the other end of the third switch is connected with a vn input end of the dynamic comparator, one end of the fourth switch is used as a vip input end, and the other end of the fourth switch is connected with a switch array of the N-end capacitor array bottom plate.
Further, a switch array of an upper electrode plate of the P-end capacitor array is connected with a vp input end of the dynamic comparator, a switch array of a lower electrode plate of the P-end capacitor array is connected with the reference driving reverser, and an output end of the reference driving reverser is connected with the SAR logic circuit.
Further, the switch array of the upper electrode plate of the N-end capacitor array is connected with the vn input end of the dynamic comparator, and the switch array of the lower electrode plate of the N-end capacitor array is connected with the reference driving reverser.
Further, the P, N end capacitor array includes: the switch array of the upper polar plate, the capacitor array and the switch array of the lower polar plate are sequentially connected in series.
Adopt above-mentioned further beneficial effect: meanwhile, the differential symmetry of the sampling network in differential and single-ended applications is ensured, and the linearity of the sampling signal is improved.
Furthermore, the switch array is at least formed by connecting two switches in parallel, and the capacitor array is at least formed by connecting two capacitors in parallel.
Further, the switch array of the lower polar plate in the N-end capacitor array comprises at least two alternative switches, each alternative switch comprises an A switch and a B switch, the A switch is connected with the fourth switch, and the B switch is connected with the input end of the reference driving reverser.
The above further advantageous effects: the switching between single-ended and differential applications can be effectively realized.
On the basis of the technical scheme, the invention also comprises an application switching method of the successive approximation type analog-digital converter, and the application switching method comprises the following steps:
s1, in the sampling stage, part of switches in the sampling switch circuit are closed and part of switches are opened, and the capacitor array samples by closing or opening the switches of the switch array in the charge redistribution type digital-to-analog converter;
and S2, after the sampling stage is finished, the switch of the sampling switch circuit is disconnected, and the SAR logic circuit controls the output of the reference driving inverter to judge the code word of the analog-digital converter by closing or opening the switch in the charge redistribution type digital-analog converter.
Has the advantages that: the power consumption is reduced, the application area is reduced, the linearity of a sampling signal is improved, and the fact that the single-ended application and the differential application can share the same SAR logic is guaranteed.
Further, in step S1, the switching method of the differential application specifically includes:
in the sampling stage, a first switch and a second switch in the sampling switch circuit are closed, a third switch and a fourth switch are opened, switch arrays in the P-end capacitor array are closed, a switch array of an upper electrode plate in the N-end capacitor array is closed, a switch array B of a switch array of a lower electrode plate is closed, a switch A is opened, and at the moment, the capacitor arrays at the P, N end are all sampled by the upper electrode plate.
Further, in step S1, the switching method of the single-ended application specifically includes:
in the sampling stage, an input signal is input from a vip end, a first switch, a third switch and a fourth switch are closed, a second switch is opened, switch arrays in a P-end capacitor array are all closed, an upper electrode plate switch array in an N-end capacitor array is closed, a lower electrode plate switch array A is closed, a switch B is opened, the P-end capacitor array samples an upper electrode plate, and the N-end capacitor array samples a lower electrode plate.
Drawings
FIG. 1 is a schematic diagram of a successive approximation type ADC according to the present invention;
FIG. 2 is a schematic diagram of a successive approximation type ADC according to the present invention;
FIG. 3 is a flow chart of a method for switching between successive approximation type ADC applications according to the present invention;
FIG. 4 is a schematic diagram of a partial structure of an equivalent sampling network during single-ended application switching according to the present invention;
FIG. 5 is a schematic diagram of a partial structure of an equivalent sampling network during switching of differential applications;
FIG. 6 is a schematic diagram of the conversion logic timing of the switched successive approximation analog-to-digital converter for single-ended and differential applications according to the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1 and 2, a successive approximation type analog-to-digital converter includes: the sampling switch circuit, the charge redistribution type digital-to-analog converter, the dynamic comparator and the SAR logic circuit are sequentially connected in series; the single-end application driving source is connected with the sampling switch circuit; the charge redistribution type digital-to-analog converter consists of a P-end capacitor array, an N-end capacitor array and a reference driving reverser; the P-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit; the N-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit.
The sampling switch circuit comprises a first switch, a second switch, a third switch and a fourth switch SSWP2, wherein one end of the first switch is used as a vip input end, the other end of the first switch is connected with a vp input end of the dynamic comparator, one end of the second switch is used as a vin input end, the other end of the second switch is connected with a vn input end of the dynamic comparator, one end of the third switch is used as an output end of the single-ended application driving source, the other end of the third switch is connected with a vn input end of the dynamic comparator, one end of the fourth switch is used as a vip input end, and the other end of the fourth switch is connected with a switch array of the N-end capacitor array bottom plate.
The switch array of the upper electrode plate of the P-end capacitor array is connected with the vp input end of the dynamic comparator, the switch array of the lower electrode plate of the P-end capacitor array is connected with the reference driving reverser, and the output end of the reference driving reverser is connected with the SAR logic circuit.
The switch array of the upper electrode plate of the N-end capacitor array is connected with the vn input end of the dynamic comparator, and the switch array of the lower electrode plate of the N-end capacitor array is connected with the reference driving reverser or the fourth switch. The input end of the switch array of the upper polar plate of the P-end capacitor array is connected with the second switch in parallel and then connected with the vp input end of the dynamic comparator; the input end of the switch array of the upper polar plate of the N-end capacitor array is connected with the first switch in parallel and then connected with the vn input end of the dynamic comparator.
P, N the end capacitor array includes: the switch array of the upper polar plate, the capacitor array and the switch array of the lower polar plate are sequentially connected in series. The switch array is at least connected in parallel by two switches, and the capacitor array is at least connected in parallel by two capacitors. The switch array of the lower polar plate in the N-end capacitor array comprises at least two alternative switches, each alternative switch comprises an A switch and a B switch, the A switch is connected with the fourth switch, and the B switch is connected with the input end of the reference driving reverser.
As shown in fig. 3, an application switching method of a successive approximation type analog-to-digital converter includes the steps of:
s1, in the sampling stage, part of switches in the sampling switch circuit are closed and part of switches are opened, and the capacitor array samples by closing or opening the switches of the switch array in the charge redistribution type digital-to-analog converter;
and S2, after the sampling stage is finished, the switch of the sampling switch circuit is disconnected, and the SAR logic circuit controls the output of the reference driving inverter to judge the code word of the analog-digital converter by closing or opening the switch in the charge redistribution type digital-analog converter.
In step S1, the switching method of the differential application specifically includes: in the sampling stage, a first switch and a second switch in the sampling switch circuit are closed, a third switch and a fourth switch are opened, the sum of the switch arrays in the P-end capacitor array is closed, the switch array of the upper electrode plate in the N-end capacitor array is closed, the switch array B of the lower electrode plate in the N-end capacitor array is closed, the switch A is opened, and at the moment, the capacitor arrays at the P, N end are all sampled by the upper electrode plate.
In step S1, the method for switching single-ended applications specifically includes: in the sampling stage, an input signal is input from a vip end, a first switch, a third switch and a fourth switch are closed, a second switch is opened, the sum of the switch arrays in a P-end capacitor array is closed, an upper electrode plate switch array in an N-end capacitor array is closed, an A switch of a lower electrode plate switch array is closed, a B switch is opened, the P-end capacitor array samples an upper electrode plate, and the N-end capacitor array samples a lower electrode plate.
The SAR logic circuit controls the output of a reference driving reverser connected to the lower polar plate of the P-end capacitor array to be power voltage and controls the output of a reference driving reverser connected to the lower polar plate of the N-end capacitor array to be power voltage at the initial stage of code word judgment; in the code word judging stage after the sampling stage, the first clock cycle does not do any operation, and the second clock cycle starts the judgment of the MSB.
When the ADC is applied in a single end, the first clock cycle of the ADC code word judging stage is used for establishing the voltage of the vn input end of the dynamic comparator.
The technical principle is explained as follows: if the input signal to the ADC is a differential pair of signals, the corresponding v ip and v in can be expressed as
vip＝VCM+VDM
vin＝VCM-VDM
VCM is a common-mode signal of differential input, VDM is a differential-mode signal of differential input, and the differential input signals are added to obtain
vip+vin＝2VCM
Thus, from one of the common mode signal and the differential signal, the other of the differential signals is obtained, which can be expressed as
vin＝2VCM-vip
If the common-mode signal is chosen to be half the supply voltage, i.e. if the common-mode signal is chosen to be half the supply voltage
VCM＝VDD/2
Then there is
vin＝2VCM-vip＝VDD-vip
For differential application of ADC, the corresponding equivalent sampling network is shown in FIG. 4, and in the sampling phase, the signals at the input ends of the comparators are respectively
vp＝vip
vn＝vin
In the initial stage of code word judgment, because the voltage of the lower electrode plate of the capacitor in the capacitor array is kept unchanged, namely the capacitor in the capacitor array is not overturned any more, the method can be obtained by the charge conservation principle,
vp＝vip
vn＝vin
for single-ended application of the ADC, the corresponding equivalent sampling network is as shown in fig. 5, assuming that the lower plate of the N-end capacitor array is connected to GND in the default state of the SAR logic, and in the sampling stage, the signals at the input end of the comparator are respectively GND
vp＝vip
vn＝VDD
In the initial stage of code word judgment, the lower plate voltage of the capacitor in the P-end capacitor array is kept unchanged, the lower plate voltage of the capacitor in the N-end capacitor array is switched to GND (ground potential), and the charge conservation principle can be used for obtaining the voltage of the lower plate of the capacitor in the N-end capacitor array
(VDD-vip)×2N-1×C＝(vn-0)×2N-1×C
Namely, it is
vp＝vip
vn＝VDD-vip＝2VCM-vip＝vin
That is, by switching, when the ADC is applied in a single end, the input voltage of the comparator is equivalent to that in a differential application in the initial stage of the codeword conversion, and the same SAR logic can be shared.
For single-ended application of the ADC, if the lower plate of the N-end capacitor array is connected with VDD in the default state of SAR logic, then in the sampling stage, the signals at the input end of the comparator are respectively VDD
vp＝vip
vn＝GND
In the initial stage of code word judgment, the lower plate voltage of the capacitor in the P-end capacitor array is kept unchanged, the lower plate voltage of the capacitor in the N-end capacitor array is switched to GND (ground potential), and the charge conservation principle can be used for obtaining the voltage of the lower plate of the capacitor in the N-end capacitor array
(0-vip)×2N-1×C＝(vn-VDD)×2N-1×C
Namely, it is
vp＝vip
vn＝VDD-vip＝2VCM-vip＝vin
When the ADC is applied in a single end, because the N-end capacitor array is used for sampling a bottom plate, the voltage at the vn input end of the comparator cannot be immediately established to a desired value vi N in the initial stage of codeword judgment, and therefore the corresponding SAR logic needs to be slightly modified.
Fig. 6 shows the SAR logic timing sequence applicable to switching between single-ended and differential applications of the ADC according to the present invention, compared to the conventional SAR logic, in the codeword decision stage after the sampling stage, no operation is performed in the first clock cycle, and the decision of the MSB (most significant bit) is started in the second clock cycle. For single-ended application of the ADC, the first clock cycle of the codeword decision stage is used for the establishment of the comparator vn input voltage. For the differential application of the ADC, the first clock cycle of the codeword decision stage is a waiting cycle, which has no substantial meaning, and the purpose is only that the single-ended application of the ADC and the differential application can share the same set of SAR logic.
In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (9)
1. A successive approximation analog-to-digital converter, comprising: the sampling switch circuit, the charge redistribution type digital-to-analog converter, the dynamic comparator and the SAR logic circuit are sequentially connected in series; the single-end application driving source is connected with the sampling switch circuit; the charge redistribution type digital-to-analog converter consists of a P-end capacitor array, an N-end capacitor array and a reference driving reverser; the P-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit; the N-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is connected with the SAR logic circuit;
the P, N end capacitor array includes: the switch array of the upper polar plate, the capacitor array and the switch array of the lower polar plate are sequentially connected in series; the switch array is at least formed by connecting two switches in parallel, and the capacitor array is at least formed by connecting two capacitors in parallel; the switch array of the lower polar plate in the N-end capacitor array comprises at least two alternative switches, each alternative switch comprises an A switch and a B switch, the A switch is connected with the fourth switch, and the B switch is connected with the input end of the reference driving reverser.
2. A successive approximation type analog-to-digital converter according to claim 1,
the N-end capacitor array is connected with the reference driving reverser in series, and the output end after the series connection is also connected with the sampling switch circuit.
3. The successive approximation type analog-to-digital converter according to claim 1, wherein the sampling switch circuit comprises a first switch, a second switch, a third switch and a fourth switch, wherein one end of the first switch is used as a vip input end, the other end of the first switch is connected with a vp input end of the dynamic comparator, one end of the second switch is used as a vin input end, the other end of the second switch is connected with a vn input end of the dynamic comparator, one end of the third switch is connected with an output end of the single-ended application driving source, the other end of the third switch is connected with a vn input end of the dynamic comparator, one end of the fourth switch is used as a vip input end, and the other end of the fourth switch is connected with a switch array of.
4. The successive approximation type analog-digital converter according to claim 1, wherein the switch array of the upper plate of the P-end capacitor array is connected with the vp input end of the dynamic comparator, the switch array of the lower plate of the P-end capacitor array is connected with the reference driving inverter, and the output end of the reference driving inverter is connected with the SAR logic circuit.
5. A successive approximation analog-to-digital converter according to claim 2 or 3, wherein the switch array of the upper plate of the N-terminal capacitor array is connected to the vn input terminal of the dynamic comparator, and the switch array of the lower plate of the N-terminal capacitor array is connected to the reference driving inverter.
6. A successive approximation type analog-digital converter according to claim 3 or 4, characterized in that the input end of the switch array of the upper plate of the P-end capacitor array is connected in parallel with the first switch and then connected with the vp input end of the dynamic comparator; and the input end of the switch array of the upper polar plate of the N-end capacitor array is connected with the second switch in parallel and then connected with the vn input end of the dynamic comparator.
7. An application switching method using the successive approximation type analog-to-digital converter according to any one of claims 1 to 6, the application switching method comprising the steps of:
s1, in the sampling stage, part of switches in the sampling switch circuit are closed and part of switches are opened, and the capacitor array samples by closing or opening the switches of the switch array in the charge redistribution type digital-to-analog converter;
and S2, after the sampling stage is finished, the switch of the sampling switch circuit is disconnected, and the SAR logic circuit controls the output of the reference driving inverter to judge the code word of the analog-digital converter by closing or opening the switch in the charge redistribution type digital-analog converter.
8. The method of claim 7, wherein in step S1, the method of switching the differential application specifically includes:
in the sampling stage, a first switch and a second switch in the sampling switch circuit are closed, a third switch and a fourth switch are opened, switch arrays in the P-end capacitor array are closed, a switch array of an upper electrode plate in the N-end capacitor array is closed, a switch array B of a switch array of a lower electrode plate is closed, a switch A is opened, and at the moment, the capacitor arrays at the P, N end are all sampled by the upper electrode plate.
9. The method of claim 7, wherein in step S1, the method of switching the single-ended application specifically includes:
in the sampling stage, an input signal is input from a vip end, a first switch, a third switch and a fourth switch are closed, a second switch is opened, switch arrays in a P-end capacitor array are all closed, an upper electrode plate switch array in an N-end capacitor array is closed, a lower electrode plate switch array A is closed, a switch B is opened, the P-end capacitor array samples an upper electrode plate, and the N-end capacitor array samples a lower electrode plate.
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| CN114448436A (en) * | 2022-02-10 | 2022-05-06 | 芯海科技（深圳）股份有限公司 | ADC circuit and control method thereof |
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| CN104158546A (en) * | 2014-08-22 | 2014-11-19 | 深圳市芯海科技有限公司 | ADC (Analog to Digital Converter) circuit adopting single-ended conversion successive approximation structure |
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