CN104158546A - ADC (Analog to Digital Converter) circuit adopting single-ended conversion successive approximation structure - Google Patents
ADC (Analog to Digital Converter) circuit adopting single-ended conversion successive approximation structure Download PDFInfo
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Abstract
The invention discloses an ADC (Analog to Digital Converter) circuit adopting a single-ended conversion successive approximation structure. The ADC circuit comprises a capacitive conversion array, a common-mode voltage storage capacitor, a common-mode voltage input end, a comparator, an SAR (Successive Approximation) control logic and a multiplexer switch, wherein upper pole plates of all capacitors are connected together, and lower pole plates are respectively connected to a plurality of input sources through a multi-way analog selector switch; the multiplexer switch is connected to a negative end of an input signal and a negative end of reference voltage, the SAR control logic controls the multiplexer switch, so that the lower pole plate of the common-mode voltage storage capacitor is connected to the negative end of the input signal in a sampling stage, and is connected to the negative end of the reference voltage in a conversion stage at the end of sampling. According to the ADC circuit, a system detuning problem caused by uneven signal and chip reference ground planes is effectively eliminated without increasing the cost of a chip and a system, so that accuracy of measurement is improved.
Description
Technical field
The present invention relates to integrated circuit, especially for digital to analog converter (ADC) circuit of systematic survey.
Background technology
When digital to analog converter (ADC) chip is used for measuring, be generally divided into single-ended and two kinds of input pattern signals of difference.Single-ended connection be one end reference of fixedly connecing chip (or ADC reference voltage negative terminal), another termination input signal, therefore ADC input only has one end; This connection is that the negative terminal of hypothesis input signal is also with reference to ground.The connection of difference is that the positive and negative terminal of signal all accesses ADC input as input signal, therefore ADC input is two ends.Corresponding to single-ended input and difference input, ADC internal conversion mode is also divided into single-ended conversion and differential conversion.Single-ended conversion has advantages of that area is little, low in energy consumption, but also has easily and be disturbed, and lacks of proper care greatly and is not easy the shortcomings such as elimination; Differential conversion has excellent symmetry, and common-mode noise is had to good restraint, also can eliminate well the impact of various non-ideal factors in transfer process, and such as switch-charge injection, clock feedthrough etc. are lacked of proper care little and are easy to process; But its shortcoming is area, large, corresponding power consumption is also large.In a lot of application, for single-ended signal, generally adopt the mode of single-ended input to utilize single-ended conversion ADC to measure.The prerequisite that this method exists is that the reference ground of signal and the reference ground of chip are flat.But sometimes this prerequisite is invalid, for example, in a kind of application of power-supply management system, due to the electric current that signal ground loop can be flow through ampere level and change, causing ground level is non-flat forms.Measure the ground of chip ADC and the potential difference of may exist～10mV of signal ground, this is equivalent to bring a unbalance of system to the measurement of ADC, cause measuring inaccurate, even when input signal amplitude itself just compared with hour, for example <10mV, this unbalance of system is equivalent to the measurement to ADC and has brought a dead band, has a strong impact on the accuracy of measurement.Conventionally ADC is inner can be with mistuning calibration function mechanism, is the offset error of ADC itself but alignment mechanism mainly tackles, and for unbalance of system, these internal mechanisms are helpless.Utilize the ADC of difference input and the differential conversion resolution system imbalance of having an opportunity, but can increase area and the power consumption of ADC, be unfavorable for reducing costs.
Patent application 201310522054X puts forward a kind of gradually-appoximant analog-digital converter and control method of capacitor array type, this transducer specifically comprises sampling hold circuit, comparator and control logic, and sampling hold circuit comprises sampling switch and capacitor array digital to analog converter.The present invention is by changing the connected mode of capacitor array, at switch for the first time, for the second time and for the third time in course of action, not consumed energy of capacitor array analog to digital converter, and after course of action also obviously compared with prior art in the energy of capacitor array Analog to Digital Converter consumes little, and can be generalized in the capacitor array type gradually-appoximant analog-digital converter of any resolution, it is wider that it is suitable for, and energy consumption is less, has more practicality.But above-mentioned patent application, its effect and difference input be less than too large difference, and its capacitor array is upper and lower relation and is connected to the positive and negative terminal of comparator, has in fact just improved the measurement accuracy of ADC itself, and internal mechanism is remained to helpless.
Summary of the invention
For addressing the above problem, the object of the present invention is to provide a kind of single-ended conversion successively to approach the adc circuit of structure, this circuit can not increase under the prerequisite of cost and power consumption, eliminates the unbalance of system of measuring, and improves the accuracy of measuring.
Another object of the present invention is to provide a kind of single-ended conversion successively to approach the adc circuit of structure, and this circuit structure is simple and easy to implement, and does not increase chip and system cost.
For achieving the above object, technical scheme of the present invention is as follows.
A kind of single-ended conversion successively approaches the adc circuit of (SAR) structure, it is characterized in that comprising:
Electric capacity conversion array, has input signal sampling and digital-to-analogue conversion (DAC) function, comprises multiple electric capacity; The top crown of all electric capacity links together, and bottom crown can be connected to multiple input sources by a multi-channel analog selector switch separately,
Common-mode voltage storage capacitance, for samples storage common-mode voltage;
Common-mode voltage input, comprises two switches, for electric capacity conversion array electric capacity top crown and common-mode voltage storage capacitance top crown being connected to common-mode voltage in sample phase;
Comparator, an input termination capacitor conversion array top crown, another input termination common-mode voltage storage capacitance top crown, compares two ends size and exports comparative result to SAR control logic;
SAR control logic, multidiameter option switch in control capacitance conversion array and common-mode voltage input end switch complete the sampling of input signal and common-mode voltage, and successively complete the conversion of analog to digital, the digital code value after output conversion according to comparator results control;
Also comprise a multidiameter option switch at the bottom crown of common-mode voltage storage capacitance, described multidiameter option switch connects input signal negative terminal and reference voltage negative terminal, this multidiameter option switch of SAR control logic control makes the bottom crown of common-mode voltage storage capacitance connect the negative terminal of input signal in sample phase, and the translate phase after sampling finishes connects reference voltage negative terminal.
Described input, comprises reference voltage anode, reference voltage negative terminal and input signal anode.
The reference ground that above-mentioned reference voltage negative terminal is ADC.
Further, described common-mode voltage storage capacitance, its size is 90%～110% of electric capacity conversion array total capacitance size.
Described electric capacity conversion array adopts cascade structure, is divided into MSB electric capacity conversion array and two parts of LSB electric capacity conversion array, and the convergent-divergent electric capacity of connecting between described two parts.
The reference ground that described input signal negative terminal is input signal.
Described common-mode voltage is 1/2 of supply voltage.
Single-ended conversion of the present invention successively approaches the adc circuit of (SAR) structure, can not increase on the basis of chip and system cost, effectively eliminate the unbalance of system problem of bringing due to signal and chip reference horizontal plane of manufacturing injustice, improve the accuracy of measuring.
Brief description of the drawings
Fig. 1 is the circuit diagram that the present invention implements.
Fig. 2 is the circuit theory diagrams of the present invention while being implemented on measuring system.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Referring to accompanying drawing 1, be depicted as 4 adc circuits that successively approach, this circuit comprised realize sampling and digital-to-analogue voltage conversion function electric capacity conversion array module DAC, comparator module CMP1, common-mode voltage storage capacitance Cm, common-mode voltage input SWCM1 SWCM2, negative terminal sampling switch SWN, SAR control logic SAR_Logic1; Wherein electric capacity top crown output changing voltage in electric capacity conversion array module DAC, connects comparator C MP1 anode; Common-mode voltage input end capacitor Cm top crown connects comparator negative terminal; Comparator output meets SAR control logic SAR_Logic1; Sequencing control DAC module is controlled in SAR_Logic1 output and SWN switch is sampled, and according to comparator results control voltage transitions, the positive terminal voltage of comparator can successively be approached to negative terminal voltage, finally exports transformation result OUT.
In accompanying drawing 1, DAC module adopts cascade structure, and MSB array comprises capacitor C 3, C2; LSB array comprises capacitor C 1, C0 and Terminal Capacitance C00; Between MSB array and LSB array, connect by convergent-divergent capacitor C s; C3～C00 is connected to different voltage by multidiameter option switch SW3～SW00 respectively, comprise anode with reference to VREFP, negative terminal with reference to VREFN, anode input INP, but Terminal Capacitance C00 is fixedly attached to VREFN; If specific capacitance is Cu, C3=2Cu, C2=Cu, C1=2Cu, C0=Cu, C00=Cu, and Cs=4Cu/3; Sample phase, SWCM1 and SWCM2 closure, comparator C MP1 two inputs all meet common-mode voltage VCM; Switch SW 3～SW0 gets to VINP end, and input is sampled; Negative terminal SWN gets to VINN end, and input signal negative terminal is sampled; After sampling finishes, enter the change-over period, SWCM1 and SWCM2 disconnect, and SW2～SW0, SWN get to VREFN end simultaneously, and SW3 gets to VREFP end.Now, the voltage of comparator anode can change, and comparator is according to the Voltage-output comparative result at input two ends.When comparator is output as timing, while arrival, SAR_Logic1 controlled SW3 and got to VREFN the next change-over period, and SW2 gets to VREFP simultaneously, the like, until SW0 switch also relatively completes.The state of SW3～SW0 switch is exactly the output of SAR_Logic1.Owing to having introduced VINN in sample phase, so the voltage of final ADC conversion is VINP-VINN, instead of VINP.When VINN is during corresponding to a unbalance of system, this ADC just can give unbalance of system to eliminate.
Participate in accompanying drawing 2, be depicted as the present invention and be applied to the measuring system of eliminating unbalance of system, wherein V is that power supply, ADC1 are that ADC, the DC-DC with elimination unbalance of system function shown in accompanying drawing 1 is a switch power module, Load1 is the load of DC-DC1, voltage VOU of DC-DC1 output is to load Load1 power supply, and RS3～RS1 is respectively that Load1, DC-DC1 and ADC1 arrive the systematically cabling dead resistance of GND.System, for the electric current of sensing lead Load1, seals in a small resistor Rsen in its earth-return, and ADC1 measures AINP, and Load1 electric current is AINP/Rsen; But due to the existence of RS, add large (～the 1A) of electric current of Load1, make AINN and systematically between GND, have significant potential difference, this is unbalance of system; Unbalance of system exists and makes the actual current of electric current that AINP/Rsen calculates and Load1 inconsistent, causes measuring inaccurate.Therefore, ADC1 adopts the ADC that eliminates unbalance of system function that has shown in the drawings, and its anode connects measuring system with reference to REFP with reference to VREFP, and negative terminal is with reference to VREFN welding system ground GND, and the VINP of anode input simultaneously meets AINP, and negative terminal input VINN meets AINN; The output of ADC1 is corresponding to voltage difference AINP-AINN like this, and (AINP-AINN)/Rsen is exactly that we want the Load1 electric current of measuring.
In a word, the foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. single-ended conversion successively approaches an adc circuit for structure, it is characterized in that comprising:
Electric capacity conversion array, has input signal sampling and digital-to-analogue conversion (DAC) function, comprises multiple electric capacity; The top crown of all electric capacity links together, and bottom crown can be connected to multiple input sources by a multi-channel analog selector switch separately,
Common-mode voltage storage capacitance, for samples storage common-mode voltage;
Common-mode voltage input, comprises two switches, for electric capacity conversion array electric capacity top crown and common-mode voltage storage capacitance top crown being connected to common-mode voltage in sample phase;
Comparator, an input termination capacitor conversion array top crown, another input termination common-mode voltage storage capacitance top crown, compares two ends size and exports comparative result to SAR control logic;
SAR control logic, multidiameter option switch in control capacitance conversion array and common-mode voltage input end switch complete the sampling of input signal and common-mode voltage, and successively complete the conversion of analog to digital, the digital code value after output conversion according to comparator results control;
Also comprise a multidiameter option switch at the bottom crown of common-mode voltage storage capacitance, described multidiameter option switch connects input signal negative terminal and reference voltage negative terminal, this multidiameter option switch of SAR control logic control makes the bottom crown of common-mode voltage storage capacitance connect the negative terminal of input signal in sample phase, and the translate phase after sampling finishes connects reference voltage negative terminal.
2. single-ended conversion as claimed in claim 1 successively approaches the adc circuit of structure, it is characterized in that described input, comprises reference voltage anode, reference voltage negative terminal and input signal anode.
3. single-ended conversion as claimed in claim 2 successively approaches the adc circuit of structure, it is characterized in that the reference ground that above-mentioned reference voltage negative terminal is ADC.
4. single-ended conversion as claimed in claim 1 successively approaches the adc circuit of structure, it is characterized in that described common-mode voltage storage capacitance, and its size is 90%～110% of electric capacity conversion array total capacitance size.
5. single-ended conversion as claimed in claim 1 successively approaches the adc circuit of structure, it is characterized in that described electric capacity conversion array adopts cascade structure, be divided into MSB electric capacity conversion array and two parts of LSB electric capacity conversion array, and the convergent-divergent electric capacity of connecting between described two parts.
6. single-ended conversion as claimed in claim 1 successively approaches the adc circuit of structure, it is characterized in that the reference ground that described input signal negative terminal is input signal.
7. single-ended conversion as claimed in claim 1 successively approaches the adc circuit of structure, it is characterized in that described common-mode voltage is 1/2 of supply voltage.
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| CN104579348A (en) * | 2015-01-15 | 2015-04-29 | 北京华强智连微电子有限责任公司 | Successive approximation type ADC structure and algorithm |
| CN105471432A (en) * | 2015-11-19 | 2016-04-06 | 成都华微电子科技有限公司 | Low power consumption charge redistribution capacitance array circuit |
| CN105897272A (en) * | 2016-03-30 | 2016-08-24 | 豪威科技(上海)有限公司 | Successive approximation register analog-to-digital converter and control method thereof |
| CN106452440A (en) * | 2016-04-26 | 2017-02-22 | 芯海科技（深圳）股份有限公司 | Low-power-consumption successive approximation analog-to-digital converter circuit |
| CN107395205A (en) * | 2017-06-22 | 2017-11-24 | 西安电子科技大学 | Gradual approaching A/D converter based on asymmetric differential capacitance array |
| CN107968656A (en) * | 2016-10-20 | 2018-04-27 | 国民技术股份有限公司 | A kind of successive approximation simulates digital quantizer and its using switching method |
| CN109104193A (en) * | 2018-10-30 | 2018-12-28 | 华大半导体有限公司 | A kind of successive approximation modulus conversion circuit and its operation method |
| CN109245771A (en) * | 2018-09-19 | 2019-01-18 | 西安电子科技大学 | A kind of successive approximation digital analog converter |
| CN109379082A (en) * | 2018-09-29 | 2019-02-22 | 湖南品腾电子科技有限公司 | A kind of gradually-appoximant analog-digital converter |
| CN109639282A (en) * | 2018-10-25 | 2019-04-16 | 西安电子科技大学 | A kind of low-power consumption SYN register type successive approximation analog to digital C of single ended input |
| CN109818615A (en) * | 2019-01-31 | 2019-05-28 | 芯海科技（深圳）股份有限公司 | The control method of analog-digital converter |
| TWI661681B (en) * | 2018-01-03 | 2019-06-01 | 財團法人成大研究發展基金會 | Adc and an interfacing circuit adaptable thereto |
| CN111756379A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Capacitive SAR ADC |
| CN113452371A (en) * | 2020-03-25 | 2021-09-28 | 智原微电子(苏州)有限公司 | Successive approximation temporary storage type analog-digital converter and related control method |
| CN113612482A (en) * | 2021-10-08 | 2021-11-05 | 杭州优智联科技有限公司 | Single-ended successive approximation register type analog-to-digital converter circuit |
| CN117713820A (en) * | 2023-12-20 | 2024-03-15 | 灿芯半导体(上海)股份有限公司 | ADC lower polar plate sampling circuit |
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| CN104579348A (en) * | 2015-01-15 | 2015-04-29 | 北京华强智连微电子有限责任公司 | Successive approximation type ADC structure and algorithm |
| CN105471432A (en) * | 2015-11-19 | 2016-04-06 | 成都华微电子科技有限公司 | Low power consumption charge redistribution capacitance array circuit |
| CN105897272B (en) * | 2016-03-30 | 2019-07-23 | 豪威科技(上海)有限公司 | Successive approximation analog-digital converter and its control method |
| CN105897272A (en) * | 2016-03-30 | 2016-08-24 | 豪威科技(上海)有限公司 | Successive approximation register analog-to-digital converter and control method thereof |
| CN106452440A (en) * | 2016-04-26 | 2017-02-22 | 芯海科技（深圳）股份有限公司 | Low-power-consumption successive approximation analog-to-digital converter circuit |
| CN107968656A (en) * | 2016-10-20 | 2018-04-27 | 国民技术股份有限公司 | A kind of successive approximation simulates digital quantizer and its using switching method |
| CN107968656B (en) * | 2016-10-20 | 2021-08-20 | 国民技术股份有限公司 | Successive approximation type analog-digital converter and application switching method thereof |
| CN107395205A (en) * | 2017-06-22 | 2017-11-24 | 西安电子科技大学 | Gradual approaching A/D converter based on asymmetric differential capacitance array |
| CN107395205B (en) * | 2017-06-22 | 2020-06-19 | 西安电子科技大学 | Successive approximation type analog-digital converter based on asymmetric differential capacitor array |
| CN109995369A (en) * | 2018-01-03 | 2019-07-09 | 财团法人成大研究发展基金会 | Analog-to-digital converter and interface circuit suitable for analog-to-digital converter |
| TWI661681B (en) * | 2018-01-03 | 2019-06-01 | 財團法人成大研究發展基金會 | Adc and an interfacing circuit adaptable thereto |
| CN109995369B (en) * | 2018-01-03 | 2023-01-17 | 财团法人成大研究发展基金会 | Analog-to-digital converter and interface circuit suitable for analog-to-digital converter |
| CN109245771A (en) * | 2018-09-19 | 2019-01-18 | 西安电子科技大学 | A kind of successive approximation digital analog converter |
| CN109379082B (en) * | 2018-09-29 | 2023-12-26 | 长沙学院 | Successive approximation analog-to-digital converter |
| CN109379082A (en) * | 2018-09-29 | 2019-02-22 | 湖南品腾电子科技有限公司 | A kind of gradually-appoximant analog-digital converter |
| CN109639282B (en) * | 2018-10-25 | 2021-08-24 | 西安电子科技大学 | Single-ended input low-power-consumption synchronous register type successive approximation ADC |
| CN109639282A (en) * | 2018-10-25 | 2019-04-16 | 西安电子科技大学 | A kind of low-power consumption SYN register type successive approximation analog to digital C of single ended input |
| CN109104193A (en) * | 2018-10-30 | 2018-12-28 | 华大半导体有限公司 | A kind of successive approximation modulus conversion circuit and its operation method |
| CN109818615A (en) * | 2019-01-31 | 2019-05-28 | 芯海科技（深圳）股份有限公司 | The control method of analog-digital converter |
| CN111756379A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Capacitive SAR ADC |
| CN111756379B (en) * | 2019-03-27 | 2023-09-26 | 中芯国际集成电路制造(上海)有限公司 | Capacitive SAR ADC |
| CN113452371A (en) * | 2020-03-25 | 2021-09-28 | 智原微电子(苏州)有限公司 | Successive approximation temporary storage type analog-digital converter and related control method |
| CN113452371B (en) * | 2020-03-25 | 2023-07-04 | 智原微电子(苏州)有限公司 | Successive approximation register analog-to-digital converter and related control method |
| CN113612482A (en) * | 2021-10-08 | 2021-11-05 | 杭州优智联科技有限公司 | Single-ended successive approximation register type analog-to-digital converter circuit |
| CN117713820A (en) * | 2023-12-20 | 2024-03-15 | 灿芯半导体(上海)股份有限公司 | ADC lower polar plate sampling circuit |
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