CN113612482A

CN113612482A - Single-ended successive approximation register type analog-to-digital converter circuit

Info

Publication number: CN113612482A
Application number: CN202111172083.9A
Authority: CN
Inventors: 孟彦杰; 董宗宇
Original assignee: Hangzhou Youzhilian Technology Co ltd
Current assignee: Hangzhou Youzhilian Technology Co ltd
Priority date: 2021-10-08
Filing date: 2021-10-08
Publication date: 2021-11-05
Anticipated expiration: 2041-10-08
Also published as: CN113612482B

Abstract

The invention discloses a single-ended successive approximation register type analog-to-digital converter circuit, wherein an SAR ADC framework comprises a comparator, a first capacitor array coupled to a first input end in the comparator, a second capacitor array coupled to a second input end in the comparator and a controller coupled to an output end of the comparator; top plates of the first capacitor array and the second capacitor array can be coupled to the first input end and the second input end respectively; the bottom plates of the first capacitor array and the second capacitor array can be selectively coupled to a positive reference voltage and a negative reference voltage, and the bottom plates of the first capacitor array and the second capacitor array can be selectively coupled to a first input signal and a second input signal respectively based on a state switch; the first input terminal and the second input terminal are selectively coupleable to a third input signal and a fourth input signal, respectively, based on the state switch; the controller can control the positive and negative reference voltages to be selectively coupled to the bottom plates of the first and second capacitive arrays.

Description

Single-ended successive approximation register type analog-to-digital converter circuit

Technical Field

The embodiment of the invention relates to the technical field of integrated circuit design, in particular to a single-ended successive approximation register analog-to-digital converter circuit and a single-ended successive approximation register analog-to-digital converter architecture.

Background

Analog-to-Digital converters (ADCs) are widely used in a variety of integrated circuit systems, such as medical systems, audio systems, test and measurement devices, communication systems, and image and video systems. The most common ADC architectures include flash (flash) ADCs, pipeline (pipeline) ADCs, and Successive Approximation Register (SAR) ADCs. In practical applications, the SAR ADC is usually used in a system with a limited power supply, such as a portable device, because the SAR ADC architecture consumes less power than the flash ADC and pipeline ADC.

However, in a general SAR ADC architecture, an amplifier capable of converting a single-ended signal into a differential signal is usually disposed at a front end of the ADC architecture, and the differential signal output by the amplifier can ensure that a comparator and a sampling circuit in the ADC architecture operate at a proper voltage operating point.

However, the amplifier for converting a single-ended signal into a differential signal at present usually adopts a negative feedback operational amplifier architecture in a specific implementation process, and the architecture requires a circuit area and power consumption that are usually higher than those of the ADC architecture on the premise of some applicable requirements (such as low noise, high linearity, and the like), so that the implementation of deep submicron processing is not friendly, and the goal of low power consumption in the current System-on-a-Chip (SOC) product cannot be achieved.

Disclosure of Invention

Accordingly, embodiments of the present invention are directed to single-ended successive approximation register analog-to-digital converter circuits and architectures; the front end of the SAR ADC framework can be eliminated, an amplifier used for converting a single-ended signal into a differential signal can be eliminated, and the whole area and the power consumption of the circuit are reduced.

The technical scheme of the embodiment of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides an SAR ADC architecture suitable for an SAR ADC circuit of a single-ended successive approximation register type analog-to-digital converter, where the SAR ADC architecture includes: a comparator, a first capacitor array coupled to a first input of the comparator, a second capacitor array coupled to a second input of the comparator, and a controller coupled to an output of the comparator; wherein the content of the first and second substances,

top plates of the first capacitor array and the second capacitor array are respectively coupled to the first input end and the second input end; the bottom plates of the first and second capacitive arrays can each be selectively coupled to a positive reference voltage signal and a negative reference voltage signal, the bottom plate of the first capacitive array can be selectively coupled to a first input signal based on a state switch; a bottom plate of the second capacitive array is selectively coupleable to a second input signal based on the state switch; the first input terminal is selectively coupleable to a third input signal based on the state switch, and the second input terminal is selectively coupleable to a fourth input signal based on the state switch; the controller can control the positive and negative reference voltage signals to be selectively coupled to the bottom plates of the first and second capacitive arrays.

In a second aspect, an embodiment of the present invention provides a single-ended successive approximation register analog-to-digital converter SAR ADC circuit, where the circuit includes: inputting a multiplexer and the SAR ADC architecture of the first aspect; wherein the input multiplexer is configured to receive a single-ended input signal Vi _ SE and input a single-ended signal VI _ ADC to the SAR ADC architecture.

The embodiment of the invention provides a single-ended successive approximation register analog-to-digital converter circuit and a framework; by designing the sampling circuit of the SAR ADC framework, a conversion module from a single-ended signal to a differential signal is eliminated, so that the processing of the single-ended signal VI _ ADC can be completed only through the SAR ADC framework, the requirements of high signal-to-noise ratio (SNR) and stray-free dynamic range (SFDR) are met, and the circuit area and the power consumption are reduced.

Drawings

Fig. 1 is a schematic diagram of a SAR ADC circuit employed in the conventional scheme.

Fig. 2 is a schematic diagram of a single-ended SAR ADC circuit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of an SAR ADC according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of another SAR ADC architecture according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of another SAR ADC architecture according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

In the process of single-ended signal processing, for example, in the SAR ADC circuit shown in fig. 1, a single-ended signal to differential signal conversion module (e.g., the SE _ to _ Diff module shown in fig. 1) is generally added to a front end of the SAR ADC structure, so as to ensure that a Comparator (COMP) and a sampling circuit in the SAR ADC structure operate at a suitable voltage operating point, in detail, an input of the SAR ADC structure is generally a differential signal, and therefore the SE _ to _ Diff module is required to output a differential signal according to the input single-ended signal, such as the VIP _ ADC and the VIN _ ADC shown in fig. 1. Of course, it is understood that in the specific implementation process, the components in the circuit diagram shown in fig. 1 may further include at least an Input multiplexer (Input Mux) for providing an Input signal to the SE _ to _ Diff module, a Serial Peripheral Interface (SPI) for providing an Input control word (Input _ sel) to the Input Mux, a Timing Logic (Timing Logic) for providing Timing Logic to the circuit through a clock signal (CLK), a Bandgap reference Bandgap for providing a reference voltage signal (Vref) to the SAR ADC architecture, and a SAR Logic controller (SAR Logic) for receiving an output of SAR COMP. Based on the above components, the signals involved in the circuit diagram shown in fig. 1 may further include: the Input Mux includes a single-ended signal Vi _ SE Input to the Input Mux, a MISO signal, a MOSI signal, an SPI clock signal (SPI _ CLK), and an Analog control signal (Analog _ ctrl) provided to the SPI, and VDD for supplying power to each device in the circuit and a circuit common ground VSS, and may further include an output signal Dout of the SAR ADC architecture and an end-of-conversion signal EOC. In some examples, to complete all bit conversion, the voltage value of Vref is usually set according to Vref ≧ Vi _ SE (full scale), which is to be noted to mean the single-ended signal Vi _ SE that needs to be input to complete all bit conversion.

In view of the circuit diagram and the related descriptions shown in fig. 1, on one hand, the SE _ to _ Diff module in fig. 1 generally adopts a negative feedback operational amplifier structure in the conventional implementation process, but based on the dual requirements of full low noise and high linearity involved in the current radio frequency receiver of the wireless system, the negative feedback operational amplifier structure of the SE _ to _ Diff module occupies a larger area and higher power consumption in the circuit; in some examples, the SE _ to _ Diff modules may occupy more circuit area and consume more power than the ADC. Therefore, using the SE _ to _ Diff module in the rf receiving circuit is not favorable for the implementation of deep submicron technology, and cannot achieve the current goal of low power consumption for SOC products. On the other hand, based on the setting of Vref ≧ Vi _ SE (full scale), a higher power supply voltage is needed to generate a proper reference voltage VREF to realize the setting, so that the voltage domain is more complicated, and the power consumption is increased; therefore, the reliability requirement of deep submicron technology (such as Time Dependent Dielectric Breakdown (TDDB) or Bias Temperature Instability (BTI)) cannot be satisfied, and realizing high power supply voltage poses a great challenge.

In view of the above, embodiments of the present invention are expected to eliminate the SE _ to _ Diff module based on the circuit diagram shown in fig. 1, such as the single-ended SAR ADC circuit shown in fig. 2, where the Input multiplexer (Input Mux) receives the single-ended Input signal Vi _ SE and inputs the output Vi _ ADC to the SAR ADC architecture. By designing the sampling circuit in the SAR ADC architecture in the circuit shown in fig. 2, the processing of the single-ended Signal VI _ ADC can be completed only by the SAR ADC architecture itself, the requirements of high Signal-to-Noise Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) are met, and the circuit area and power consumption are reduced. Based on this, referring to fig. 3, it shows a SAR ADC architecture 3 suitable for a single-ended SAR ADC circuit provided in an embodiment of the present invention, including: a comparator 301, a first capacitor array 302 coupled to a first input VXP of the comparator 301 as indicated by the dashed box, a second capacitor array 303 coupled to a second input VXN of the comparator 301 as indicated by the dashed box, and a controller 304 coupled to an output of the comparator 301; wherein the content of the first and second substances,

the top plates of the first capacitor array 302 and the second capacitor array 303 can be coupled to a first input terminal and a second input terminal of the comparator 301, respectively; the bottom plates of the first capacitive array 302 and the second capacitive array 303 can each be selectively coupled to a positive reference voltage signal VREFP and a negative reference voltage signal VREFN, and further, the bottom plate of the first capacitive array 302 can be selectively coupled to a first input signal based on a state switch SAMP; the bottom plate of the second capacitor array 303 is selectively coupleable to a second input signal based on the state switch SAMP; the first input VXP of the comparator 301 is selectively coupleable to a third input signal based on the state switch SAMP, and the second input VXN of the comparator 301 is selectively coupleable to a fourth input signal based on the state switch SAMP; the controller 304 can control the positive reference voltage signal VREFP and the negative reference voltage signal VREFN to be selectively coupled to the bottom plates of the first capacitive array 302 and the second capacitive array 303.

For the SAR ADC architecture shown in fig. 3, in some possible implementations, the state switch SAMP is used to characterize an operating phase of the SAR ADC architecture, and in an embodiment of the present invention, the state switch is closed, that is, when SAMP =1, the sampling phase is performed; when the state switch is off, that is, when SAMP =0, the state switch is a transition stage after the sampling stage is ended. It should be noted that, in conjunction with the structure shown in fig. 3, the opening and closing of the state switch not only affects the signal types coupled to the bottom plates of the first capacitor array 302 and the second capacitor array 303, but also affects the signal types coupled to the first input terminal VXP and the second input terminal VXN of the comparator 301. Furthermore, in other possible implementations, the first capacitive array 302 and the second capacitive array 303 in the SAR ADC architecture shown in fig. 3 each include capacitors of different weights, such as the MSB capacitor, MSB-1 capacitor, MSB-2 capacitor … … LSB capacitor shown in the figure; in addition, each of the capacitor array 302 and the second capacitor array 303 includes an upper portion and a lower portion, and each portion includes capacitors with the same weight; in the first capacitor array 302, capacitors with the same weight in the upper part and the lower part are connected and coupled to the top plate of the first capacitor array 302, and the unconnected end between the capacitors is coupled to the bottom plate of the first capacitor array 302; the second capacitor array 303 is similar, capacitors with the same weight in the upper and lower parts are connected and coupled to the top plate of the second capacitor array 303, and the unconnected ends of the capacitors are coupled to the bottom plate of the second capacitor array 303.

In combination with the above implementation manner, in some examples, as in the Input signal bottom plate sampling scheme shown in fig. 4, the first Input signal is a single-ended Input signal Vi _ SE or a Vi _ ADC output by the Input multiplexer, because a difference between the two is only whether the Input Mux outputs the first Input signal or not and the difference is not processed by filtering or the like, for the SAR ADC architecture, Vi _ SE and Vi _ ADC may be considered to be the same or similar. The second input signal and the third input signal are both VFS/4; wherein VFS =2 (VREFP-VREFN); the fourth input signal is ground GND.

Based on the above example, in conjunction with fig. 4, when in the sampling phase, i.e., SAMP =1, the single-ended input signal Vi _ SE is coupled to the bottom plate of the first capacitor array 302, the top plate of the first capacitor array 302 is coupled to VFS/4, the bottom plate of the second capacitor array 303 is coupled to VFS/4, and the top plate of the second capacitor array 303 is grounded; when the sampling phase is finished and then the conversion phase is carried out, that is, the SAMP =0, all the bottom plate electrodes of the upper part of the first capacitor array 302 are connected to VREFP, and all the bottom plate electrodes of the lower part of the first capacitor array 302 are connected to VREFN; the upper and lower portions of the second capacitor array 303 are also connected to VREFP and VREFN, respectively. At this time, the input voltages of the first input terminal VXP and the second input terminal VXN of the comparator 301 are:

VXP = VREF_CM – (Vi_SE – VFS/4)

VXN = VREF_CM – (VFS/4 - 0)

where VREF _ CM represents the differential common mode voltage of the reference voltage VREF, specifically, VREF _ CM = (VREFP + VREFN)/2.

By the input voltage of the first input terminal VXP and the second input terminal VXN, the differential input voltage of the comparator 301 can be obtained as follows: VX _ diff = Vi _ SE-VFS/2.

It should be noted that, as can be known from analyzing the differential input voltage of the comparator 301, the SAR ADC architecture provided in the embodiment of the present invention can implement comparison between the input signal and VFS/2, and further implicitly implement conversion from a single-ended signal to a differential signal. In some preferred examples of practical applications, the above design of the SAR ADC architecture can be simplified by choosing an appropriate VFS/4 value, such as VFS/4= VREF _ CM.

Further, during the transition phase, comparator 301 activates the first comparison cycle based on the aforementioned VX _ diff, the comparison result determines the MSB, and controller 304 controls SAR timing logic to control first capacitor array 302 and second capacitor array 303 to perform the MSB-1 transition based on the result of the MSB. If MSB =1, the controller 304 switches the MSB capacitance connected to VREFP in the first capacitance array 302 to connection VREFN and the MSB capacitance connected to VREFN on the second capacitance array 303 to connection VREFP, so that the differential input voltage of the comparator 301 is then updated to: VX _ diff = Vi _ SE-VFS/4 and VFS/4= (VREFP-VREFN)/2, so that after the MSB-1 conversion is completed, the controller 304 continues to perform the subsequent conversion of the remaining bits to LSB according to the logic similar to that of MSB-1.

Continuing with fig. 4, VREFP =0.9V, VREFN =0V, and the reference voltage is set to the common mode voltage VREF _ CM = 0.45V. The input single-ended voltage (Vi _ SE) is 1.8V full scale. In the conventional scheme, since VREF = VREFP-VREFN is smaller than the full scale of the input single-ended voltage, correct conversion cannot be achieved. Unless the supply voltage is increased (at least more than 1.8V is required, typically at least up to 2V), for example so that VREFP = 1.8V. With the SAR ADC structure of the present invention, in combination with the above, it can be known that when operating at 1.8V or even lower (1.1V) supply voltage, the requirement for the reference voltage can be selected to be 0.9V instead of the 1.8V mentioned in the conventional scheme.

It can be understood that according to the above scheme, after the sampling phase of the input signal is finished, the conversion from the input single end to the differential can be effectively finished by using the reference voltage smaller than the input voltage. In addition, the SAR ADC architecture according to the embodiment of the present invention may be applied not only to a bottom plate sampling scheme, but also to a top plate sampling scheme in some examples, as shown in fig. 5, where the first input signal and the fourth input signal are VFS/4; the second input signal is ground, and the third input signal is a single-ended input signal Vi _ SE. The opening and closing of the SAMP corresponds to the sampling phase and the conversion phase, respectively.

For the top plate sampling scheme shown in fig. 5, the specific implementation process is similar to the bottom plate sampling scheme shown in fig. 4, and details thereof are not repeated in the embodiment of the present invention.

It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A SAR ADC architecture suitable for a single-ended successive approximation register analog-to-digital converter, SAR ADC, circuit, the SAR ADC architecture comprising: a comparator, a first capacitor array coupled to a first input of the comparator, a second capacitor array coupled to a second input of the comparator, and a controller coupled to an output of the comparator; wherein the content of the first and second substances,

2. The SAR ADC architecture of claim 1, wherein the state switch is configured to characterize an operating phase of the SAR ADC architecture, wherein the state switch is a sampling phase; the disconnection of the state switch is a conversion stage after the sampling stage is finished.

3. The SAR ADC architecture of claim 1, wherein the first capacitive array and the second capacitive array each comprise capacitors of different weights; the first capacitor array and the second capacitor array respectively comprise an upper part and a lower part, and each part comprises capacitors with the same weight; in the first capacitor array, capacitors with the same weight in the upper part and the lower part are connected and coupled to the top plate of the first capacitor array, and the unconnected end between the capacitors is coupled to the bottom plate of the first capacitor array; capacitors with the same weight in the upper part and the lower part of the second capacitor array are connected and coupled to the top plate of the second capacitor array, and the unconnected ends of the capacitors are coupled to the bottom plate of the second capacitor array.

4. The SAR ADC architecture of any of claims 1 to 3, wherein the first input signal is a single ended input signal Vi SE; the second input signal and the third input signal are both VFS/4; wherein VFS =2 (VREFP-VREFN), the VREFP representing the positive reference voltage signal, the VREFN representing the negative reference voltage signal; the fourth input signal is ground GND.

5. The SAR ADC architecture of claim 4, wherein during a sampling phase, the single-ended input signal Vi _ SE is coupled to a bottom plate of the first capacitor array, a top plate of the first capacitor array is coupled to VFS/4, a bottom plate of the second capacitor array is coupled to VFS/4, and a top plate of the second capacitor array is grounded; when the sampling phase is shifted to a conversion phase after the sampling phase is finished, all bottom pole plates at the upper part of the first capacitor array are connected to VREFP, and all bottom pole plates at the lower part of the first capacitor array are connected to VREFN; the upper and lower portions of the second capacitor array are also connected to VREFP and VREFN, respectively.

6. The SAR ADC architecture of claim 5, wherein the input voltages of the first input VXP and the second input VXN of the comparator are respectively:

VXP = VREF_CM – (Vi_SE – VFS/4)

VXN = VREF_CM – (VFS/4 - 0)

wherein VREF _ CM represents a differential common mode voltage of the reference voltage VREF, i.e., VREF _ CM = (VREFP + VREFN)/2;

obtaining the differential input voltage of the comparator by the input voltages of the first input end VXP and the second input end VXN as follows: VX _ diff = Vi _ SE-VFS/2.

7. The SAR ADC architecture of claim 6, wherein during a conversion phase, after the comparator activates a first comparison period based on VX diff, the comparator determines the MSB weight according to the obtained comparison result; and the controller controls the first capacitor array and the second capacitor array to carry out MSB-1 weight conversion according to the MSB weight result; and if MSB =1, the controller switches the capacitance of the MSB weight of the first capacitive array connected to VREFP to connection VREFN and the capacitance of the MSB weight of the second capacitive array connected to VREFN to connection VREFP such that the differential input voltage of the comparator is updated to: VX _ diff = Vi _ SE-VFS/4 and VFS/4= (VREFP-VREFN)/2, and the conversion of MSB-1 weight is completed until the conversion of the subsequent remaining weight bits is completed up to the LSB weight.

8. The SAR ADC architecture of any of claims 1 to 3, wherein the first input signal and the fourth input signal are VFS/4; the second input signal is ground, and the third input signal is a single-ended input signal Vi _ SE; the switching of the state switch SAMP corresponds to the sampling phase and the switching phase, respectively.

9. A single-ended successive approximation register analog-to-digital converter, SAR, ADC, circuit, comprising: an input multiplexer, the SAR ADC architecture of any of claims 1 to 8; wherein the input multiplexer is configured to receive a single-ended input signal Vi _ SE and input a single-ended signal VI _ ADC to the SAR ADC architecture.