CN109379082B - Successive approximation analog-to-digital converter - Google Patents
Successive approximation analog-to-digital converter Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
Abstract
The invention discloses a successive approximation analog-to-digital converter, comprising: the digital control circuit comprises a DAC, a comparator, an output register and digital control logic, wherein the input end of the DAC is connected with an input signal Vin and a reference voltage Vref, and the input ends of the comparator are respectively the output voltage V of the DAC DAC And an internal common mode level V generated by the voltage division of the VDD resistor CM The input end of the digital control logic is connected to the output end of the comparator, the analog-to-digital conversion result is output by acquiring sampling time and selecting the number of bits of the ADC, the input end of the output register is connected to the output end of the digital control logic, the first output end of the output register is connected to the DAC, and the second output end outputs the conversion signal. The invention skillfully takes all capacitors of the MSB bit as sampling capacitors to sample and stores the input voltage in the DAC, thereby needing no additional sampling hold circuit, greatly reducing layout area, adjusting resolution and optimizing the speed and precision of the ADC.
Description
Technical Field
The invention relates to the field of analog-to-digital converters, in particular to a successive approximation analog-to-digital converter.
Background
The successive approximation analog-to-digital converter SAR (Successive Approximation Register), in each conversion process, compares the input analog signal with each other by traversing all the quantized values and converting them to analog values, and finally obtains the digital signal to be output. The basic structure of a conventional SAR analog-to-digital converter is shown in fig. 1, and mainly comprises a DAC, a comparator, an output register, and digital control logic, and the core of the conventional SAR analog-to-digital converter is the DAC and the comparator. A combined schematic diagram of an r+c scaling type DAC is shown in fig. 2. The MSB bits employ charge scaling sub-DACs and the LSB bits employ voltage scaling sub-DACs, which have the advantage that the accuracy of the MSB is higher and the LSB is monotonic, since less tolerance is required for the LSB, so the overall performance of the structure is better. The output voltage of the DAC can be expressed as:
however, the conventional SAR ADC requires an additional sample-and-hold circuit, resulting in a large circuit layout area; meanwhile, the resolution cannot be adjusted, namely the number of bits of the ADC is not selectable, so that the ADC cannot be suitable for different application occasions, and the conversion speed and the conversion precision of the ADC are optimized.
Disclosure of Invention
The invention aims to overcome the defects and shortcomings of the prior art and provides a novel successive approximation analog-to-digital converter. The invention discloses a successive approximation analog-to-digital converter, which mainly comprises a DAC, a comparator, an output register and digital control logic, wherein an input signal Vin is input to the DAC instead of being used as the input of the comparator, and the input of two ends of the comparator are respectively the output voltage V of the DAC DAC And an internal common mode level V generated by the voltage division of the VDD resistor CM The digital control logic outputs the analog-to-digital conversion result by acquiring the sampling time and selecting the number of bits of the ADC. During sampling, all capacitors of the MSB bit are smartly used as sampling capacitors to sample and store the input voltage in the DAC, so that an additional sampling and holding circuit is not needed, the layout area is greatly reduced, the resolution can be adjusted, for example, a 10-bit or 12-bit ADC is selected, and the speed and the precision of the ADC are optimized.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a successive approximation analog-to-digital converter comprising: the digital control circuit comprises a DAC, a comparator, an output register and digital control logic, wherein the input end of the DAC is connected with an input signal Vin and a reference voltage Vref, and the input ends of the comparator are respectively the output voltage V of the DAC DAC And an internal common mode level V generated by the voltage division of the VDD resistor CM The input end of the digital control logic is connected to the output end of the comparator, the analog-to-digital conversion result is output by acquiring sampling time and selecting the number of bits of the ADC, the input end of the output register is connected to the output end of the digital control logic, the first output end of the output register is connected to the DAC, and the second output end outputs the conversion signal.
Further, the digital control logic may acquire the sample at a time that is, by SAMP<3:0>Selecting the number of sampling time periods, the sampling time being (SAMP<3:0>+1)*T CLK Wherein T is CLK Is the clock period of the ADC;
the digital control logic selects whether the ADC is 10 BITs or 12 BITs according to the BIT_OPT, when the BIT_OPT is high, the ADC is 10 BITs, and when the BIT_OPT is low, the ADC is 12 BITs.
Further, a switch S is provided between the positive and negative inputs of the comparator E For switching to cause the comparator to enter different phases.
Further, during the calibration phase, switch S E Closing, the input signal Vin is connected with the lower polar plate of all the capacitors, and the upper polar plate of all the capacitors is connected with the common mode level V CM The two input ends of the comparator are connected with a common mode level V CM The comparator enters a calibration phase.
Further, during the comparison phase, switch S E Disconnection, the positive input end of the comparator is connected with the common mode level V CM The negative input end is connected with the output voltage V of the DAC DAC The method comprises the steps of carrying out a first treatment on the surface of the During the highest bit comparison, one half of the lower capacitor plates are grounded, the other half of the lower capacitor plates are connected with the reference voltage Vref, if the output is low, the highest bit is high, then 3/4 of the lower capacitor plates are grounded, and 1/4 of the lower capacitor plates are connected with the reference voltage Vref, if the output is high, the next highest bit is low.
Further, during the sampling phase, the capacitors C0-C2M+K-1 are switched to the input voltage of the comparator, the input signal Vin is stored in the capacitors, and the voltages at the two ends of the capacitors C0-C2M+K-1 are as follows: vin-V CM 。
Further, during the conversion phase, the output voltage V of the comparator is obtained according to the equivalent circuit and the charge conservation of the comparison phase and the conversion phase out ＝A.(V cm '-V cm )＝A[V DAC -V in ]Where A is the comparator gain and Vcm' is the equivalent voltage at the comparator input.
Compared with the prior art, the invention has the following advantages and effects:
the successive approximation analog-to-digital converter provided by the invention does not need an additional sampling hold circuit, utilizes a high-order conversion capacitor as a sampling capacitor, saves input voltage, and greatly reduces layout area.
The sampling time of the successive approximation analog-to-digital converter provided by the invention can be independently configured, when the input signal is weak, the input signal is required to be completely sampled, and then the sampling time is required to be increased.
The successive approximation analog-to-digital converter provided by the invention can select 10-bit ADC or 12-bit ADC by configuration, and the 10-bit ADC has two clock cycles less than 12-bit ADC, which means that the 10-bit ADC can have higher speed and the 12-bit ADC has higher precision. The method is suitable for different application occasions, and optimizes the speed and the precision of the ADC. Assuming that the sampling period of the ADC is two clock periods, the 10-bit ADC is 12.5% faster than the 12-bit ADC, that is, by configuring 10 bits or 12 bits, the conversion speed of the ADC can be increased by 12.5% when the 10-bit ADC is used.
Drawings
The invention will be further understood from the following description taken in conjunction with the accompanying drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the embodiments. In the figures, like reference numerals designate corresponding parts throughout the different views.
Fig. 1 is a basic structural diagram of a conventional SAR analog-to-digital converter;
FIG. 2 is a combined schematic diagram of an R+C scaling type DAC;
FIG. 3 is a block diagram of a successive approximation analog-to-digital converter of the present invention;
FIG. 4 is a schematic diagram of the core circuit DAC and comparator of the successive approximation analog to digital converter of the present invention;
FIG. 5 is an equivalent circuit diagram of the successive approximation analog-to-digital converter of the present invention during a sampling phase;
fig. 6 is an equivalent circuit diagram of the successive approximation analog-to-digital converter of the present invention at the conversion stage.
Detailed Description
Examples
As shown in fig. 3, the successive approximation analog-to-digital converter provided in this embodiment includes: the digital control circuit comprises a DAC, a comparator, an output register and digital control logic, wherein the input end of the DAC is connected with an input signal Vin and a reference voltage Vref, and the input ends of the comparator are respectively the output voltage V of the DAC DAC And an internal common mode level V generated by the voltage division of the VDD resistor CM The input end of the digital control logic is connected to the output end of the comparator, the analog-to-digital conversion result is output by acquiring sampling time and selecting the number of bits of the ADC, the input end of the output register is connected to the output end of the digital control logic, the first output end of the output register is connected to the DAC, and the second output end outputs the conversion signal.
Preferably, the digital control logic obtains the time of sampling specifically by SAMP<3:0>Selecting the number of sampling time periods, the sampling time being (SAMP<3:0>+1)*T CLK Wherein T is CLK Is the clock period of the ADC; the digital control logic selects whether the ADC is 10 BITs or 12 BITs according to the BIT_OPT, when the BIT_OPT is high, the ADC is 10 BITs, and when the BIT_OPT is low, the ADC is 12 BITs. In this way, when sampling, all capacitors of MSB bit are smartly used as sampling capacitors to sample, and the input voltage is sampled and stored in DAC, thus saving the sampling and holding module.
Preferably, a switch S is provided between the positive and negative inputs of the comparator E For switching to cause the comparator to enter different phases.
The schematic diagram of the core circuit DAC and the comparator of the successive approximation analog-to-digital converter is shown in FIG. 4, and the switch S is switched during sampling E Closing, the input signal Vin is connected with the lower polar plate of all the capacitors, and the upper polar plate of all the capacitors is connected with the common mode level V CM The two input ends of the comparator are connected with a common mode level V CM The comparisonThe device enters the calibration phase.
Further, during the comparison phase, switch S E Disconnection, the positive input end of the comparator is connected with the common mode level V CM The negative input end is connected with the output voltage V of the DAC DAC The method comprises the steps of carrying out a first treatment on the surface of the During the highest bit comparison, half of the lower capacitance plates are grounded, the other half of the lower capacitance plates are connected with the reference voltage Vref, if the output is low, the highest bit is high, then 3/4 of the lower capacitance plates are grounded, 1/4 of the lower capacitance plates are connected with the reference voltage Vref, if the output is high, the next highest bit is low, and so on.
In the sampling stage of the successive approximation analog-to-digital converter, as shown in fig. 5, capacitors C0 to c2m+k-1 are switched to the input voltage of the comparator, the input signal Vin is stored in the capacitors, and voltages at two ends of the capacitors C0 to c2m+k-1 are as follows: vin-V CM 。
The equivalent circuit diagram of the successive approximation analog-to-digital converter in the conversion stage is shown in fig. 6, and the output voltage V of the comparator is obtained according to the equivalent circuit and the charge conservation of the comparison stage and the conversion stage in the conversion stage out ＝A.(V cm '-V cm )＝A[V DAC -V in ]Where A is the comparator gain and Vcm' is the equivalent voltage at the comparator input.
Specifically, C eq Is equivalent capacitance, the size of the equivalent capacitance is
C eq ＝(2 m-1 b 0 +2 m-2 b 1 +...+b m-1 ) And C, performing the operation of the device. The conservation of charge according to the comparison phase and the conversion phase is:
(V in -V cm )2 M C＝(V ref -V cm ').C eq +(V k -V cm ')C-V cm '(2 M -C eq /C-1)C，
wherein,
the method can obtain: v (V) out ＝A.(V cm '-V cm )＝A[V DAC -V in ]Where a is the comparator gain. From the formula, by comparing V cm '-V cm To replace V DAC -V in Thus not requiring direct comparison of V DAC And V IN Is of a size of (a) and (b).
An example specific calculation is next performed on the samples and comparisons. Assuming that the ADC is a 12-bit ADC, vdd=v REF ＝5V，V IN =3.5v. When the sampling phase is completed, the voltage at two ends of the DAC capacitor is-V IN +V CM At this time, the total charge of the upper plate of the capacitor is q= -64c× (V IN -V CM )。
Firstly, the highest position of the initial state is high, at this time, half of the capacitance lower polar plate is connected with V REF The rest is unchanged, and is still grounded, and the total charge amount on the capacitor is as follows: q=32c× (V DAC_1 -V REF )+32C×V DAC_1 From conservation of charge, V can be obtained DAC_1 -V CM ＝1/2V REF -V IN ＝2.5-3.5＝-1.0V<0, so the comparator output is 0, so the most significant bit is high, which is done within the first clock cycle of the comparison phase.
Secondly, the next highest position and the highest position are assumed to be the same high, and at the moment, the lower polar plate of the 3/4 capacitor is connected with V REF The rest is unchanged, and is still grounded, and the total charge amount on the capacitor is as follows: q=48c× (V CDAC_2 -V REF )+16C× DAC _ 2 The conservation of charge can be achieved by: v (V) DAC _ 2 -Vd＝3/4V REF -V IN ＝3/4×5-3.5＝0.25V>0, so the comparator output is 1, so the next highest bit is low, and this is done within the second clock cycle of the comparison stage.
And so on, obtaining a 12-bit ADC conversion result.
The timing sequence of the ADC adopts 5-bit Gray code count, taking 12-bit ADC as an example, and taking 14 cycles from 00000 to 01011 as comparison phases, SAMP<3:0>The number of counts of the control 01001 to 00000 is SAMP<3:0>+1, thereby realizing a sampling time of%SAMP<3:0>+1)*T CLK 。
When bit_opt is high, the ADC is a 10-BIT ADC, i.e. the 5-BIT gray code count is 12 cycles total from 00000 to 01110 in the comparison phase; when bit_opt is low, the ADC is a 12-BIT ADC, i.e., the 5-BIT gray code count is 14 cycles total from 00000 to 01011 in the comparison phase, thereby realizing the BIT number switching of the ADC.
In the embodiment, the successive approximation analog-to-digital converter provided uses the high-order DAC capacitor as the sampling capacitor, so that a sampling hold circuit is saved, and the layout area is greatly reduced; and the number of bits of the ADC is selectable, for example 10 bits or 12 bits; the sampling time is selectable, for example, 1-16 ADC clock cycles can be selected, and the sampling time is suitable for different application occasions, so that the speed and the precision of the ADC are optimized.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
While the invention has been described above with reference to various embodiments, it should be understood that many changes and modifications can be made without departing from the scope of the invention. It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention. The above examples should be understood as illustrative only and not limiting the scope of the invention. Various changes and modifications to the present invention may be made by one skilled in the art after reading the teachings herein, and such equivalent changes and modifications are intended to fall within the scope of the invention as defined in the appended claims.
Claims (6)
1. A successive approximation analog-to-digital converter comprising: DAC, comparator, output register and digital control logic,
wherein, the input end of the DAC is connected with an input signal Vin and a reference voltage Vref,
the two ends of the comparator are respectively input with the output voltage V of the DAC DAC And an internal common mode level V generated by the voltage division of the VDD resistor CM ，
The input end of the digital control logic is connected to the output end of the comparator, and the analog-digital conversion result is output by acquiring the sampling time and selecting the digits of the ADC,
the input end of the output register is connected to the output end of the digital control logic, the first output end of the output register is connected to the DAC, and the second output end outputs the conversion signal;
the time for the digital control logic to acquire the samples is specifically SAMP<3:0>Selecting the number of sampling time periods, wherein the sampling time isWherein T is CLK Is the clock period of the ADC;
the digital control logic selects whether the ADC is 10 BITs or 12 BITs according to the BIT_OPT, when the BIT_OPT is high, the ADC is 10 BITs, and when the BIT_OPT is low, the ADC is 12 BITs.
2. The successive approximation analog-to-digital converter of claim 1, being characterized byThe method is characterized in that: having a switch S between the positive and negative inputs of the comparator E For switching to cause the comparator to enter different phases.
3. The successive approximation analog-to-digital converter according to claim 2, wherein: during the calibration phase, switch S E Closing, the input signal Vin is connected with the lower polar plate of all the capacitors, and the upper polar plate of all the capacitors is connected with the common mode level V CM The two input ends of the comparator are connected with a common mode level V CM The comparator enters a calibration phase.
4. The successive approximation analog-to-digital converter according to claim 2, wherein: during the comparison phase, switch S E Disconnection, the positive input end of the comparator is connected with the common mode level V CM The negative input end is connected with the output voltage V of the DAC DAC The method comprises the steps of carrying out a first treatment on the surface of the During the highest bit comparison, one half of the lower capacitor plates are grounded, the other half of the lower capacitor plates are connected with the reference voltage Vref, if the output is low, the highest bit is high, then 3/4 of the lower capacitor plates are grounded, and 1/4 of the lower capacitor plates are connected with the reference voltage Vref, if the output is high, the next highest bit is low.
5. The successive approximation analog-to-digital converter according to claim 2, wherein: during the sampling phase, capacitor C 0 ~C 2M+K-1 Is switched to the input voltage of the comparator, the input signal Vin is stored in a capacitor, capacitor C 0 ~C 2M+K-1 The voltage at two ends is: vin-V CM 。
6. The successive approximation analog-to-digital converter according to claim 2, wherein: during the conversion stage, the output voltage of the comparator is obtained according to the equivalent circuit and the charge conservation of the comparison stage and the conversion stageWherein A is the comparator gain, V cm ' equivalent power for comparator input terminalPressing.
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| CN110022155B (en) * | 2019-03-06 | 2021-05-25 | 东北大学 | Asynchronous over-level sampling analog-to-digital converter with sampling threshold changing along with input signal |
| CN110071720B (en) * | 2019-04-25 | 2023-05-26 | 湖南品腾电子科技有限公司 | Self-calibrating full-capacitance successive approximation digital-to-analog conversion circuit |
| CN110071722B (en) * | 2019-04-25 | 2022-12-27 | 湖南品腾电子科技有限公司 | Voltage scaling type successive approximation digital-to-analog conversion circuit |
| CN110880937B (en) * | 2019-12-24 | 2024-04-12 | 中山大学 | N bit analog-to-digital converter based on progressive approximation architecture |
| US10903843B1 (en) * | 2020-02-14 | 2021-01-26 | Analog Devices International Unlimited Company | SAR ADC with variable sampling capacitor |
| CN112564710B (en) * | 2020-12-14 | 2023-04-18 | 峰岧科技(上海)有限公司 | Analog-to-digital conversion method, device, circuit and computer readable storage medium |
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