CN107968656A - A kind of successive approximation simulates digital quantizer and its using switching method - Google Patents
A kind of successive approximation simulates digital quantizer and its using switching method Download PDFInfo
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- CN107968656A CN107968656A CN201610919701.4A CN201610919701A CN107968656A CN 107968656 A CN107968656 A CN 107968656A CN 201610919701 A CN201610919701 A CN 201610919701A CN 107968656 A CN107968656 A CN 107968656A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The present invention relates to a kind of successive approximation simulation digital quantizer and its using switching method, including：Sampling switch circuit, Charge scaling type digital analog converter, dynamic comparer and SAR logic circuits are sequentially connected in series；Single-ended applications driving source is connected with sampling switch circuit；Charge scaling type digital analog converter is made of P ends capacitor array, N-terminal capacitor array and benchmark driving reverser；P ends capacitor array and benchmark driving reverser series connection, the output terminal after series connection are connected with SAR logic circuits；N-terminal capacitor array and benchmark driving reverser series connection, the output terminal after series connection are connected with SAR logic circuits.The present invention can improve the linearity of sampled signal, and then the raising achievable precision of ADC, reduce power consumption to ensure the symmetry of sampling network when single-ended applications and differential applications.
Description
Technical field
The present invention relates to analog-digital converter field, more particularly to a kind of successive approximation simulation digital quantizer and its
Using switching method.
Background technology
In recent years, for SOC systems in order to expand the more and more interface systems of various application integration, general ADC is therein
One kind, requirement of the SOC systems to general ADC is low in energy consumption, area is small and supports single-ended differential applications at the same time, to speed and precision
Requirement it is relatively low, with the development of CMOS technology, achievable capacitance is less and less in advanced technologies, and matching precision is got over
Come it is higher, charge type SAR ADC become SOC systems in general ADC first choice.
In order to meet that general ADC is single-ended and the application demand of difference, common processing method, difference sampling is made by ADC,
The output of the Differential Input connection fully differential VGA (variable gain amplifier) of ADC, by the way that VGA is configured to single ended input application
Or Differential Input application, switch so as to fulfill the single-ended differential applications of ADC.This processing method is to the VGA before ADC input terminals
More demanding, VGA can consume relatively large power consumption, and take larger area, can be right in order to save the VGA of ADC front ends
Sampling switch and capacitor array carry out a series of processing, equally meet the needs of general ADC single-ended applications and differential applications.
The content of the invention
The technical problems to be solved by the invention are：In the prior art, VGA is configured to single ended input application or difference is defeated
Enter application, so as to fulfill ADC single-ended differential applications switch, this processing method to before ADC input terminals VGA requirement compared with
Height, VGA can consume relatively large power consumption, and take larger area.
The technical solution that the present invention solves above-mentioned technical problem is as follows：A kind of successive approximation simulates digital quantizer, bag
Include：Sampling switch circuit, Charge scaling type digital analog converter, dynamic comparer and SAR logic circuits are sequentially connected in series；It is single
End application drive source is connected with sampling switch circuit；Charge scaling type digital analog converter is by P ends capacitor array, N-terminal electricity
Hold array and benchmark driving reverser composition；P ends capacitor array and benchmark driving reverser series connection, output terminal after series connection with
SAR logic circuits connect；N-terminal capacitor array and benchmark driving reverser series connection, the output terminal after series connection connect with SAR logic circuits
Connect.
Beneficial effects of the present invention：Sampling switch and capacitor array are handled through the above way, reduce the area of occupancy,
The present invention with the symmetry of guarantee sampling network when single-ended applications and differential applications, can improve the linearity of sampled signal, and then
The achievable precision of ADC is improved, reduces power consumption.
Based on the above technical solutions, the present invention can also be improved as follows.
Further, the N-terminal capacitor array and benchmark driving reverser series connection, the output terminal after series connection are also opened with sampling
Powered-down road connection.
Further, the sampling switch circuit includes first switch, second switch, third switch and the 4th switch, its
Middle first switch one end connects the vp input terminals of dynamic comparer, the conduct of second switch one end as vip input terminals, the other end
Vin input terminals, the other end connect the vn input terminals of dynamic comparer, the output of the 3rd switch one end connection single-ended applications driving source
End, the other end connect the vn input terminals of dynamic comparer, and the 4th switch one end is as vip input terminals, other end connection N-terminal capacitance
The switch arrays of array bottom crown.
Further, the vp input terminals of the switch arrays of P ends capacitor array top crown and dynamic comparer connect, P ends capacitance
The switch arrays of array bottom crown are connected with benchmark driving reverser, the output terminal and SAR logic circuits of benchmark driving reverser
Connection.
Further, the switch arrays of N-terminal capacitor array top crown are connected with the vn input terminals of dynamic comparer, N-terminal capacitance
The switch arrays of array bottom crown are connected with benchmark driving reverser.
Further, the P, N-terminal capacitor array include：Switch arrays, capacitor array, the switch of bottom crown of top crown
Array, three are sequentially connected in series.
Using above-mentioned further beneficial effect：Ensure the differential symmetry of sampling network when difference and single-ended applications at the same time
Property, improves the linearity of sampled signal.
Further, the switch arrays are at least by two switch in parallel, and capacitor array is at least by two capacitance parallel connections.
Further, the switch arrays of the bottom crown in N-terminal capacitor array are to include at least two either-or switch, each
The switch of alternative includes A switches and B switches, and A switches are connected with the 4th switch, the input of B switches and benchmark driving reverser
End is connected.
Above-mentioned further beneficial effect：Single-ended and difference application switching can be effectively realized.
Based on the above technical solutions, the present invention further comprises a kind of answering for successive approximation simulation digital quantizer
With switching method, this includes the following steps using switching method：
S1, the partial switch closure in sample phase, sampling switch circuit, part disconnect, and pass through Charge scaling type
The switch closure of switch arrays in digital analog converter is opened, and capacitor array is sampled；
S2, after sample phase, sampling switch circuit switches off, and is turned by Charge scaling type digital simulation
Switch closure or opening in parallel operation, the output of SAR logic circuits control benchmark driving reverser, carry out Analog-digital Converter
The codeword decision of device.
Beneficial effect：Reduce power consumption, reduce the area of application, while improve the linearity of sampled signal, ensure
Single-ended and differential applications can jointly with same SAR logics.
Further, in step S1, the switching method of differential applications is specially：
First switch and second switch closure in sample phase, sampling switch circuit, the 3rd switch and the 4th switch
Disconnect, the switch arrays in the capacitor array of P ends close, the switch arrays closure and bottom crown of top crown in N-terminal capacitor array
Switch arrays B switch closures, A switches off, and P, the capacitor array of N-terminal are top crown sampling at this time.
Further, in step S1, the switching method of single-ended applications is specially：
In sample phase, input signal is inputted from vip ends, and first switch, the 3rd switch and the 4th switch closure, second opens
Shut-off is opened, and the switch arrays in the capacitor array of P ends close, top crown switch arrays closure and bottom crown in N-terminal capacitor array
Switch arrays A switch closures, B are switched off, and P ends capacitor array samples for top crown, and N-terminal capacitor array samples for bottom crown.
Brief description of the drawings
Fig. 1 simulates digital quantizer schematic diagram for a kind of successive approximation of the present invention；
Fig. 2 is that a kind of successive approximation of the present invention simulates the schematic diagram of digital quantizer；
A kind of successive approximation that Fig. 3 is the present invention simulates digital quantizer application switching method flow chart；
Equivalent sampling network portion structure diagram when Fig. 4 is the single-ended applications switching of the present invention；
Equivalent sampling network portion structure diagram when Fig. 5 is the differential applications switching of invention；
When Fig. 6 is that the successive approximation of the single-ended and differential applications switching of the present invention simulates the conversion logic of digital quantizer
Sequence schematic diagram.
Embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
As depicted in figs. 1 and 2, a kind of successive approximation simulation digital quantizer, including：Sampling switch circuit, electric charge are again
Distribution type digital analog converter, dynamic comparer and SAR logic circuits are sequentially connected in series；Single-ended applications driving source and sampling switch
Circuit connects；Charge scaling type digital analog converter drives reverser by P ends capacitor array, N-terminal capacitor array and benchmark
Composition；P ends capacitor array and benchmark driving reverser series connection, the output terminal after series connection are connected with SAR logic circuits；N-terminal capacitance
Array and benchmark driving reverser series connection, the output terminal after series connection are connected with SAR logic circuits.
Sampling switch circuit includes first switch, second switch, third switch and the 4th switch SSWP2, wherein, first opens
Close one end and be used as vip input terminals, the vp input terminals of other end connection dynamic comparer, second switch one end as vin input terminals,
The other end connects the vn input terminals of dynamic comparer, output terminal of the 3rd switch one end as single-ended applications driving source, the other end
The vn input terminals of dynamic comparer are connected, the 4th switch one end connects pole under N-terminal capacitor array as vip input terminals, the other end
The switch arrays of plate.
The switch arrays of P ends capacitor array top crown and the vp input terminals of dynamic comparer connect, pole under the capacitor array of P ends
The switch arrays of plate are connected with benchmark driving reverser, and the output terminal of benchmark driving reverser is connected with SAR logic circuits.
The switch arrays of N-terminal capacitor array top crown are connected with the vn input terminals of dynamic comparer, pole under N-terminal capacitor array
Switch arrays and benchmark the driving reverser of plate or the 4th switch connection.The input of the switch arrays of P ends capacitor array top crown
End is in parallel with second switch, reconnects the vp input terminals of dynamic comparer；The input of the switch arrays of N-terminal capacitor array top crown
End is in parallel with first switch, reconnects the vn input terminals of dynamic comparer.
P, N-terminal capacitor array includes：Switch arrays, capacitor array, the switch arrays of bottom crown of top crown, three is successively
Series connection.Switch arrays are at least by two switch in parallel, and capacitor array is at least by two capacitance parallel connections.Under in N-terminal capacitor array
The switch arrays of pole plate are to include at least two either-or switch, and the switch of each alternative includes A switches and B switches, and A is opened
Close and be connected with the 4th switch, B switches are connected with the input terminal of benchmark driving reverser.
As shown in figure 3, a kind of successive approximation simulation digital quantizer applies switching method, the step of method, is：
S1, the partial switch closure in sample phase, sampling switch circuit, part disconnect, and pass through Charge scaling type
The switch closure of switch arrays in digital analog converter is opened, and capacitor array is sampled；
S2, after sample phase, sampling switch circuit switches off, and is turned by Charge scaling type digital simulation
Switch closure or opening in parallel operation, the output of SAR logic circuits control benchmark driving reverser, carry out Analog-digital Converter
The codeword decision of device.
In step S1, the switching method of differential applications is specially：First switch in sample phase, sampling switch circuit
Close, the 3rd switch and the 4th switch off with second switch, switch arrays in the capacitor array of P ends and close, N-terminal capacitance
The B switch closures of the switch arrays of the switch arrays closure of top crown and bottom crown in array, A switches off, at this time P, N-terminal
Capacitor array is top crown sampling.
In step S1, the switching method of single-ended applications is specially：In sample phase, input signal is inputted from vip ends, and first
Switch, the 3rd switch and the 4th switch closure, second switch disconnect, and switch arrays in the capacitor array of P ends and close, N-terminal
Top crown switch arrays closure and the A switch closures of bottom crown switch arrays, B are switched off in capacitor array, P ends capacitor array
Sampled for top crown, N-terminal capacitor array samples for bottom crown.
For SAR logic circuits in the starting stage of codeword decision, control is connected to the benchmark driving of P ends capacitor array bottom crown
Reverser output is supply voltage, controls the benchmark driving reverser output for being connected to N-terminal capacitor array bottom crown electric for power supply
Pressure；Codeword decision stage after sample phase, first clock cycle do not do any operation, and second clock cycle is
Start the judgement of MSB.
In ADC single-ended applications, first clock cycle in ADC codeword decision stages is used for dynamic comparer vn input terminals
The foundation of voltage.
Technical principle explaination is as follows：If the input signal of ADC is a pair of of differential signal, corresponding v i p and v i n can
To be expressed as
Vip=VCM+VDM
Vin=VCM-VDM
Wherein, VCM is the common-mode signal of Differential Input, and VDM is the difference mode signal of Differential Input, by differential input signal phase
Add, can obtain
Vip+vin=2VCM
Then, another letter in differential signal can be obtained by a signal in common-mode signal and differential signal
Number, it is represented by
Vin=2VCM-vip
If common-mode signal is chosen for the half of supply voltage, i.e.,
VCM=VDD/2
Then have
Vin=2VCM-vip=VDD-vip
For the differential applications of ADC, corresponding equivalent sampling network is as shown in figure 4, in sample phase, comparator input terminal
Signal be respectively
Vp=vip
Vn=vin
In the starting stage of codeword decision, since the bottom crown voltage of capacitance in capacitor array remains unchanged, i.e. capacitance battle array
Capacitance does not have any upset in row, can be obtained by principle of charge conservation,
Vp=vip
Vn=vin
For the single-ended applications of ADC, corresponding equivalent sampling network is as shown in fig. 5, it is assumed that N under SAR logic default conditions
The bottom crown connection GND of capacitor array is held, in sample phase, the signal of comparator input terminal is respectively
Vp=vip
Vn=VDD
The bottom crown voltage of capacitance remains unchanged in the starting stage of codeword decision, P ends capacitor array, N-terminal capacitance battle array
Capacitance bottom crown voltage switching can be obtained to GND by principle of charge conservation in row
(VDD-vip)×2N-1× C=(vn-0) × 2N-1×C
I.e.
Vp=vip
Vn=VDD-vip=2VCM-vip=vin
That is, by switching, during ADC single-ended applications, in the starting stage of code word conversion, the input of comparator
It is equivalent when voltage and differential applications, identical SAR logics can be shared.
For the single-ended applications of ADC, if the bottom crown of N-terminal capacitor array connects VDD under SAR logic default conditions, that
In sample phase, the signal of comparator input terminal is respectively
Vp=vip
Vn=GND
The bottom crown voltage of capacitance remains unchanged in the starting stage of codeword decision, P ends capacitor array, N-terminal capacitance battle array
Capacitance bottom crown voltage switching can be obtained to GND by principle of charge conservation in row
(0-vip)×2N-1× C=(vn-VDD) × 2N-1×C
I.e.
Vp=vip
Vn=VDD-vip=2VCM-vip=vin
During ADC single-ended applications, since N-terminal capacitor array is bottom crown sampling, in the starting stage of codeword decision, comparator
Vn input terminal voltages cannot establish desired value vi n immediately, so corresponding SAR logics need to be modified slightly.
Fig. 6 show proposed by the present invention suitable for the single-ended SAR logical sequences with differential applications switching of ADC, and routine
SAR logics compare, the codeword decision stage after sample phase, first clock cycle does not do any operation, second
A clock cycle just starts the judgement of MSB (highest order).For ADC single-ended applications, first clock week in codeword decision stage
Phase is used for the foundation of comparator vn input terminal voltages.For ADC differential applications, first clock cycle in codeword decision stage is
Latent period, no essential meaning, purpose, which is intended merely to ADC single-ended applications and differential applications, can share same set of SAR logics.
In the present specification, a schematic expression of the above terms does not necessarily refer to the same embodiment or example.
Moreover, particular features, structures, materials, or characteristics described can be in any one or more of the embodiments or examples with suitable
Mode combines.In addition, without conflicting with each other, those skilled in the art can be by the difference described in this specification
Embodiment or example and different embodiments or exemplary feature are combined and combine.
Although the embodiment of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, those of ordinary skill in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, changes, replacing and modification.
Claims (12)
1. a kind of successive approximation simulates digital quantizer, it is characterised in that including：Sampling switch circuit, Charge scaling type
Digital analog converter, dynamic comparer and SAR logic circuits are sequentially connected in series；Single-ended applications driving source connects with sampling switch circuit
Connect；Charge scaling type digital analog converter is made of P ends capacitor array, N-terminal capacitor array and benchmark driving reverser；P
Capacitor array and benchmark driving reverser series connection are held, the output terminal after series connection is connected with SAR logic circuits；N-terminal capacitor array and
Benchmark driving reverser series connection, the output terminal after series connection are connected with SAR logic circuits.
A kind of 2. successive approximation simulation digital quantizer according to claim 1, it is characterised in that the N-terminal electricity
Hold array and benchmark driving reverser series connection, the output terminal after series connection is also connected with sampling switch circuit.
3. a kind of successive approximation simulation digital quantizer according to claim 1, it is characterised in that the sampling is opened
Powered-down road includes first switch, second switch, third switch and the 4th switch, wherein first switch one end as vip input terminals,
The other end connects the vp input terminals of dynamic comparer, and second switch one end is as vin input terminals, other end connection dynamic comparer
Vn input terminals, the 3rd switch one end connection single-ended applications driving source output terminal, the other end connection dynamic comparer vn it is defeated
Enter end, the 4th switch one end connects the switch arrays of N-terminal capacitor array bottom crown as vip input terminals, the other end.
A kind of 4. successive approximation simulation digital quantizer according to claim 1, it is characterised in that P ends capacitor array
The switch arrays of top crown and the vp input terminals of dynamic comparer connect, the switch arrays and benchmark of P ends capacitor array bottom crown
Reverser connection is driven, the output terminal of benchmark driving reverser is connected with SAR logic circuits.
A kind of 5. successive approximation simulation digital quantizer according to Claims 2 or 3, it is characterised in that N-terminal capacitance battle array
The switch arrays of row top crown are connected with the vn input terminals of dynamic comparer, the switch arrays and base of N-terminal capacitor array bottom crown
Quasi- driving reverser connection.
A kind of 6. successive approximation simulation digital quantizer according to claim 3, it is characterised in that the P ends electricity
It is in parallel with first switch to hold the input terminal of the switch arrays of array top crown, reconnects the vp input terminals of dynamic comparer；It is described
N-terminal capacitor array top crown switch arrays input terminal it is in parallel with second switch, reconnect dynamic comparer vn input
End.
A kind of 7. successive approximation simulation digital quantizer according to claim 1-4, it is characterised in that described P, the N
End capacitor array includes：Switch arrays, capacitor array, the switch arrays of bottom crown of top crown, three are sequentially connected in series.
A kind of 8. successive approximation simulation digital quantizer according to claim 7, it is characterised in that the switch arrays
Row are at least by two switch in parallel, and capacitor array is at least by two capacitance parallel connections.
A kind of 9. successive approximation simulation digital quantizer according to claim 8, it is characterised in that N-terminal capacitor array
In the switch arrays of bottom crown be to include at least two either-or switch, the switch of each alternative includes A switches and B is opened
Close, A switches are connected with the 4th switch, and B switches are connected with the input terminal of benchmark driving reverser.
A kind of 10. application of successive approximation simulation digital quantizer using described in any claim in claim 1 to 9
Switching method, it is characterised in that this includes the following steps using switching method：
S1, the partial switch closure in sample phase, sampling switch circuit, part disconnect, and pass through Charge scaling type numeral
The switch closure of switch arrays in analog converter is opened, and capacitor array is sampled；
S2, after sample phase, sampling switch circuit switches off, and passes through Charge scaling type digital analog converter
In switch closure or open, SAR logic circuits control benchmark driving reverser output, carry out analog-digital converter
Codeword decision.
11. a kind of successive approximation simulation digital quantizer according to claim 10 applies switching method, its feature
It is, in step S1, the switching method of differential applications is specially：
First switch and second switch closure in sample phase, sampling switch circuit, the 3rd switch and the 4th switch off,
Switch arrays in the capacitor array of P ends close, the switch arrays closure of top crown and the switch of bottom crown in N-terminal capacitor array
The B switch closures of array, A are switched off, and P, the capacitor array of N-terminal are top crown sampling at this time.
12. a kind of successive approximation simulation digital quantizer according to claim 11 applies switching method, its feature
It is, in step S1, the switching method of single-ended applications is specially：
In sample phase, input signal is inputted from vip ends, and first switch, the 3rd switch and the 4th switch closure, second switch break
Open, the switch arrays in the capacitor array of P ends close, top crown switch arrays closure and bottom crown switch in N-terminal capacitor array
Array A switch closures, B are switched off, and P ends capacitor array samples for top crown, and N-terminal capacitor array samples for bottom crown.
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| CN108880552B (en) * | 2018-07-05 | 2022-04-22 | 河海大学常州校区 | SAR-ADC (synthetic aperture radar-analog converter) resisting single event effect |
| CN109655927A (en) * | 2018-11-20 | 2019-04-19 | 华中科技大学 | A kind of variable-gain equivalent sampling Ground Penetrating Radar control system based on CPLD |
| CN109655927B (en) * | 2018-11-20 | 2020-06-02 | 华中科技大学 | Variable gain equivalent sampling ground penetrating radar control system based on CPLD |
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| WO2023151633A1 (en) * | 2022-02-10 | 2023-08-17 | 芯海科技（深圳）股份有限公司 | Adc circuit and control method therefor |
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