CN103199864A - Successive approximation type analog-digital converter - Google Patents
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- CN103199864A CN103199864A CN201310048708XA CN201310048708A CN103199864A CN 103199864 A CN103199864 A CN 103199864A CN 201310048708X A CN201310048708X A CN 201310048708XA CN 201310048708 A CN201310048708 A CN 201310048708A CN 103199864 A CN103199864 A CN 103199864A
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Abstract
The invention discloses a successive approximation type analog-digital converter. The successive approximation type analog-digital converter comprises a digital-analog converter, a comparator, a successive approximation logical circuit and a clock source, wherein the successive approximation logical circuit comprises a shifting register and a data register, and a unit of the data register comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first electric potential, a second electric potential, a short circuit capacitor, a self-locking switch, a first phase inverter, a second phase inverter and a third phase inverter. The successive approximation type analog-digital converter largely reduces the delay of the motion that a comparative result is output from the comparator to the digital-analog converter, thereby obviously improving the conversion efficiency of the analog-digital converter.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of analog to digital converter, particularly gradual approaching A/D converter.
Background technology
Fig. 1 has shown a traditional gradual approaching A/D converter, and it comprises digital to analog converter 100, comparator 105, and approach logical circuit 110 one by one.Wherein, approaching logical circuit 110 one by one is made up of shift register 120 and data register 115.Shift register 120 is arrays of being made up of some shifting deposit unit 140-1 ~ 140-n, and each shifting deposit unit has a data input D, an output Q, an input end of clock Ck; Wherein, the data input pin of arbitrary shifting deposit unit 140-i all is coupled to the output of upper level 140-(i-1), first data input pin that moves deposit unit is coupled to the input 121 of described shift register, and the input end of clock of each shifting deposit unit is coupled to the input end of clock 136 of described shift register.The output of i shifting deposit unit 140-i is coupled to i output 122-i of shift register 120.Data register 115 comprises an array of being made up of data deposit unit 145-1 ~ 145-n, and data deposit unit 145-i has data input pin D, output Q.The data input pin D of data deposit unit 145-i is coupled to the output 107 of comparator 105, and its output Q is coupled to the i position input 231-i of digital to analog converter 100.Comparator 105 is used for the output 102 of comparator input signal 101 and digital to analog converter.The work clock 131 of comparator 105 is provided by clock source 130, and comparator is worked in the logic level generation saltus step of work clock.Gate 135 is used for more whether finishing of detection comparator, and in this realization circuit of Fig. 1, gate 135 is actually or door.When comparator resets, two output 106,107 is logical zero, 135 output 136 is logical zero, comparator 105 is worked when the logic level generation saltus step of clock source output 131,106, in 107 is 1 by the logical zero saltus step, make the output 136 of gate 135 jump to logical one, flip-flop shift 120 by logical zero.If before 136 saltus steps, the i-1 position of shift register output 122-(i-1) be high, i position output 122-i is low, after 136 saltus steps, output 122-i in the i position of shift register is also by the low height that becomes so.Then, i data deposit unit 145-i is triggered, and makes its output 231-i catch the value of the output 107 of comparator.Because 231 also is the input of digital to analog converter 100 simultaneously, when signal 231-i changed, the output 102 of digital to analog converter 100 changed accordingly, is input to comparator 105, waited for the saltus step next time of clock 131.This process goes on always, and saltus step is successively exported for high in the n position of shift register 120, and the data deposit unit 145 of data register 115 the insides is triggered successively, and the comparative result of storage comparator uses up up to all data deposit units.This moment, the n position output 231-1 ~ 231-n of data register 115 was exactly the output of this gradual approaching A/D converter.
In a kind of implementation shown in Figure 1, shifting deposit unit 140 and data deposit unit 145 are common d type flip flop.It has multiple way of realization, such as static d type flip flop or dynamic d type flip flop, and other way of realization can also be arranged.
The conversion speed of this gradual approaching A/D converter is subject to several factors, and the logical time delay that outputs to from comparator between the input of digital to analog converter is exactly one of them.As shown in Figure 2, this logical time delay is through gate 135, shifting deposit unit 140-i, data deposit unit 145-I.Wherein, between 3 ~ 4 inverter time-delays, the time-delay of shifting deposit unit and data deposit unit is also greatly between 2 ~ 4 inverter time-delays greatly in the time-delay of gate 135 (or door).Total logical time delay is greatly between the time-delay of 7 ~ 12 inverters, so conventional successive approach type analog to digital converter conversion speed is slow.
Summary of the invention
Technical problem to be solved by this invention is: overcome the slow problem of conventional successive approach type analog to digital converter conversion speed, a kind of high speed self-locking register for analog to digital converter is provided, can significantly cut down the time-delay from comparator output comparative result to the digital to analog converter action, significantly the switching rate of Lifting Modules number converter.
The technology of the present invention solution: a kind of high speed self-locking register for analog to digital converter, a kind of gradual approaching A/D converter comprises a digital to analog converter, a comparator, one is approached logical circuit one by one, a clock source;
The described control logic circuit that approaches one by one comprises a shift register, a data register;
Described shift register has an input, an input end of clock, some outputs;
Described shift register is an array of being made up of some shifting deposit units, and each described shifting deposit unit all has a data input, an output, an input end of clock;
The data input pin of each described shifting deposit unit is coupled to the output of upper level, the data input pin of first described shifting deposit unit is coupled to the input of described shift register, the input end of clock of each described shifting deposit unit is coupled to the input end of clock of described shift register, and the output of each described shifting deposit unit is coupled to one of some outputs of described shift register;
Described data register comprises an array of being made up of some data deposit units, and each described data deposit unit all has a data input, an output;
The data input pin of each described data deposit unit is coupled to the output of described comparator, and the output of each described data deposit unit is coupled to one of some inputs of described digital to analog converter;
The output of described comparator comparator input signal and digital to analog converter;
Described comparator is controlled in described clock source;
Its characteristics are:
Each described data deposit unit also has first and second input end of clock;
Each described data deposit unit all comprises first, second, third, fourth transistor, first and second current potential, a short circuit capacitance, a self-lock switch, first, second, third inverter;
Described first, second, third, fourth transistor has the grid end, source end and drain terminal;
The source end of described the first transistor is coupled to first current potential of described data deposit unit;
Described first and second transistorized drain terminal is coupled to the output of described data deposit unit after through first inverter;
The source end of described transistor seconds and the 3rd transistorized drain terminal are coupled to second current potential of described data deposit unit by described short circuit capacitance;
The described the 3rd transistorized source end is coupled to the described the 4th transistorized drain terminal;
The described the 4th transistorized source end is coupled to second current potential of described data deposit unit;
The grid end of described the first transistor is coupled to first input end of clock of described data deposit unit;
The grid end of described transistor seconds is coupled to the data input pin of described data deposit unit;
The described the 3rd transistorized grid end and the 4th transistorized grid end can exchange, and are coupled to the output of described first input end of clock or the 3rd inverter respectively;
The input of described the 3rd inverter is coupled to described second clock input;
The output of described data deposit unit is coupled to an end of described self-lock switch by described second inverter, and the other end of described self-lock switch is coupled to source end and the 3rd transistorized drain terminal of described transistor seconds;
Described self-lock switch is by the second clock input control of described data deposit unit;
First input end of clock of each described data deposit unit is coupled to the output of one of described shifting deposit unit, and the second clock input of each described data deposit unit is coupled to the output of the next stage of one of described shifting deposit unit.
Described the first transistor is the p-type MOS transistor, second, third, the 4th transistor is n type MOS transistor.
Described the first transistor is n type MOS transistor, second, third, the 4th transistor is the p-type MOS transistor.
Described self-lock switch is cmos transmission gate.
Described short circuit capacitance is realized by mos capacitance.
Described shifting deposit unit is realized by d type flip flop.
The present invention and prior art have following beneficial effect: the present invention is directed to traditional gradually-appoximant analog-digital converter, significantly shortened from the logical time delay between the input that outputs to digital to analog converter of comparator, can significantly improve the conversion speed of gradual approaching A/D converter.
Description of drawings
Fig. 1 is traditional gradual approaching A/D converter;
Fig. 2 is the time-delay path of conventional successive approach type analog to digital converter between from the comparator to DAC;
Fig. 3 gradual approaching A/D converter of the present invention;
Fig. 4 is the input signal rising edge arriving path that sparks constantly of the data input pin of data deposit unit among the present invention;
Fig. 5 is the self-locking process schematic diagram of data deposit unit among the present invention;
Fig. 6 is for outputing to the signal path of digital to analog converter control end from comparator.
Embodiment
Shown in Fig. 1-6, the traditional relatively scheme of circuit of the present invention has following several change: the firstth, the d type flip flop in traditional data register has been transformed into the dynamic circuit 235 shown in the dashed circle of Fig. 3 the inside.Different with traditional d type flip flop that has only a clock input, new dynamic circuit (to call new data deposit unit in the following text) comprises two input end of clock: the first input end of clock Ck
iWith second clock input Ck
I+1, wherein, Ck
iBe coupled to the output 142-i of i shifting deposit unit, Ck
I+1Be coupled to the output 142-i+1 of i+1 shifting deposit unit.
New data deposit unit 235 comprises the first transistor 300, transistor seconds 330, the three transistors 320, the four transistors 325; Short circuit capacitance 315, self-lock switch 335, the first inverters 305, the second inverters 310, the three inverters 340.The source end of the first transistor 300 is coupled to power supply (first current potential), and the drain terminal of the first transistor 300 and transistor seconds 330 is coupled to the input of first inverter 305, and the output 302 of data deposit unit is coupled in the output of first inverter; The source end of transistor seconds 330 and the drain terminal of the 3rd transistor 320 are coupled to ground (second current potential) by short circuit capacitance 315; The source end of the 3rd transistor 320 is coupled to the drain terminal of the 4th transistor 325; The source end of the 4th transistor 325 is coupled to ground (second current potential).The grid end of the first transistor 300 is coupled to the first input end of clock Ck of data deposit unit 235
iThe grid end of transistor seconds is coupled to the data input pin D of data deposit unit 235.The 3rd transistorized grid end and the 4th transistorized grid end can exchange, and are coupled to data deposit unit 235 first input end of clock Ck respectively
iOr the output of second inverter.The input of second inverter is second clock Cki+1.
After the drain terminal of the first transistor and transistor seconds passes through the time delay module that is made of first and second inverter, be coupled to an end of self-lock switch 335,335 the other end is coupled to source end and the 3rd transistorized drain terminal of transistor seconds; Self-lock switch is by the second clock input control of data deposit unit; Ck
iBe coupled to the output 142-i of i shifting deposit unit, Ck
I+1Be coupled to the output 142-(i+1 of i+1 shifting deposit unit).
The clock input that second kind of change of the scheme that circuit of the present invention is traditional relatively is shift register changes the control clock 131 of comparator into.Like this, before comparator 105 output results, shift register 120 is just ready.New data deposit unit 235 is only at Cki=1, and ability gating during Cki+1=0 that is to say that the first transistor 300 disconnects, the 3rd, the 4th transistor turns, the state that self-lock switch 335 disconnects.This data deposit unit 235 comes down to the dynamic circuit of precharge logical, as long as comparator 105 output comparative results, node 301 just can be exported its anti-phase result.If but do not have short circuit capacitance 315, and that discharging current will be through three transistors, and the time-delay that causes is approximately the time-delay of 6 inverters, and this is compared with traditional sequential logical circuit that is made of d type flip flop, and the advantage on the speed is also not obvious.Add that short circuit capacitance is equivalent to ac short circuit after the short circuit capacitance 315, the spark electric current will flow directly to ground by it, and the logical time delay of this one-level has been narrowed down to an inverter time-delay, compare traditional sequential logical circuit, and significant speed advantage is arranged.
Yet if not by inverter 305,310 and the self-locking circuit that constitutes of self-lock switch 335, this data deposit unit 235 can not keep this operation result always.Though before the result of comparator output next time, Cki and Cki+1 are equal to 1, a meeting in the three or four transistor disconnects, avoided the continuous discharge electric current on ground, but because the existence of short circuit capacitance, electric charge on the node 301 can with short circuit capacitance on electric charge redistribute (if transistor seconds conducting), cause the mistake output result of this data deposit unit 235.Therefore, the self-locking circuit of the present invention's design, when the 3rd or the 4th transistor ends, closed self-lock switch 335 forces to make the logic level of node 303 to equal the logic level of node 301, like this, after the comparative result of next comparator arrives, no matter whether conducting of transistor seconds, can not change the logic level of node 301, just can not change the output result of this data deposit unit 235 yet.
Another circuit skill of hiding is, whole approach logical circuit one by one and reset in, Ck1-Ckn all becomes logical zero, comparator 105 also resets, the first transistor conducting, and transistor seconds ends, the the 3rd or the 4th transistor ends, node 301 is charged to logic high, and node 303 will keep former logic level, rather than the logic low wanted of the present invention.Only be strobed at data deposit unit 235-i, Cki=1, the moment of Cki+1=0, the equal conducting of the three or four transistor, node 303 just can be discharged.So the size of short circuit capacitance must be through well-designed, to guarantee that node 303 is fully discharged before comparator output comparative result.
Because nmos pass transistor compares the PMOS transistor, corresponding speed is faster, so the first transistor of the present invention is the p-type MOS transistor, second, third, the 4th transistor is n type MOS transistor.
In fact, the first transistor is designed to n type MOS transistor, second, third, the 4th transistor is that the p-type MOS transistor also can realize similar functions, but performance is poor slightly.In order to make this change operate as normal, need the corresponding polarity of adjusting comparator, make its output at reset mode can make transistor seconds normally end.
Shifting deposit unit in the present embodiment is realized by d type flip flop.
The non-elaborated part of the present invention belongs to techniques well known.
More than disclosed only be specific embodiments of the invention.According to technological thought provided by the invention, those skilled in the art can think and variation, all should fall within the scope of protection of the present invention.
Claims (6)
1. a gradual approaching A/D converter comprises a digital to analog converter, a comparator, and one is approached logical circuit one by one, a clock source;
The described control logic circuit that approaches one by one comprises a shift register, a data register;
Described shift register has an input, an input end of clock, some outputs;
Described shift register is an array of being made up of some shifting deposit units, and each described shifting deposit unit all has a data input, an output, an input end of clock;
The data input pin of each described shifting deposit unit is coupled to the output of upper level, the data input pin of first described shifting deposit unit is coupled to the input of described shift register, the input end of clock of each described shifting deposit unit is coupled to the input end of clock of described shift register, and the output of each described shifting deposit unit is coupled to one of some outputs of described shift register;
Described data register comprises an array of being made up of some data deposit units, and each described data deposit unit all has a data input, an output;
The data input pin of each described data deposit unit is coupled to the output of described comparator, and the output of each described data deposit unit is coupled to one of some inputs of described digital to analog converter;
The output of described comparator comparator input signal and digital to analog converter;
Described comparator is controlled in described clock source;
It is characterized in that:
Each described data deposit unit also has first and second input end of clock;
Each described data deposit unit all comprises first, second, third, fourth transistor, first and second current potential, a short circuit capacitance, a self-lock switch, first, second, third inverter;
Described first, second, third, fourth transistor has the grid end, source end and drain terminal;
The source end of described the first transistor is coupled to first current potential of described data deposit unit;
Described first and second transistorized drain terminal is coupled to the output of described data deposit unit after through first inverter;
The source end of described transistor seconds and the 3rd transistorized drain terminal are coupled to second current potential of described data deposit unit by described short circuit capacitance;
The described the 3rd transistorized source end is coupled to the described the 4th transistorized drain terminal;
The described the 4th transistorized source end is coupled to second current potential of described data deposit unit;
The grid end of described the first transistor is coupled to first input end of clock of described data deposit unit;
The grid end of described transistor seconds is coupled to the data input pin of described data deposit unit;
The described the 3rd transistorized grid end and the 4th transistorized grid end can exchange, and are coupled to the output of described first input end of clock or the 3rd inverter respectively;
The input of described the 3rd inverter is coupled to described second clock input;
The output of described data deposit unit is coupled to an end of described self-lock switch by described second inverter, and the other end of described self-lock switch is coupled to source end and the 3rd transistorized drain terminal of described transistor seconds;
Described self-lock switch is by the second clock input control of described data deposit unit;
First input end of clock of each described data deposit unit is coupled to the output of one of described shifting deposit unit, and the second clock input of each described data deposit unit is coupled to the output of the next stage of one of described shifting deposit unit.
2. gradual approaching A/D converter according to claim 1, it is characterized in that: described the first transistor is the p-type MOS transistor, second, third, the 4th transistor is n type MOS transistor.
3. gradual approaching A/D converter according to claim 1, it is characterized in that: described the first transistor is n type MOS transistor, second, third, the 4th transistor is the p-type MOS transistor.
4. gradual approaching A/D converter according to claim 1, it is characterized in that: described self-lock switch is cmos transmission gate.
5. gradual approaching A/D converter according to claim 1, it is characterized in that: described short circuit capacitance is realized by mos capacitance.
6. gradual approaching A/D converter according to claim 1, it is characterized in that: described shifting deposit unit is d type flip flop.
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| CN103929178A (en) * | 2014-04-29 | 2014-07-16 | 中国电子科技集团公司第二十四研究所 | Successive approximation analog-digital converter and conversion method thereof |
| CN104967450A (en) * | 2015-07-28 | 2015-10-07 | 西安电子科技大学 | Control logic circuit with low fan-in |
| CN105070318A (en) * | 2015-08-06 | 2015-11-18 | 中国电子科技集团公司第二十四研究所 | High-speed shift register applied to successive approximation type analog-to-digital converter |
| CN109687872A (en) * | 2019-02-26 | 2019-04-26 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit and sampling adjustment method for SAR_ADC |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| CN111030697A (en) * | 2019-12-31 | 2020-04-17 | 江苏科大亨芯半导体技术有限公司 | High-speed low-power-consumption successive approximation type analog-to-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929178A (en) * | 2014-04-29 | 2014-07-16 | 中国电子科技集团公司第二十四研究所 | Successive approximation analog-digital converter and conversion method thereof |
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| CN104967450A (en) * | 2015-07-28 | 2015-10-07 | 西安电子科技大学 | Control logic circuit with low fan-in |
| CN104967450B (en) * | 2015-07-28 | 2018-01-16 | 西安电子科技大学 | Control logic circuit with low fan-in |
| CN105070318A (en) * | 2015-08-06 | 2015-11-18 | 中国电子科技集团公司第二十四研究所 | High-speed shift register applied to successive approximation type analog-to-digital converter |
| CN105070318B (en) * | 2015-08-06 | 2019-01-11 | 中国电子科技集团公司第二十四研究所 | A kind of high speed shift register applied to gradual approaching A/D converter |
| CN109687872A (en) * | 2019-02-26 | 2019-04-26 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit and sampling adjustment method for SAR_ADC |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| CN111030697A (en) * | 2019-12-31 | 2020-04-17 | 江苏科大亨芯半导体技术有限公司 | High-speed low-power-consumption successive approximation type analog-to-digital converter |
| CN111030697B (en) * | 2019-12-31 | 2023-04-25 | 江苏科大亨芯半导体技术有限公司 | High-speed low-power-consumption successive approximation type analog-to-digital converter |
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