CN104967450A - Control logic circuit with low fan-in - Google Patents

Control logic circuit with low fan-in Download PDF

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CN104967450A
CN104967450A CN201510451112.3A CN201510451112A CN104967450A CN 104967450 A CN104967450 A CN 104967450A CN 201510451112 A CN201510451112 A CN 201510451112A CN 104967450 A CN104967450 A CN 104967450A
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dynamic logic
logic cells
input
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cells
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CN104967450B (en
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王玉涛
姚娇娇
朱樟明
梁宇华
杨银堂
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Xidian University
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Xidian University
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Abstract

The invention discloses a control logic circuit with low fan-in. The control logic circuit is characterized in that the control logic circuit comprises a main control logic trigger circuit, a main control logic circuit and a sub control logic circuit; the main control logic trigger circuit is used for generating a triggering signal driving the main control logic circuit to work; the main control logic circuit is used for generating input of the sub control logic circuit and comprises an and gate and four same dynamic logic units; the dynamic logic units are used for dividing 16 comparison results of a comparator into four groups and latching the four groups in order; each sub control logic circuit comprises four NOR gates and 16 same dynamic logic units, and the dynamic logic units are used for latching and outputting 16 latching results of the main control logic circuit. The beneficial effects of the control logic circuit with low fan-in are that the control logic circuit has low fan-in in the premise of meeting low-latching time, fan-out of a comparator is lowered, and thus the comparator can work in a high speed.

Description

There is the control logic circuit of low fan-in
Technical field
The present invention relates to a kind of control logic circuit, be specifically related to a kind of control logic circuit with low fan-in, belong to field of analog integrated circuit.
Background technology
SAR ADC (gradual approaching A/D converter), due to advantages such as its structure are simple, low in energy consumption, easy of integration, area is little, becomes the study hotspot of industrial quarters and academia in recent years.The design of high speed SAR ADC is mainly subject to the restriction of the speed of comparator and the settling time of DAC network.Along with the raising of SAR ADC precision, adopt traditional control logic circuit, the load capacitance of comparator can corresponding increase a lot, make the design of high-speed comparator more difficult.If the number of the dynamic logic unit of control logic part can be reduced, to reduce the load capacitance of comparator, so the speed of comparator will promote greatly.
In view of the foregoing, a kind of novel low fan-in dynamic logic circuit becomes a kind of demand.
Summary of the invention
The object of the present invention is to provide a kind of control logic circuit with low fan-in, by the circuit form being divided into main control logic circuit different with sub-control logic circuit two kinds the dynamic logic unit in control logic circuit, make the load of comparator in 16 SAR ADC reduce to original 1/4th, and ensure latch correct for 16 comparative results to export.
In order to realize above-mentioned target, the present invention adopts following technical scheme:
There is a control logic circuit for low fan-in, it is characterized in that, be arranged in analog to digital converter, comprising: main control logic circuits for triggering, main control logic circuit and sub-control logic circuit, wherein:
Aforementioned main control logic circuits for triggering are for generation of the triggering signal making main control logic circuit work;
Aforementioned main control logic circuit is for generation of the input of sub-control logic circuit, and it comprises 1 dynamic logic unit identical with 4 with door, and these 4 dynamic logic unit are used for 16 of comparator comparative results to divide 4 groups to latch successively;
Aforementioned sub-control logic circuit comprises 4 NOR gate dynamic logic unit identical with 16, and these 16 dynamic logic unit are used for 16 of main control logic circuit latch result to latch output respectively.
The aforesaid control logic circuit with low fan-in, is characterized in that, aforementioned main control logic circuits for triggering comprise: inverter I1, same or door XNOR, buffer BUF, inverter I2 and NAND gate NAND, wherein:
The input of aforementioned inverter I1 meets sampling clock Sample, output and an aforementioned input that is same or door XNOR of aforementioned inverter I1 connect aforementioned sub-control logic circuit, aforementioned with or another input of door XNOR and the input of aforementioned buffers BUF connect aforementioned main control logic circuit, the output of aforementioned buffers BUF connects the input of aforementioned inverter I2, and the output of aforementioned inverter I2 and aforementioned output that is same or door XNOR connect two inputs of aforementioned NAND gate NAND respectively; The output of aforementioned NAND gate NAND connects the input of aforementioned main control logic circuit;
The output signal S of aforementioned inverter I1 0as the input signal of sub-control logic circuit, the output signal of aforementioned NAND gate NAND is as the triggering signal of aforementioned main control logic circuit.
The aforesaid control logic circuit with low fan-in, is characterized in that, aforementioned main control logic circuit comprises: with door AND, dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic cells D L4, wherein:
Aforementioned with door AND one inputs, the input CMPP short circuit of the input CMPP of the input CMPP of aforementioned dynamic logic cells D L1, aforementioned dynamic logic cells D L2, the input CMPP of aforementioned dynamic logic cells D L3 and aforementioned dynamic logic cells D L4 meet the positive output CMPP of comparator, and aforementioned another with door AND inputs, the input CMPN short circuit of the input CMPN of the input CMPN of aforementioned dynamic logic cells D L1, aforementioned dynamic logic cells D L2, the input CMPN of aforementioned dynamic logic cells D L3 and aforementioned dynamic logic cells D L4 meet the negative output CMPN of comparator;
The input CLK short circuit of aforementioned dynamic logic cells D L1, aforementioned dynamic logic cells D L2, aforementioned dynamic logic cells D L3 and aforementioned dynamic logic cells D L4 also connects output that is aforementioned and door AND;
The input D of aforementioned dynamic logic cells D L1 connects the output of aforementioned main control logic circuits for triggering, the output Q of aforementioned dynamic logic cells D L1 meets the input D of aforementioned dynamic logic cells D L2, and output P and N of aforementioned dynamic logic cells D L1 connects aforementioned sub-control logic circuit;
The output Q of aforementioned dynamic logic cells D L2 meets the input D of aforementioned dynamic logic cells D L3, and output P and N of aforementioned dynamic logic cells D L2 connects aforementioned sub-control logic circuit;
The output Q of aforementioned dynamic logic cells D L3 meets the input D of aforementioned dynamic logic cells D L4, and output P and N of aforementioned dynamic logic cells D L3 connects aforementioned sub-control logic circuit;
The output Q of aforementioned dynamic logic cells D L4 connects aforementioned main control logic circuits for triggering, and output P and N of aforementioned dynamic logic cells D L4 connects aforementioned sub-control logic circuit;
The output signal P1 that aforementioned dynamic logic cells D L1 produces 0and N1 0, the output signal P2 that produces of aforementioned dynamic logic cells D L2 0and N2 0, the output signal P3 that produces of aforementioned dynamic logic cells D L3 0and N3 0and the output signal P4 that aforementioned dynamic logic cells D L4 produces 0and N4 0as the input signal of sub-control logic circuit;
The output signal Q that aforementioned main control logic circuit produces 0as the input signal of main control logic circuits for triggering.
The aforesaid control logic circuit with low fan-in, it is characterized in that, aforementioned sub-control logic circuit comprises: NOR gate NOR1, dynamic logic cells D L5, dynamic logic cells D L6, dynamic logic cells D L7, dynamic logic cells D L8, NOR gate NOR2, dynamic logic cells D L9, dynamic logic cells D L10, dynamic logic cells D L11, dynamic logic cells D L12, NOR gate NOR3, dynamic logic cells D L13, dynamic logic cells D L14, dynamic logic cells D L15, dynamic logic cells D L16, NOR gate NOR4, dynamic logic cells D L17, dynamic logic cells D L18, dynamic logic cells D L19 and dynamic logic cells D L20, wherein:
The input D of aforementioned dynamic logic cells D L5, the input D of aforementioned dynamic logic cells D L9, the input D of aforementioned dynamic logic cells D L13 and the input D short circuit of aforementioned dynamic logic cells D L17 also connect main control logic circuits for triggering;
The input CMPP of an input of aforementioned NOR gate NOR1, aforementioned dynamic logic cells D L5, the input CMPP of aforementioned dynamic logic cells D L6, the input CMPP of aforementioned dynamic logic cells D L7 and the input CMPP short circuit of aforementioned dynamic logic cells D L8 also meet the output signal P1 of main dynamic logic circuit 0, another input of aforementioned NOR gate NOR1, the input CMPN short circuit of the input CMPN of aforementioned dynamic logic cells D L5, the input CMPN of aforementioned dynamic logic cells D L6, the input CMPN of aforementioned dynamic logic cells D L7 and aforementioned dynamic logic cells D L8 meet the output signal N1 of main dynamic logic circuit 0the input CLK of aforementioned dynamic logic cells D L5, the input CLK of aforementioned dynamic logic cells D L6, the input CLK of aforementioned dynamic logic cells D L7 and the input CLK short circuit of aforementioned dynamic logic cells D L8 also connect the output of aforementioned NOR gate NOR1, the output Q of aforementioned dynamic logic cells D L5 meets the input D of aforementioned dynamic logic cells D L6, the output Q of aforementioned dynamic logic cells D L6 meets the input D of aforementioned dynamic logic cells D L7, and the output Q of aforementioned dynamic logic cells D L7 meets the input D of aforementioned dynamic logic cells D L8;
The input CMPP of an input of aforementioned NOR gate NOR2, aforementioned dynamic logic cells D L9, the input CMPP of aforementioned dynamic logic cells D L10, the input CMPP of aforementioned dynamic logic cells D L11 and the input CMPP short circuit of aforementioned dynamic logic cells D L12 also meet the output signal P2 of main dynamic logic circuit 0, another input of aforementioned NOR gate NOR2, the input CMPN short circuit of the input CMPN of aforementioned dynamic logic cells D L9, the input CMPN of aforementioned dynamic logic cells D L10, the input CMPN of aforementioned dynamic logic cells D L11 and aforementioned dynamic logic cells D L12 meet the output signal N2 of main dynamic logic circuit 0the input CLK of aforementioned dynamic logic cells D L9, the input CLK of aforementioned dynamic logic cells D L10, the input CLK of aforementioned dynamic logic cells D L11 and the input CLK short circuit of aforementioned dynamic logic cells D L12 also connect the output of aforementioned NOR gate NOR2, the output Q of aforementioned dynamic logic cells D L9 meets the input D of aforementioned dynamic logic cells D L10, the output Q of aforementioned dynamic logic cells D L10 meets the input D of aforementioned dynamic logic cells D L11, and the output Q of aforementioned dynamic logic cells D L11 meets the input D of aforementioned dynamic logic cells D L12;
The input CMPP of an input of aforementioned NOR gate NOR3, aforementioned dynamic logic cells D L13, the input CMPP of aforementioned dynamic logic cells D L14, the input CMPP of aforementioned dynamic logic cells D L15 and the input CMPP short circuit of aforementioned dynamic logic cells D L16 also meet the output signal P3 of main dynamic logic circuit 0, another input of aforementioned NOR gate NOR2, the input CMPN short circuit of the input CMPN of aforementioned dynamic logic cells D L13, the input CMPN of aforementioned dynamic logic cells D L14, the input CMPN of aforementioned dynamic logic cells D L15 and aforementioned dynamic logic cells D L16 meet the output signal N3 of main dynamic logic circuit 0the input CLK of aforementioned dynamic logic cells D L13, the input CLK of aforementioned dynamic logic cells D L14, the input CLK of aforementioned dynamic logic cells D L15 and the input CLK short circuit of aforementioned dynamic logic cells D L16 also connect the output of aforementioned NOR gate NOR3, the output Q of aforementioned dynamic logic cells D L13 meets the input D of aforementioned dynamic logic cells D L14, the output Q of aforementioned dynamic logic cells D L14 meets the input D of aforementioned dynamic logic cells D L15, and the output Q of aforementioned dynamic logic cells D L15 meets the input D of aforementioned dynamic logic circuit DL16;
The input CMPP of an input of aforementioned NOR gate NOR4, aforementioned dynamic logic cells D L17, the input CMPP of aforementioned dynamic logic cells D L18, the input CMPP of aforementioned dynamic logic cells D L19 and the input CMPP short circuit of aforementioned dynamic logic cells D L20 also meet the output signal P4 of main dynamic logic circuit 0, another input of aforementioned NOR gate NOR4, the input CMPN short circuit of the input CMPN of aforementioned dynamic logic cells D L17, the input CMPN of aforementioned dynamic logic cells D L18, the input CMPN of aforementioned dynamic logic cells D L19 and aforementioned dynamic logic cells D L20 meet the output signal N4 of main dynamic logic circuit 0the input CLK of aforementioned dynamic logic cells D L17, the input CLK of aforementioned dynamic logic cells D L18, the input CLK of aforementioned dynamic logic cells D L19 and the input CLK short circuit of aforementioned dynamic logic cells D L20 also connect the output of aforementioned NOR gate NOR4, the output Q of aforementioned dynamic logic cells D L17 meets the input D of aforementioned dynamic logic cells D L18, the output Q of aforementioned dynamic logic cells D L18 meets the input D of aforementioned dynamic logic cells D L19, and the output Q of aforementioned dynamic logic cells D L19 meets the input D of aforementioned dynamic logic cells D L20;
Aforementioned dynamic logic cells D L5 produces output signal P1 and N1, aforementioned dynamic logic cells D L9 produces output signal P2 and N2, aforementioned dynamic logic cells D L13 produces output signal P3 and N3, aforementioned dynamic logic cells D L17 produces output signal P4 and N4, aforementioned dynamic logic cells D L6 produces output signal P5 and N5, aforementioned dynamic logic cells D L10 produces output signal P6 and N6, aforementioned dynamic logic cells D L14 produces output signal P7 and N7, aforementioned dynamic logic cells D L18 produces output signal P8 and N8, aforementioned dynamic logic cells D L7 produces output signal P9 and N9, aforementioned dynamic logic cells D L11 produces output signal P10 and N10, aforementioned dynamic logic cells D L15 produces output signal P11 and N11, aforementioned dynamic logic cells D L19 produces output signal P12 and N12, aforementioned dynamic logic cells D L8 produces output signal P13 and N13, aforementioned dynamic logic cells D L12 produces output signal P14 and N14, aforementioned dynamic logic cells D L16 produces output signal P15 and N15, aforementioned dynamic logic cells D L20 produces output signal P16 and N16.
Usefulness of the present invention is: because 4 dynamic logic unit in main control logic circuit are used by repetitive cycling, carry out 16 comparative results of latched comparator, the load of comparator is made to be reduced to 4 dynamic logic unit from traditional 16 dynamic logic unit, so under the prerequisite meeting the low latch time, control logic circuit of the present invention has lower fan-in, reduce the fan-out of comparator, comparator is worked at faster speed.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of control logic circuit of the present invention;
Fig. 2 is the circuit structure diagram of dynamic logic unit in main control logic circuit;
Fig. 3 is the circuit structure diagram of dynamic logic unit in sub-control logic circuit.
Embodiment
Control logic circuit of the present invention is arranged in analog to digital converter.
Below in conjunction with the drawings and specific embodiments, concrete introduction is done to the present invention.
First, the structure of control logic circuit of the present invention is introduced.
With reference to Fig. 1, the control logic circuit with low fan-in of the present invention, it comprises: main control logic circuits for triggering, main control logic circuit and sub-control logic circuit, and wherein, main control logic circuits for triggering are for generation of the triggering signal making main control logic circuit work; Main control logic circuit is for generation of the input of sub-control logic circuit, and it comprises 1 dynamic logic unit identical with 4 with door, and these 4 dynamic logic unit are used for 16 of comparator comparative results to divide 4 groups to latch successively; Sub-control logic circuit comprises 4 NOR gate dynamic logic unit identical with 16, and these 16 dynamic logic unit are used for 16 of main control logic circuit latch result to latch output respectively.
Introduce these three circuit of main control logic circuits for triggering, main control logic circuit and sub-control logic circuit below respectively in detail.
One, main control logic circuits for triggering
With reference to Fig. 1, main control logic circuits for triggering comprise: inverter I1, same or door XNOR, buffer BUF, inverter I2 and NAND gate NAND.
In these main control logic circuits for triggering, annexation between each components and parts is: the input of inverter I1 meets sampling clock Sample, output and an input that is same or door XNOR of inverter I1 connect sub-control logic circuit, with or another input of door XNOR and the input of buffer BUF connect main control logic circuit, the output of buffer BUF connects the input of inverter I2, and the output of inverter I2 and output that is same or door XNOR connect two inputs of NAND gate NAND respectively; The output of NAND gate NAND connects the input of main control logic circuit.
The output signal S of inverter I1 0as the input signal of sub-control logic circuit, the output signal of NAND gate NAND is as the triggering signal of main control logic circuit.
Two, main control logic circuit
With reference to Fig. 1, main control logic circuit comprises: with door AND, dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic cells D L4, wherein, 4 dynamic logic unit are used for 16 of comparator comparative results to divide 4 groups to latch successively.
In main control logic circuit, annexation between each components and parts is: input with one of door AND, the input CMPP of dynamic logic cells D L1, the input CMPP of dynamic logic cells D L2, the input CMPP of dynamic logic cells D L3 and the input CMPP short circuit of dynamic logic cells D L4 also meet the positive output CMPP of comparator, input with another of door AND, the input CMPN of dynamic logic cells D L1, the input CMPN of dynamic logic cells D L2, the input CMPN of dynamic logic cells D L3 and the input CMPN short circuit of dynamic logic cells D L4 also meet the negative output CMPN of comparator,
The input CLK short circuit of dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic cells D L4 also connects the output with door AND;
The input D of dynamic logic cells D L1 connects the output of main control logic circuits for triggering, and the output Q of dynamic logic cells D L1 meets the input D of dynamic logic cells D L2, and output P and N of dynamic logic cells D L1 connects sub-control logic circuit;
The output Q of dynamic logic cells D L2 meets the input D of dynamic logic cells D L3, and output P and N of dynamic logic cells D L2 connects sub-control logic circuit;
The output Q of dynamic logic cells D L3 meets the input D of dynamic logic cells D L4, and output P and N of dynamic logic cells D L3 connects sub-control logic circuit;
The output Q of dynamic logic cells D L4 connects main control logic circuits for triggering, and output P and N of dynamic logic cells D L4 connects sub-control logic circuit.
The output signal P1 that dynamic logic cells D L1 produces 0and N1 0, dynamic logic cells D L2 produce output signal P2 0and N2 0, dynamic logic cells D L3 produce output signal P3 0and N3 0and the output signal P4 that dynamic logic cells D L4 produces 0and N4 0as the input signal of sub-control logic circuit.
The output signal Q that main control logic circuit produces 0as the input signal of main control logic circuits for triggering.
Three, sub-control logic circuit
With reference to Fig. 1, sub-control logic circuit comprises: NOR gate NOR1, dynamic logic cells D L5, dynamic logic cells D L6, dynamic logic cells D L7, dynamic logic cells D L8, NOR gate NOR2, dynamic logic cells D L9, dynamic logic cells D L10, dynamic logic cells D L11, dynamic logic cells D L12, NOR gate NOR3, dynamic logic cells D L13, dynamic logic cells D L14, dynamic logic cells D L15, dynamic logic cells D L16, NOR gate NOR4, dynamic logic cells D L17, dynamic logic cells D L18, dynamic logic cells D L19 and dynamic logic cells D L20, wherein, these 16 dynamic logic unit are used for 16 of main control logic circuit latch result to latch output respectively.
In sub-control logic circuit, the annexation between each components and parts is: the input D of dynamic logic cells D L5, the input D of dynamic logic cells D L9, the input D of dynamic logic cells D L13 and the input D short circuit of dynamic logic cells D L17 also connect main control logic circuits for triggering;
The input CMPP short circuit of an input of NOR gate NOR1, input CMPP, the input CMPP of dynamic logic cells D L6 of dynamic logic cells D L5, the input CMPP of dynamic logic cells D L7 and dynamic logic cells D L8 also meets the output signal P1 of main dynamic logic circuit 0, another input of NOR gate NOR1, input CMPN, the input CMPN of dynamic logic cells D L6 of dynamic logic cells D L5, the input CMPN short circuit of the input CMPN of dynamic logic cells D L7 and dynamic logic cells D L8 meet the output signal N1 of main dynamic logic circuit 0the input CLK of dynamic logic cells D L5, the input CLK of dynamic logic cells D L6, the input CLK of dynamic logic cells D L7 and the input CLK short circuit of dynamic logic cells D L8 also connect the output of NOR gate NOR1, the output Q of dynamic logic cells D L5 meets the input D of dynamic logic cells D L6, the output Q of dynamic logic cells D L6 meets the input D of dynamic logic cells D L7, and the output Q of dynamic logic cells D L7 meets the input D of dynamic logic cells D L8;
The input CMPP short circuit of an input of NOR gate NOR2, input CMPP, the input CMPP of dynamic logic cells D L10 of dynamic logic cells D L9, the input CMPP of dynamic logic cells D L11 and dynamic logic cells D L12 also meets the output signal P2 of main dynamic logic circuit 0, another input of NOR gate NOR2, input CMPN, the input CMPN of dynamic logic cells D L10 of dynamic logic cells D L9, the input CMPN short circuit of the input CMPN of dynamic logic cells D L11 and dynamic logic cells D L12 meet the output signal N2 of main dynamic logic circuit 0the input CLK of dynamic logic cells D L9, the input CLK of dynamic logic cells D L10, the input CLK of dynamic logic cells D L11 and the input CLK short circuit of dynamic logic cells D L12 also connect the output of NOR gate NOR2, the output Q of dynamic logic cells D L9 meets the input D of dynamic logic cells D L10, the output Q of dynamic logic cells D L10 meets the input D of dynamic logic cells D L11, and the output Q of dynamic logic cells D L11 meets the input D of dynamic logic cells D L12;
The input CMPP short circuit of an input of NOR gate NOR3, input CMPP, the input CMPP of dynamic logic cells D L14 of dynamic logic cells D L13, the input CMPP of dynamic logic cells D L15 and dynamic logic cells D L16 also meets the output signal P3 of main dynamic logic circuit 0, another input of NOR gate NOR2, input CMPN, the input CMPN of dynamic logic cells D L14 of dynamic logic cells D L13, the input CMPN short circuit of the input CMPN of dynamic logic cells D L15 and dynamic logic cells D L16 meet the output signal N3 of main dynamic logic circuit 0the input CLK of dynamic logic cells D L13, the input CLK of dynamic logic cells D L14, the input CLK of dynamic logic cells D L15 and the input CLK short circuit of dynamic logic cells D L16 also connect the output of NOR gate NOR3, the output Q of dynamic logic cells D L13 meets the input D of dynamic logic cells D L14, the output Q of dynamic logic cells D L14 meets the input D of dynamic logic cells D L15, and the output Q of dynamic logic cells D L15 meets the input D of dynamic logic circuit DL16;
The input CMPP short circuit of an input of NOR gate NOR4, input CMPP, the input CMPP of dynamic logic cells D L18 of dynamic logic cells D L17, the input CMPP of dynamic logic cells D L19 and dynamic logic cells D L20 also meets the output signal P4 of main dynamic logic circuit 0, another input of NOR gate NOR4, input CMPN, the input CMPN of dynamic logic cells D L18 of dynamic logic cells D L17, the input CMPN short circuit of the input CMPN of dynamic logic cells D L19 and dynamic logic cells D L20 meet the output signal N4 of main dynamic logic circuit 0the input CLK of dynamic logic cells D L17, the input CLK of dynamic logic cells D L18, the input CLK of dynamic logic cells D L19 and the input CLK short circuit of dynamic logic cells D L20 also connect the output of NOR gate NOR4, the output Q of dynamic logic cells D L17 meets the input D of dynamic logic cells D L18, the output Q of dynamic logic cells D L18 meets the input D of dynamic logic cells D L19, and the output Q of dynamic logic cells D L19 meets the input D of dynamic logic cells D L20.
Dynamic logic cells D L5 produces output signal P1 and N1, dynamic logic cells D L9 produces output signal P2 and N2, dynamic logic cells D L13 produces output signal P3 and N3, dynamic logic cells D L17 produces output signal P4 and N4, dynamic logic cells D L6 produces output signal P5 and N5, dynamic logic cells D L10 produces output signal P6 and N6, dynamic logic cells D L14 produces output signal P7 and N7, dynamic logic cells D L18 produces output signal P8 and N8, dynamic logic cells D L7 produces output signal P9 and N9, dynamic logic cells D L11 produces output signal P10 and N10, dynamic logic cells D L15 produces output signal P11 and N11, dynamic logic cells D L19 produces output signal P12 and N12, dynamic logic cells D L8 produces output signal P13 and N13, dynamic logic cells D L12 produces output signal P14 and N14, dynamic logic cells D L16 produces output signal P15 and N15, dynamic logic cells D L20 produces output signal P16 and N16.
Next, the operation principle of control logic circuit of the present invention is introduced.
After sampling terminates (namely Sample signal becomes low level), produce triggering signal by main control logic circuits for triggering, make DL5, DL9, DL13 and DL17 in the DL1 in main control logic circuit and sub-control logic circuit enter the preparation stage.When the output of comparator is effective (CMPP and CMPN is respectively 1/0 or 0/1), CMPP and CMPN is latched fast by DL1 and outputs to dynamic logic cells D L5, and dynamic logic cells D L5 is by P1 0and N1 0latch and export, producing top digit output code P1 (N1).Meanwhile, the control signal that DL1 produces is input to the input D of DL2, makes DL2 enter the preparation stage.When comparator output again effectively time, CMPP and CMPN is latched fast by DL2 and outputs to dynamic logic cells D L9, and dynamic logic cells D L9 is by P2 0and N2 0latch and export and produce time high-order digit output code P2 (N2).In this way until produce digital output code P4 (N4).
After front 4 bit codes latch, DL4 produces control signal Q 0, after this control signal enters main control logic circuits for triggering, carry out logical operation with Sample signal and produce low level control signal and make the of short duration reset of DL1, reenter the preparation stage afterwards.The course of work is same as described above afterwards, just 5th ~ 8 bit codes is latched by DL6, DL10, DL14 and the DL18 in sub-control logic circuit and export to produce digital code P5 (N5) ~ P8 (N8).
After front 8 bit codes latch, DL4 produces control signal and again makes the of short duration reset of DL1, then reenters the preparation stage.Said process repeats always, until the comparative result of 16 times all latches output, produce P1 (N1) ~ P16 (N16), the latching process of a change-over period terminates.
Fig. 2 is the internal circuit configuration figure of the dynamic logic unit (DL1 ~ DL4) in main control logic circuit of the present invention.When D is high level, and when CLK is high level by low transition, the output signal CMPP of comparator and CMPN is delivered to P and N and latches output.Only when D becomes after low level makes circuit reset again, second time could be carried out to CMPP and CMPN and latch.This dynamic logic circuit is exactly common, and being applicable to CMPP and CMPN at reseting stage is the situation of 0/0.
Fig. 3 is the internal circuit configuration figure of the dynamic logic unit (DL5 ~ DL20) in sub-control logic circuit of the present invention.When D is high level, and when CLK is high level by low transition, the output signal CMPP of comparator and CMPN is delivered to P and N and latches output.Only when D becomes after low level makes circuit reset again, second time could be carried out to CMPP and CMPN and latch.It is the situation of 1/1 that this dynamic logic circuit is applicable to CMPP and CMPN at reseting stage.
The control logic circuit with low fan-in provided by the invention, because 4 dynamic logic unit in main control logic circuit are used by repetitive cycling, carry out 16 comparative results of latched comparator, the load of comparator is made to be reduced to 4 dynamic logic unit from traditional 16 dynamic logic unit, so it is when meeting normal latched comparator and exporting, its fan-in is 1/4th of traditional control logic circuit, make in the design of high speed SAR ADC, the speed of comparator can obtain very large raising.
For SMIC 180nm CMOS technology, the speed of the comparator of the control logic circuit that contrast access is traditional and access low fan-in control logic circuit of the present invention, supply voltage be 1.8V, input voltage difference for 20mV time, the time delay accessing the comparator of traditional control logic circuit is 930ps, and the time delay accessing the comparator of low fan-in control logic circuit of the present invention only has 470ps, the speed of comparator improves nearly 1 times, and when the speed of comparator is by process technology limit, this technology is still effective to the speed improving comparator.
It should be noted that, above-described embodiment does not limit the present invention in any form, the technical scheme that the mode that all employings are equal to replacement or equivalent transformation obtains, and all drops in protection scope of the present invention.

Claims (4)

1. there is a control logic circuit for low fan-in, it is characterized in that, be arranged in analog to digital converter, comprising: main control logic circuits for triggering, main control logic circuit and sub-control logic circuit, wherein:
Described main control logic circuits for triggering are for generation of the triggering signal making main control logic circuit work;
Described main control logic circuit is for generation of the input of sub-control logic circuit, and it comprises 1 dynamic logic unit identical with 4 with door, and these 4 dynamic logic unit are used for 16 of comparator comparative results to divide 4 groups to latch successively;
Described sub-control logic circuit comprises 4 NOR gate dynamic logic unit identical with 16, and these 16 dynamic logic unit are used for 16 of main control logic circuit latch result to latch output respectively.
2. the control logic circuit with low fan-in according to claim 1, is characterized in that, described main control logic circuits for triggering comprise: inverter I1, same or door XNOR, buffer BUF, inverter I2 and NAND gate NAND, wherein:
The input of described inverter I1 meets sampling clock Sample, output and a described input that is same or door XNOR of described inverter I1 connect described sub-control logic circuit, described with or another input of door XNOR and the input of described buffer BUF connect described main control logic circuit, the output of described buffer BUF connects the input of described inverter I2, and the output of described inverter I2 and described output that is same or door XNOR connect two inputs of described NAND gate NAND respectively; The output of described NAND gate NAND connects the input of described main control logic circuit;
The output signal S of described inverter I1 0as the input signal of sub-control logic circuit, the output signal of described NAND gate NAND is as the triggering signal of described main control logic circuit.
3. the control logic circuit with low fan-in according to claim 1, it is characterized in that, described main control logic circuit comprises: with door AND, dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic cells D L4, wherein:
Described with door AND one inputs, the input CMPP short circuit of the input CMPP of the input CMPP of described dynamic logic cells D L1, described dynamic logic cells D L2, the input CMPP of described dynamic logic cells D L3 and described dynamic logic cells D L4 meet the positive output CMPP of comparator, and described another with door AND inputs, the input CMPN short circuit of the input CMPN of the input CMPN of described dynamic logic cells D L1, described dynamic logic cells D L2, the input CMPN of described dynamic logic cells D L3 and described dynamic logic cells D L4 meet the negative output CMPN of comparator;
The input CLK short circuit of described dynamic logic cells D L1, described dynamic logic cells D L2, described dynamic logic cells D L3 and described dynamic logic cells D L4 also connects output that is described and door AND;
The input D of described dynamic logic cells D L1 connects the output of described main control logic circuits for triggering, the output Q of described dynamic logic cells D L1 meets the input D of described dynamic logic cells D L2, and output P and N of described dynamic logic cells D L1 connects described sub-control logic circuit;
The output Q of described dynamic logic cells D L2 meets the input D of described dynamic logic cells D L3, and output P and N of described dynamic logic cells D L2 connects described sub-control logic circuit;
The output Q of described dynamic logic cells D L3 meets the input D of described dynamic logic cells D L4, and output P and N of described dynamic logic cells D L3 connects described sub-control logic circuit;
The output Q of described dynamic logic cells D L4 connects described main control logic circuits for triggering, and output P and N of described dynamic logic cells D L4 connects described sub-control logic circuit;
The output signal P1 that described dynamic logic cells D L1 produces 0and N1 0, the output signal P2 that produces of described dynamic logic cells D L2 0and N2 0, the output signal P3 that produces of described dynamic logic cells D L3 0and N3 0and the output signal P4 that described dynamic logic cells D L4 produces 0and N4 0as the input signal of sub-control logic circuit;
The output signal Q that described main control logic circuit produces 0as the input signal of main control logic circuits for triggering.
4. the control logic circuit with low fan-in according to claim 1, it is characterized in that, described sub-control logic circuit comprises: NOR gate NOR1, dynamic logic cells D L5, dynamic logic cells D L6, dynamic logic cells D L7, dynamic logic cells D L8, NOR gate NOR2, dynamic logic cells D L9, dynamic logic cells D L10, dynamic logic cells D L11, dynamic logic cells D L12, NOR gate NOR3, dynamic logic cells D L13, dynamic logic cells D L14, dynamic logic cells D L15, dynamic logic cells D L16, NOR gate NOR4, dynamic logic cells D L17, dynamic logic cells D L18, dynamic logic cells D L19 and dynamic logic cells D L20, wherein:
The input D of described dynamic logic cells D L5, the input D of described dynamic logic cells D L9, the input D of described dynamic logic cells D L13 and the input D short circuit of described dynamic logic cells D L17 also connect main control logic circuits for triggering;
The input CMPP of an input of described NOR gate NOR1, described dynamic logic cells D L5, the input CMPP of described dynamic logic cells D L6, the input CMPP of described dynamic logic cells D L7 and the input CMPP short circuit of described dynamic logic cells D L8 also meet the output signal P1 of main dynamic logic circuit 0, another input of described NOR gate NOR1, the input CMPN short circuit of the input CMPN of described dynamic logic cells D L5, the input CMPN of described dynamic logic cells D L6, the input CMPN of described dynamic logic cells D L7 and described dynamic logic cells D L8 meet the output signal N1 of main dynamic logic circuit 0the input CLK of described dynamic logic cells D L5, the input CLK of described dynamic logic cells D L6, the input CLK of described dynamic logic cells D L7 and the input CLK short circuit of described dynamic logic cells D L8 also connect the output of described NOR gate NOR1, the output Q of described dynamic logic cells D L5 meets the input D of described dynamic logic cells D L6, the output Q of described dynamic logic cells D L6 meets the input D of described dynamic logic cells D L7, and the output Q of described dynamic logic cells D L7 meets the input D of described dynamic logic cells D L8;
The input CMPP of an input of described NOR gate NOR2, described dynamic logic cells D L9, the input CMPP of described dynamic logic cells D L10, the input CMPP of described dynamic logic cells D L11 and the input CMPP short circuit of described dynamic logic cells D L12 also meet the output signal P2 of main dynamic logic circuit 0, another input of described NOR gate NOR2, the input CMPN short circuit of the input CMPN of described dynamic logic cells D L9, the input CMPN of described dynamic logic cells D L10, the input CMPN of described dynamic logic cells D L11 and described dynamic logic cells D L12 meet the output signal N2 of main dynamic logic circuit 0the input CLK of described dynamic logic cells D L9, the input CLK of described dynamic logic cells D L10, the input CLK of described dynamic logic cells D L11 and the input CLK short circuit of described dynamic logic cells D L12 also connect the output of described NOR gate NOR2, the output Q of described dynamic logic cells D L9 meets the input D of described dynamic logic cells D L10, the output Q of described dynamic logic cells D L10 meets the input D of described dynamic logic cells D L11, and the output Q of described dynamic logic cells D L11 meets the input D of described dynamic logic cells D L12;
The input CMPP of an input of described NOR gate NOR3, described dynamic logic cells D L13, the input CMPP of described dynamic logic cells D L14, the input CMPP of described dynamic logic cells D L15 and the input CMPP short circuit of described dynamic logic cells D L16 also meet the output signal P3 of main dynamic logic circuit 0, another input of described NOR gate NOR2, the input CMPN short circuit of the input CMPN of described dynamic logic cells D L13, the input CMPN of described dynamic logic cells D L14, the input CMPN of described dynamic logic cells D L15 and described dynamic logic cells D L16 meet the output signal N3 of main dynamic logic circuit 0the input CLK of described dynamic logic cells D L13, the input CLK of described dynamic logic cells D L14, the input CLK of described dynamic logic cells D L15 and the input CLK short circuit of described dynamic logic cells D L16 also connect the output of described NOR gate NOR3, the output Q of described dynamic logic cells D L13 meets the input D of described dynamic logic cells D L14, the output Q of described dynamic logic cells D L14 meets the input D of described dynamic logic cells D L15, and the output Q of described dynamic logic cells D L15 meets the input D of described dynamic logic circuit DL16;
The input CMPP of an input of described NOR gate NOR4, described dynamic logic cells D L17, the input CMPP of described dynamic logic cells D L18, the input CMPP of described dynamic logic cells D L19 and the input CMPP short circuit of described dynamic logic cells D L20 also meet the output signal P4 of main dynamic logic circuit 0, another input of described NOR gate NOR4, the input CMPN short circuit of the input CMPN of described dynamic logic cells D L17, the input CMPN of described dynamic logic cells D L18, the input CMPN of described dynamic logic cells D L19 and described dynamic logic cells D L20 meet the output signal N4 of main dynamic logic circuit 0the input CLK of described dynamic logic cells D L17, the input CLK of described dynamic logic cells D L18, the input CLK of described dynamic logic cells D L19 and the input CLK short circuit of described dynamic logic cells D L20 also connect the output of described NOR gate NOR4, the output Q of described dynamic logic cells D L17 meets the input D of described dynamic logic cells D L18, the output Q of described dynamic logic cells D L18 meets the input D of described dynamic logic cells D L19, and the output Q of described dynamic logic cells D L19 meets the input D of described dynamic logic cells D L20;
Described dynamic logic cells D L5 produces output signal P1 and N1, described dynamic logic cells D L9 produces output signal P2 and N2, described dynamic logic cells D L13 produces output signal P3 and N3, described dynamic logic cells D L17 produces output signal P4 and N4, described dynamic logic cells D L6 produces output signal P5 and N5, described dynamic logic cells D L10 produces output signal P6 and N6, described dynamic logic cells D L14 produces output signal P7 and N7, described dynamic logic cells D L18 produces output signal P8 and N8, described dynamic logic cells D L7 produces output signal P9 and N9, described dynamic logic cells D L11 produces output signal P10 and N10, described dynamic logic cells D L15 produces output signal P11 and N11, described dynamic logic cells D L19 produces output signal P12 and N12, described dynamic logic cells D L8 produces output signal P13 and N13, described dynamic logic cells D L12 produces output signal P14 and N14, described dynamic logic cells D L16 produces output signal P15 and N15, described dynamic logic cells D L20 produces output signal P16 and N16.
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CN103199864A (en) * 2013-02-07 2013-07-10 中国科学技术大学 Successive approximation type analog-digital converter

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CN101558451A (en) * 2006-12-12 2009-10-14 Nxp股份有限公司 Circuit with parallel functional circuits with multi-phase control inputs
CN103199864A (en) * 2013-02-07 2013-07-10 中国科学技术大学 Successive approximation type analog-digital converter
CN103152050A (en) * 2013-03-04 2013-06-12 中国科学技术大学 High-speed successive approximation type analog-to-digital converter

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