CN103208994A - Two-stage time digital convert (TDC) circuit - Google Patents
Two-stage time digital convert (TDC) circuit Download PDFInfo
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Abstract
The invention discloses a two-stage TDC circuit. The two-stage TDC circuit comprises a first counter portion and a second counter portion, wherein the first counter portion comprises a delay unit, a decoding circuit and a latch, a closed-loop delay line type structure is adopted, and the second counter portion is a pseudo random sequence counter. The two-stage TDC circuit is controlled by gating signals, capable of being turned on and off repeatedly, determined in the initial state and rapid in start. The circuit is applied to an array type infrared three-dimensional imaging reading circuit and configured outside, inside or partially outside pixels as required. Compared with an ordinary TDC circuit, the circuit is simple in structure and capable of working at high frequency, improving the temporal resolution, generating stable oscillation frequency simultaneously and satisfying application requirements for small pixel circuit area, low power consumption and high temporal resolution in array type infrared imaging reading circuits.
Description
Technical field
The present invention relates to a kind of time-to-digital conversion circuit, this circuit is used for array type infrared sensing reading circuit.
Background technology
TDC(Time Digital Convert, time-to-digital conversion circuit) be the basic means of time measurement, this technology has consequence and uses widely in fields such as Aero-Space, range finding, metering, measurement.Tradition based on the TDC circuit that analogue technique realizes exposed its job insecurity, be subject to outside noise, shortcomings such as temperature and voltage disturbance, cause its measurement result bigger error to occur, be not suitable for the measurement of large range high precision, limited the development of this technology.Fast development along with digital integrated circuit technology and CMOS technology, advantages such as the TDC circuit that digital technology realizes has that technology is simple, cost is low, portable good, working stability, circuit area are little, the problems referred to above have been solved well, improve certainty of measurement effectively, enlarged measuring range.
Along with the required precision of science and technology for time measurement improves constantly, traditional one-part form TDC is difficult to satisfy the requirement of combination property.In order to reduce quantization error, to improve conversion accuracy, must improve temporal resolution, but the raising of temporal resolution has significantly restricted the expansion of time measurement range again.The elementary tactics that solves this contradiction is to adopt two-part or multiple step format TDC structure.
The high bit flipping of straight binary counter need rely on the carry signal of low level, and namely the height bit flipping has a time difference.This situation may make the mistake latching moment, is not suitable for the higher applications of resolution requirement.
Summary of the invention
Technical problem to be solved by this invention provides a kind of two-part time-to-digital conversion circuit, and this circuit structure is simple, and the operating frequency height can utilize lower clock frequency to reach the precision of one-part form high frequency clock counter, realizes higher temporal resolution.
Another technical problem that the present invention will solve is: two-part time-to-digital conversion circuit of the present invention is used for array type infrared sensor output circuit.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of two-part time-to-digital conversion circuit comprises first counter and second counter, and wherein said first counter comprises n level delay cell, decoding circuit, latch; Described second counter adopts the pseudo noise code counter structure, wherein, through n level delay cell after export to second counter, to the output signal of delay cell handle successively by described second counter for external input signal, and the signal after will handling then is input to latch; N level delay cell produces 2 simultaneously
nIndividual phase state outputs to decoding circuit, and described decoding circuit is with 2
nIndividual phase state is decoded into binary code and is input to latch; In latch, the signal that described binary code and described second counter are input to latch merges, and latch control by outside stop pulse signal, and the signal after latching is as the output signal of described two-part time-to-digital conversion circuit, and wherein n is the natural number greater than 0.
Described delay cell adopts the mode of ring delay line, the inner clock that produces.
Described pseudo noise code counter structure is connected by trigger and logic gates and constitutes feedback loop.
Described first counter and second counter adopt gate controlled switch control.
The application of a kind of two-part time-to-digital conversion circuit in the array infrared sensor output circuit, with described two-part time-to-digital conversion circuit be disposed at that the pixel of array infrared sensor output circuit is outer, in the pixel or part place outside the pixel.
The present invention adopts above technical scheme, and compared with prior art, the technique effect that has is:
(1) two-part time-to-digital conversion circuit of the present invention comprises first counter portion and second counter portion, wherein first counter portion adopts the mode of ring delay line, ring delay line is used for phase-detection, its closed-loop structure allows delay line to reuse, when improving precision, also can satisfy the measurement requirement of wide range.
(2) two-part time-to-digital conversion circuit of the present invention is controlled by gate controlled switch, can open at any time, regularly turn-off, the operating time of counter is very short in the infrared sensing reading circuit, account for 5% of the whole system work period, can save power consumption greatly, first counter portion cooperates with second counter portion, finishing total time figure jointly transforms, reduce the pressure of high speed circuit design under power consumption and the process technology limit, satisfied the demand of many-sided balance compromises such as speed, precision, area and power consumption.
(3) operating frequency that ring shakes under the time-to-digital conversion circuit representative condition of the present invention only is 160MHZ, chip power-consumption 4mW, temporal resolution satisfies the application demand that circuit area is little, low in energy consumption, temporal resolution is high in the array type infrared sensing reading circuit less than 1ns.
Description of drawings
Fig. 1 is two-part time figure conversion circuit block diagram.
Fig. 2 is two-part time figure conversion circuit structure chart.
Fig. 3 is two-part time figure conversion circuit figure.
Fig. 4 is two-part time figure conversion circuit delay cell.
Fig. 5 is four state waveforms of the thin counter portion delay line of two-part time figure conversion circuit analogous diagram.
Fig. 6 is the low three digit wave form analogous diagram of the thin counter portion decoding of two-part time figure conversion circuit output.
Fig. 7 is the wave simulation figure of high ten in the thick segment count pseudo noise code of two-part time figure conversion circuit counter.
Fig. 8 places the outer schematic diagram of infrared output pixel for two-part numeral conversion circuit of the present invention.
Embodiment
The present invention will be further described below in conjunction with the drawings and the specific embodiments.
Fig. 1 is entire block diagram, and circuit input signal is gate-control signal EN, stop pulse signal STOP, reset signal Reset, and output signal is: Q1, Q2 ... Qi, wherein i is the output signal number.Circuit working when gate-control signal EN is high level, circuit quits work during for low level.Stop pulse signal STOP rising edge is effective.When stop pulse signal STOP was effective, TDC stopped timing, result's output that circuit will be counted.
Fig. 2 is circuit overall structure figure, circuit mainly is made of thin counter portion (first counter portion) and coarse counter part (second counter portion), thin counter portion comprises delay cell, decoding circuit, buffer stage, latch, delay cell adopts the mode of ring delay line, by forming more than 2 inverter, logic control circuit provides control signal EN for delay cell, inhibit signal is entered by the first order of delay cell, feeds back to the first order from afterbody output and forms the delay loop; Coarse counter adopts the pseudo noise code counter structure, in counting process, need clock signal control counting, ring delay line itself is a kind of ring oscillator structure, certain frequency of oscillation is arranged, can innerly produce clock, output simultaneously can be used for needn't re-using external clock for coarse counter provides clock signal; Output to latch after the thin counter portion output signal process coarse counter section processes, each of delay cell grade output outputs to latch after entering decoding circuit decoding through buffer stage, latchs control with the signal merging back of coarse counter output by stop pulse signal STOP.
Comprising the level Four time-delay with delay cell is that example explanation entire circuit constitutes: as shown in Figure 3, has the multiplexed selector 1 of inverter functionality as the delay cell first order, homophase device 2 as delay cell second and third, level Four, logic control circuit provides control signal EN for multiplexed selector 1, after inhibit signal enters by the delay cell first order, postpone shaping through three grades of homophase devices 2 successively, output to coarse counter by afterbody then, wherein homophase device 2 can be made up of even number logical circuit 3 as shown in Figure 4, also can be made of other circuit.Two loops of input signal propagate experience are formed a ring and are shaken the cycle, are equivalent to through 8 grades of delay cells, and every grade of delay cell inherent delay time is 0.78ns, and then the ring cycle of shaking is 8 * 0.78=6.24ns, and the inverse that encircles the cycle of shaking is about 160MHZ for frequency.
Be the operation principle that example is carried out physical circuit design and explanation this programme with 13 bit sequences, wherein low three Q1, Q2, Q3 are exported by thin counter, and high ten Q4～Q13 are exported by coarse counter, and the sequence of figure place can make up according to actual needs.
Three grades of delays are same phase delay after the delay cell in the decoding circuit delay loop, and multiplexed selector 1 constitutes the anti-phase time-delay of the delay cell first order.The level Four output of delay cell constitutes 8 phase states, enters decoding circuit through after the buffer stage, and decoding can draw low three binary counting.According to decoding logic, when a signal imported the delay loop into, the node phase information of each delay cell output had corresponding truth table.According to the decoding truth table, the decoding expression formula that can obtain Q1, Q2 and Q3 is as follows:
In like manner:
Wherein a is delay cell first order output node, and b is delay cell second level output node, and c is delay cell third level output node, and d is delay cell fourth stage output node,
Consider three output delay of output signal consistency of thin counter, adopt identical decoding circuit, obtain low three decoding circuit as shown in Figure 3.Q1, Q2 are made up of with door two XOR gate and one, and Q3 adopts XOR gate and forms jointly with door, another termination low level of XOR gate one termination d GND wherein, output termination two inputs of XOR gate with, with another termination high level of door VDD.Three decoding circuit time-delays are identical, and data are exported simultaneously.
Thick counting, input path and the position of choose reasonable feedback loop according to the actual requirements.Present design is example with 10 bit pseudo noise code counter open loop structures: except the 8th grade, outside the first order trigger, other every grade trigger is that the Q termination of previous stage is gone into D end at the corresponding levels.First order trigger D end is that the Q with the 10th grade trigger inserts, the 8th grade of trigger D end be the 7th grade and the 10th grade the Q end by with or access more behind the door.All clock end C connect the Q3 end of thin counting, and coarse counter resets by the input of reset signal Reset end with thin counter.
The emulation of the delay line input of thin counter portion is controlled about 0.78ns as shown in Figure 5 the time of delay of each delay cell, and the ring vibration frequency is about 160MHZ, and the time-delay of 4 delay cells is evenly distributed, and duty ratio is controlled about 50%.Fig. 6 is the decoding output waveform, by decoding circuit the waveform transformation among Fig. 5 is exported low three binary code for Fig. 6, and Q1 is lowest order, and frequency is about 640MHZ; Q2 is meta, and frequency is about 320MHZ; Q3 is highest order, and frequency is about 160MHZ.The emulation of thick segment count output as shown in Figure 7, Q4 is lowest order, slightly counts first order output waveform figure, and Q5 ~ Q13 is the oscillogram of a clock cycle output of previous stage output delay, Q13 is highest order, and output signal can be deciphered outside sheet and read corresponding 10 system numbers.
Another object of the present invention is that two-part time-to-digital conversion circuit TDC of the present invention is used for the infrared three-dimensional imaging reading circuit of array type, can as required circuit be disposed at outside the pixel, place outside the pixel in the pixel or partly; Whole two-part time-to-digital conversion circuit TDC can be configured in outside the pixel in order to save elemental area; Also the thin segment count of two-part time-to-digital conversion circuit TDC can be configured in pixel and outward thick segment count be configured in the pixel in order to take into account elemental area and system accuracy; Can consider whole two-part time-to-digital conversion circuit TDC is configured in pixel inside under the situation relatively fully at elemental area.As shown in Figure 8, two-part time-to-digital conversion circuit TDC is outside cell array, its counting output is connected in each pixel, when the whole system laser signal is found, two-part time-to-digital conversion circuit TDC counts, and when light signal returned, the transducer in the pixel can receive signal, can produce stop signal STOP, then pixel can be preserved the counting of current two-part time-to-digital conversion circuit TDC get off.Zero-time concerning each pixel is identical, stop signal STOP asynchronism(-nization), and then gate time can be variant, time difference converted to the purpose that distance difference just can reach imaging again.
The operating frequency that ring shakes under the circuit representative condition only is 160MHZ, chip power-consumption 4mW, and temporal resolution satisfies the application demand that circuit area is little, low in energy consumption, temporal resolution is high in the array type infrared sensing reading circuit less than 1ns.
Claims (5)
1. two-part time-to-digital conversion circuit, it is characterized in that: comprise first counter and second counter, wherein said first counter comprises n level delay cell, decoding circuit, latch; Described second counter adopts the pseudo noise code counter structure, wherein, through n level delay cell after export second counter, to the output signal of delay cell handle successively by described second counter for external input signal, and the signal after will handling then is input to latch; N level delay cell produces 2 simultaneously
nIndividual phase state outputs to decoding circuit, and described decoding circuit is with 2
nIndividual phase state is decoded into binary code and is input to latch; In latch, the signal that described binary code and described second counter are input to latch merges, and the signal after being combined by outside stop pulse signal latchs control, signal after latching is as the output signal of described two-part time-to-digital conversion circuit, and wherein n is the natural number greater than 0.
2. a kind of two-part time-to-digital conversion circuit according to claim 1 is characterized in that: the mode of described delay cell employing ring delay line, the inner clock that produces.
3. a kind of two-part time-to-digital conversion circuit according to claim 1, it is characterized in that: described pseudo noise code counter structure is connected by trigger and logic gates and constitutes feedback loop.
4. according to claim 1,2 or 3 described a kind of two-part time-to-digital conversion circuits, it is characterized in that: described first counter and second counter adopt gate controlled switch control.
5. the application of the arbitrary described two-part time-to-digital conversion circuit of claim 1-3 in the array infrared sensor output circuit is characterized in that: with described two-part time-to-digital conversion circuit be disposed at that the pixel of array infrared sensor output circuit is outer, in the pixel or part place outside the pixel.
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| CN104300970A (en) * | 2014-09-28 | 2015-01-21 | 东南大学 | Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL |
| CN104333365A (en) * | 2014-10-11 | 2015-02-04 | 东南大学 | Three-segment time digital converter (TDC) circuit |
| CN104614976A (en) * | 2015-02-12 | 2015-05-13 | 中国科学技术大学 | FPGA (field programmable gate array) based time-digital converter |
| CN104935345A (en) * | 2014-03-18 | 2015-09-23 | 台湾积体电路制造股份有限公司 | System and method for a time-to-digital converter |
| CN105353600A (en) * | 2015-10-14 | 2016-02-24 | 东南大学 | High-accuracy low-power three-segment type TDC circuit used for array system |
| CN106354001A (en) * | 2016-08-31 | 2017-01-25 | 中国科学院上海高等研究院 | Time-to-digital conversion circuit |
| CN106444345A (en) * | 2016-12-19 | 2017-02-22 | 深圳大学 | Time measurement circuit and method and measuring equipment |
| CN106681126A (en) * | 2016-12-09 | 2017-05-17 | 深圳市锐能微科技股份有限公司 | Time-digital converter and error calibration device and method thereof |
| CN107643674A (en) * | 2016-07-20 | 2018-01-30 | 南京理工大学 | A kind of Vernier type TDC circuits based on FPGA carry chains |
| CN107944073A (en) * | 2017-10-12 | 2018-04-20 | 北京时代民芯科技有限公司 | A kind of ring for multichannel time measurement shakes integrated circuit |
| CN109283832A (en) * | 2018-09-14 | 2019-01-29 | 东北大学 | A kind of time-to-digit converter of low-power consumption and its PHV compensation method |
| CN110062915A (en) * | 2016-12-02 | 2019-07-26 | 高通股份有限公司 | Using the ring based on latch when it is m- number conversion |
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| CN114935886A (en) * | 2022-04-21 | 2022-08-23 | 中国科学院上海微系统与信息技术研究所 | Two-section type superconducting time-to-digital converter and superconducting detector imaging system |
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| CN104935345A (en) * | 2014-03-18 | 2015-09-23 | 台湾积体电路制造股份有限公司 | System and method for a time-to-digital converter |
| CN104935345B (en) * | 2014-03-18 | 2018-08-07 | 台湾积体电路制造股份有限公司 | Time-to-digit converter system and method |
| CN104300970A (en) * | 2014-09-28 | 2015-01-21 | 东南大学 | Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL |
| CN104333365A (en) * | 2014-10-11 | 2015-02-04 | 东南大学 | Three-segment time digital converter (TDC) circuit |
| CN104333365B (en) * | 2014-10-11 | 2017-06-09 | 东南大学 | A kind of three-stage time-to-digital conversion circuit |
| CN104614976B (en) * | 2015-02-12 | 2017-03-29 | 中国科学技术大学 | A kind of time-digital converter based on FPGA |
| CN104614976A (en) * | 2015-02-12 | 2015-05-13 | 中国科学技术大学 | FPGA (field programmable gate array) based time-digital converter |
| CN105353600A (en) * | 2015-10-14 | 2016-02-24 | 东南大学 | High-accuracy low-power three-segment type TDC circuit used for array system |
| CN107643674A (en) * | 2016-07-20 | 2018-01-30 | 南京理工大学 | A kind of Vernier type TDC circuits based on FPGA carry chains |
| CN107643674B (en) * | 2016-07-20 | 2020-01-03 | 南京理工大学 | Vernier type TDC circuit based on FPGA carry chain |
| CN106354001A (en) * | 2016-08-31 | 2017-01-25 | 中国科学院上海高等研究院 | Time-to-digital conversion circuit |
| CN106354001B (en) * | 2016-08-31 | 2019-03-12 | 中国科学院上海高等研究院 | Time-to-digital conversion circuit |
| CN110062915B (en) * | 2016-12-02 | 2020-05-29 | 高通股份有限公司 | Integrated circuit and method of time-to-digital conversion using a latch-based ring |
| CN110062915A (en) * | 2016-12-02 | 2019-07-26 | 高通股份有限公司 | Using the ring based on latch when it is m- number conversion |
| CN106681126A (en) * | 2016-12-09 | 2017-05-17 | 深圳市锐能微科技股份有限公司 | Time-digital converter and error calibration device and method thereof |
| CN106681126B (en) * | 2016-12-09 | 2019-04-30 | 深圳市锐能微科技股份有限公司 | A kind of time-to-digit converter and its apparatus and method that calibrate for error |
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| CN106444345A (en) * | 2016-12-19 | 2017-02-22 | 深圳大学 | Time measurement circuit and method and measuring equipment |
| CN107944073A (en) * | 2017-10-12 | 2018-04-20 | 北京时代民芯科技有限公司 | A kind of ring for multichannel time measurement shakes integrated circuit |
| CN107944073B (en) * | 2017-10-12 | 2021-01-08 | 北京时代民芯科技有限公司 | Ring oscillation integrated circuit for multi-channel time measurement |
| CN110244315A (en) * | 2018-03-08 | 2019-09-17 | Zf 腓德烈斯哈芬股份公司 | Method for receiving the reception device of optical signal and for receiving optical signal |
| CN110244315B (en) * | 2018-03-08 | 2024-05-31 | 微视公司 | Receiving device for receiving optical signals and method for receiving optical signals |
| CN111742493A (en) * | 2018-03-09 | 2020-10-02 | 德克萨斯仪器股份有限公司 | Swing reduction for integer mode digital phase locked loop |
| CN109283832A (en) * | 2018-09-14 | 2019-01-29 | 东北大学 | A kind of time-to-digit converter of low-power consumption and its PHV compensation method |
| CN112165314A (en) * | 2020-09-25 | 2021-01-01 | 杭州加速科技有限公司 | Frequency-adjustable clock generation unit in FPGA chip |
| CN112202425A (en) * | 2020-09-25 | 2021-01-08 | 杭州加速科技有限公司 | Clock generation unit in FPGA chip |
| CN112578661A (en) * | 2020-12-11 | 2021-03-30 | 天津大学 | Delay line calibration circuit for FPGA type time-to-digital converter |
| CN114935886A (en) * | 2022-04-21 | 2022-08-23 | 中国科学院上海微系统与信息技术研究所 | Two-section type superconducting time-to-digital converter and superconducting detector imaging system |
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Application publication date: 20130717 |