CN102882527A - Time-to-digital converter and time-to-digital conversion method - Google Patents
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Abstract
The invention discloses a time-to-digital converter, comprising a measurement control circuit unit, a fine counting interface unit, a fine counting unit, a rough counting unit, a calibration unit, an internal register unit and a post-processing unit, wherein the fine counting unit comprises an annular time delaying chain, a double-edge counter, a fine counting latch and a priority encoder; the annular time delaying chain comprises a group of AND logic gates at the uppermost part of the left side of a chip and at least eight groups of NOR logic gates at the other positions; and all the logic gates are placed in a square shape and are connected end to end. The invention further discloses a time-to-digital conversion method; and a technology of combining fine counting based on gate time delaying and fine counting based on a clock is adopted so that a time interval between a starting pulse signal and a stopping pulse signal is accurately measured, the performance requirements of high precision and large measuring range can be met, and the time-to-digital converter has small occupied space and small deviation.
Description
Technical field
The present invention relates to a kind of time accurate measuring technique field, relate in particular to a kind of time-to-digit converter, the invention still further relates to a kind of method of time figure conversion.
Background technology
In many practical implementations, for speed, the measurement of distance often is converted into measurement of time, the precision of Measuring Time directly affects the precision of engineering survey, now more and more higher to various measuring instrument required precisions, some modern high New measuring techniques such as Supersonic are used more and more extensive, the time difference of ultrasonic wave co-current flow and counter-current flow is very small, so that the required precision of Measuring Time is more and more higher, therefore high-precision time interval measurement occupies very important status in actual measurement of engineering, the time figure conversion is the common circuit of time measurement, time-to-digital conversion circuit TDC commonly used is the analog to digital hybrid circuit mostly at present, analog circuit is operated in the impact that environment under low pressure lower time easily is subjected to ambient noise and dynamic temperature, causes job insecurity.The realization technology of time-to-digital conversion circuit TDC has at present: time amplifying technique, counter technology, vernier caliper technology, current integration technology, temporal interpolation technology, simple use any one technology recited above all is difficult to satisfy simultaneously the performance requirement of high accuracy, wide range.
Summary of the invention
First technical problem to be solved by this invention is: for the deficiency of prior art existence, a kind of time-to-digit converter is provided, this time-to-digit converter can satisfy the performance requirement of high accuracy, wide range simultaneously, is fit to some precision, the demanding device of range and occasion are used.
Second technical problem to be solved by this invention is: the deficiency for prior art exists provides a kind of time figure conversion method that can realize high accuracy, wide range time measurement.
For solving above-mentioned first technical problem, technical scheme of the present invention is:
A kind of time-to-digit converter comprises:
The circuit of measurement and control unit is used for providing control signal to other modular circuit of described time-to-digit converter the conversion of realization state;
Meticulous counting interface unit is used for receiving the pulse signal that described circuit of measurement and control is sent, and with institute
State pulse signal extend to rising edge clock arrive after and start meticulous counting unit and begin counting, described pulse signal comprises beginning pulse signal and stop pulse signal, and the time interval between described beginning pulse signal and the stop pulse signal is by being surveyed the time interval;
Described meticulous counting unit comprises annular time delay chain, bilateral along counter, meticulous Puzzle lock storage and priority encoder; Described annular time delay chain comprises a group of being positioned at the top, the chip left side and gate and is positioned at least eight group NOT logic doors of other position, and described these gates are put by hollow and be end to end; Described bilateral along counter, be used for measuring described pulse signal and export as the high position of meticulous count value in the circulation number of turns of described annular time delay chain; Described meticulous Puzzle lock storage is used for locking described pulse signal in position that described annular time delay chain delays to reach; Described priority encoder is for the output signal of described meticulous Puzzle lock storage being encoded and exporting as the low level of meticulous count value;
Thick counting unit is used for the First Astronautic Research Institute for Measurement and Test and surveys the quantity of the rising edge clock in the time interval also as thick count value output;
Alignment unit is used for described meticulous counting unit is calibrated, and obtains the calibration data of an internal reference reference clock;
The internal register unit, the operation result data that are used for storing count results data, calibration initial data and the post-processing unit of described thick counting unit and meticulous counting unit;
Described post-processing unit is used for the data of described internal register unit are carried out computing: T=T according to following formula
Clk(Nc+ (Nf1-Nf2)/Nj), and deposit the result of described computing in described internal register unit, wherein
T is surveyed the time interval by described, T
ClkBe the clock cycle, Nc is the thick count value between described beginning pulse signal and the stop pulse signal, Nf1 is that described beginning pulse signal rising edge is to the meticulous count value between first rising edge clock that arrives subsequently, Nf2 is that described stop pulse signal rising edge arrives the meticulous count value between first rising edge clock that arrives subsequently, and Nj is the calibration data of a described internal reference reference clock.
As a preferred implementation, described meticulous counting interface comprise one or, NAND gate, one and door, T trigger, the first d type flip flop, the second d type flip flop and a 3d flip-flop; Described the first d type flip flop, the second d type flip flop and 3d flip-flop have respectively a CP end, a D end, a Q output, an Enable Pin and a CLR end; Described T trigger has an input, an input end of clock, an output; The Q output of described the first d type flip flop is connected with an input described or door; The Q output of described the second d type flip flop is connected with another input described or door; The D end of described 3d flip-flop is connected with output described or door, and the Q output of described 3d flip-flop is connected with an input of described NAND gate; Output described or door is connected with another input of described NAND gate; The output of described NAND gate is connected with a described input with door; The described end with the CLR of described the first d type flip flop, the second d type flip flop and 3d flip-flop respectively with the output of door is connected, and the input of described T trigger is connected with the output of described NAND gate.
As a kind of improvement, the output of described meticulous counting unit is provided with the first register group that the trailing edge that is used for latching of series connection triggers and is used for isolating the second register group that metastable rising edge triggers.
For solving above-mentioned second technical problem, technical scheme of the present invention is:
A kind of time figure conversion method may further comprise the steps:
(1) sends beginning pulse signal and stop pulse signal by described circuit of measurement and control unit;
(2) when described meticulous counting interface unit is received described beginning pulse signal, described meticulous counting unit to described beginning pulse signal rising edge and the quantity of the gate that described beginning pulse delay signal passes through in the interval between first rising edge clock signal subsequently count, obtain meticulous count results Nf1 and deposit in the internal register unit;
(3) when described meticulous counting interface unit receives the stop pulse signal, described meticulous counting unit to described stop pulse signal rising edge and the quantity of the gate that described stop pulse signal passes through in the interval between first rising edge clock signal subsequently count, obtain meticulous count results Nf2 and deposit in the internal register unit;
(4) described thick counting unit is counted the rising edge clock between described beginning pulse signal and the described stop pulse signal, obtains count results Nc and deposits in the internal register;
(5) described alignment unit is calibrated inner reference clock, obtains count results Nj and deposits in the internal register unit;
(6) calibrated after, described post-processing unit begins that (Nc+ (Nf1-Nf2)/Nj) carries out computing, and acquired results is exactly the time interval between described beginning pulse signal and the stop pulse signal according to formula T=Tclk.
After having adopted technique scheme, the invention has the beneficial effects as follows:
1, because this time-to-digit converter has adopted the technology that combines with thick counting unit based on clock based on the meticulous counting unit of gate delay, wherein, adopted the straight binary counting method based on the thick counting unit of clock, the consumption resource is few, and range ability is large; Meticulous counting unit based on gate delay is to utilize the transmission delay of not gate to come the quantization time interval, and this precision is accurate to the delay of single not gate, can realize the measurement of PS level; Thereby this time-to-digit converter can be realized high accuracy, the measurement in the wide range time interval.
2, because this time-to-digit converter is provided with meticulous counting interface, because beginning pulse signal, stop pulse signal may be most advanced and sophisticated pulses, meticulous counting interface can make signal pulse extend in rising edge clock arrives, prevent from beginning pulse signal, stop pulse signal sampling less than.
3, when designing annular time delay chain with the FPGA editing machine, the one group of gate in the top, the chip left side realizes and logic, the residue gate forms at least eight NOT logic, combinatorial logic unit is put according to hollow, the annular time delay chain end to end, owing to having adopted this structure, every group wire length is basic identical, and shorter, guaranteed the time-delay of interconnection line between the logical block about equally, reduce the line time-delay on whole logical block impact, reduce by the incomplete same deviation that causes of line, can guarantee simultaneously that each combinational logic time-delay is less, improve certainty of measurement; The employing of annular time delay chain can reduce the quantity of gate circuit in addition, and then reduces the time discrete that gate delay brings, and economizes on resources, saving chip area.
4, latch by the register group of the output of meticulous counting unit being inserted the trailing edge triggering, then send into the register group that rising edge triggers, this two-stage register group of inserting also plays the metastable effect of isolation except the data of catching dynamic latch.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples.
Fig. 1 is the structured flowchart of time-to-digit converter in the embodiment of the invention;
Fig. 2 is meticulous counting interface unit circuit among Fig. 1;
Fig. 3 is the structure chart of meticulous counting unit among Fig. 1;
Fig. 4 is the layout of the annular time delay chain of time-to-digit converter in the embodiment of the invention;
Fig. 5 is the measurement sequential chart of time-to-digit converter in the embodiment of the invention;
Fig. 6 is the state diagram of circuit of measurement and control unit among Fig. 1;
Wherein, 201. first d type flip flops; 202. the second d type flip flop; 203. the second d type flip flop; 204. or door; 205. with door; 206. NAND gate; 207.T trigger; 301. with the gate group; 302. NOT logic door group; 303. smart Puzzle lock storage; 304. bilateral along counter; 305. thick Puzzle lock storage; 306. priority encoder; 307. the first register group; 308. the second register group; 309. annular time delay chain.
Embodiment
By reference to the accompanying drawings, further set forth the present invention below.
As shown in Figure 1, a kind of time-to-digit converter, it comprises circuit of measurement and control unit, meticulous counting interface unit, thick counting unit, meticulous counting unit, alignment unit, internal register unit and post-processing unit.
As shown in Figure 2, meticulous counting interface unit comprise one or 204, one NAND gate 206, one with 205, T triggers 207 of door, the first d type flip flop 201, the second d type flip flop 202 and 3d flip-flop 203.
Described the first d type flip flop 201, the second d type flip flop 202 and 3d flip-flop 203 have respectively a CP end, a D end, a Q output, an Enable Pin and a CLR end; Described T trigger 207 has an input, an input end of clock, an output; The Q output of described the first d type flip flop 201 is connected with an input described or door; The Q output of described the second d type flip flop 202 is connected with another input described or door; The D end of described 3d flip-flop 203 is connected with output described or door, and the Q output of described 3d flip-flop 203 is connected with an input of described NAND gate; Output described or door 204 is connected with another input of described NAND gate 206; The output of described NAND gate 206 is connected with a described input with door 205; The described end with the CLR of described the first d type flip flop 201, the second d type flip flop 202 and 3d flip-flop 203 respectively with the output of door 205 is connected, and the input of described T trigger 207 is connected with the output of described NAND gate.
Among Fig. 2, the implication of each signal is as follows:
Start: the beginning pulse signal that circuit of measurement and control is sent, rising edge is effective;
Start-En: circuit of measurement and control is sent enables the commencing signal pulse, and high level is effective;
Stop: the stop pulse signal that measuring circuit is sent, rising edge is effective;
Clk: reference clock signal;
Start_u: connect meticulous counting unit, begin meticulous counting unit counting, high level is effective;
Stop_u: connect meticulous counting unit, latch meticulous counting unit counting, Low level effective;
Reset_n_c: bilateral in the meticulous counting unit that resets finished initialization along counter, and low level has
Effect;
Reset_n: the reset signal that circuit of measurement and control is sent;
Start_dff and stop_dff are respectively the pulse signals that can be caught by the clk clock of start and the two generation of stop, and pulse duration is no more than a clock cycle; When the reset_n signal was 0, three registers were output as 0, and this moment, start_u was 0, and meticulous counting unit is closed; When the reset_n signal is 1, the EN signal is 1 o'clock, the rising edge of register response start and stop and clk signal, when the rising edge of start or stop arrives, output start_u becomes 1, start_u=1, start meticulous counting unit, and be continued until the rising edge of clk, this moment, clk was that the trigger of clock reads in start_u, output becomes 1, become 0 with reset_n_c after the start_u NOT-AND operation, make three register CLR, then start_u becomes 0, start_u=0, for new once counting ready; As long as start or stop be without effective edge, then clk is that the register output of clock is always 0; Stop_u directly links to each other with clk, and when counting down to the rising edge of clk, stop_u=1 latchs meticulous count results.Because of the start_u signal be at the clk rising edge by CLR, so it always satisfy settling time so that 1 clock cycle is kept in the start_dff pulse; When start or stop put 1, output start_u signal be high level before the clk rising edge arrives always, exported stop_u signal and clock signal synchronization.
As shown in Figure 3, meticulous counting unit comprises annular time delay chain 309, bilateral along counter 304 and thick Puzzle lock storage 305, meticulous Puzzle lock storage 303 and priority encoder 306; Described annular time delay chain comprises a group of being positioned at the top, the chip left side and gate group 301 and is positioned at 15 groups of NOT logic door groups 302 of other position, and described these gates are put by hollow and be end to end; Described bilateral along counter 304, be used for measuring described pulse signal and export as the high position of meticulous count value in the circulation number of turns of described annular time delay chain; Described meticulous Puzzle lock storage 303 is used for locking described pulse signal in position that described annular time delay chain delays to reach; Described priority encoder 306, be used for the output signal of described meticulous Puzzle lock storage 303 is encoded and as the low level output of meticulous count value, the output of meticulous counting unit is provided with the first register group 307 that the trailing edge that is used for latching of series connection triggers and is used for isolating the second register group 308 that metastable rising edge triggers.
As shown in Figure 4, the annular time delay chain is with the put manual arrangement of FPGA editing machine to logical block, one group of gate of the top, the chip left side realizes and logic, remain 15 groups of gates and form 15 NOT logic, 16 combinational logics are put by hollow, the ending of time delay chain is joined, and annular time delay chain is used for the meticulous counting of counting unit; Bilateral along counter, be used for metering beginning pulse signal in the number of turns of annular time delay chain circulating propagation, as the high position output of counter; Latch and XOR unit are used for the position that the lock-in detection inhibit signal arrives; Priority encoder is used for the output signal of XOR gate is encoded, and determines the position that the tested time arrives by the coding of output, as the low level output of tale.Certainly, as required, alogical quantity can be done corresponding variation, for example can be more than eight or eight.
As shown in Figure 5, when beginning pulse signal or stop pulse signal rising edge are effective, start meticulous counting unit, begin meticulous counting; When the clock rising edge is effective, latch data, and require the meticulous counting unit of initialization after after a while, make it to respond next beginning pulse signal and stop pulse, perhaps other start the signal of meticulous counting unit, between twice meticulous counting, thick counting unit is write down the periodicity of clock, alignment unit is calibrated inner reference clock, and post-processing unit is used for the data of described internal register unit are carried out computing: T=T according to following formula
Clk(Nc+ (Nf1-Nf2)/Nj), and deposit the result of described computing in described internal register unit, wherein
T is surveyed the time interval by described, T
ClkBe the clock cycle, Nc is the thick count value between described beginning pulse signal and the stop pulse signal, Nf1 is that described beginning pulse signal rising edge is to the meticulous count value between first rising edge clock that arrives subsequently, Nf2 is that described stop pulse signal rising edge arrives the meticulous count value between first rising edge clock that arrives subsequently, and Nj is the calibration data of a described internal reference reference clock.
As shown in Figure 6, the circuit of measurement and control unit comprises the programmable logic cells based on FPGA; Circuit of measurement and control is used for providing control signal for other modules circuit, control the work of whole circuit, when initializing signal Init was effective, system entered init state, when controller received the signal of start_dff=1, controller was started working by init state; Meticulous counting unit is controlled its input, output by meticulous counting interface; When Init was effective, NextState still was S_idle; When Init is invalid, and controller input start_dff is when effective, is used for calculating the number of times cnt that start_dff arrives and automatically adds 1, state enters the S-_1_0 state by S_idle, at this moment, start thick counting unit and begin counting, write enable signal effective, deposit the output of meticulous counting unit in register, come temporarily at next clock, enter the S_1_1 state, write enable invalid, register address adds 1, judges then whether cnt equals controller input set point; If unequal, enter the S_2_0 state, repeat above operation.If equate, enter the S_j_0 state and calibrate, coarse counter stops counting, controller is put output s_c=1, starts meticulous counting unit and begins to the reference clock counting, on next clock edge, enter the S_j_1 state, put equally output s_c=1, meticulous counting unit is still at counting; On next clock edge, enter the S_j_2 state, at this moment, meticulous counting unit stops counting, write and enable effectively, to deposit in the register with the reference clock cycle count value that meticulous counting unit records, come to enter the S_j_3 state at next clock temporarily, register address adds 1, write and enable effectively will deposit register in two clock cycle count values that meticulous counting unit records continuously, start post-processing unit and begin to calculate the data of depositing in the internal register; Then enter the S_idle state, wait for again being initialised.
In fact, the above embodiment of the present invention has also disclosed a kind of time figure conversion method, and this method can be generalized into following steps:
(1) sends beginning pulse signal and stop pulse signal by described circuit of measurement and control unit;
(2) when described meticulous counting interface unit is received described beginning pulse signal, described meticulous counting unit to described beginning pulse signal rising edge and the quantity of the gate that described beginning pulse delay signal passes through in the interval between first rising edge clock signal subsequently count, obtain meticulous count results Nf1 and deposit in the internal register unit;
(3) when described meticulous counting interface unit receives the stop pulse signal, described meticulous counting unit to described stop pulse signal rising edge and the quantity of the gate that described stop pulse signal passes through in the interval between first rising edge clock signal subsequently count, obtain meticulous count results Nf2 and deposit in the internal register unit;
(4) described thick counting unit is counted the rising edge clock between described beginning pulse signal and the described stop pulse signal, obtains count results Nc and deposits in the internal register unit;
(5) described alignment unit is calibrated inner reference clock, obtains count results Nj and deposits in the internal register unit;
(6) calibrated after, described post-processing unit begins that (Nc+ (Nf1-Nf2)/Nj) carries out computing, and acquired results is exactly the time interval between described beginning pulse signal and the stop pulse signal according to formula T=Tclk.
The present invention is not limited to above-mentioned embodiment, and all are based on technical conceive of the present invention, and the technical improvement of having done all falls among protection scope of the present invention.
Claims (7)
1. a time-to-digit converter is characterized in that, comprising:
The circuit of measurement and control unit is used for providing control signal to other modular circuit of described time-to-digit converter the conversion of realization state;
Meticulous counting interface unit, be used for receiving the pulse signal that described circuit of measurement and control is sent, and with described pulse signal extend to rising edge clock arrive after and start meticulous counting unit and begin counting, described pulse signal comprises beginning pulse signal and stop pulse signal, and the time interval between described beginning pulse signal and the stop pulse signal is by being surveyed the time interval;
Described meticulous counting unit comprises annular time delay chain, bilateral along counter, meticulous Puzzle lock storage and priority encoder; Described annular time delay chain comprises a group of being positioned at the top, the chip left side and gate and is positioned at least eight group NOT logic doors of other position, and described these gates are put by hollow and be end to end; Described bilateral along counter, be used for measuring described pulse signal and export as the high position of meticulous count value in the circulation number of turns of described annular time delay chain; Described meticulous Puzzle lock storage is used for locking described pulse signal in position that described annular time delay chain delays to reach; Described priority encoder is for the output signal of described meticulous Puzzle lock storage being encoded and exporting as the low level of meticulous count value;
Thick counting unit is used for the First Astronautic Research Institute for Measurement and Test and surveys the quantity of the rising edge clock in the time interval also as thick count value output;
Alignment unit is used for described meticulous counting unit is calibrated, and obtains the calibration data of an internal reference reference clock;
The internal register unit, the operation result data that are used for storing count results data, calibration initial data and the post-processing unit of described thick counting unit and meticulous counting unit;
Described post-processing unit is used for the data of described internal register unit are carried out computing: T=T according to following formula
Clk(Nc+ (Nf1-Nf2)/Nj), and deposit the result of described computing in described internal register unit, wherein
T is surveyed the time interval by described, T
ClkBe the clock cycle, Nc is the thick count value between described beginning pulse signal and the stop pulse signal, Nf1 is that described beginning pulse signal rising edge is to the meticulous count value between first rising edge clock that arrives subsequently, Nf2 is that described stop pulse signal rising edge arrives the meticulous count value between first rising edge clock that arrives subsequently, and Nj is the calibration data of a described internal reference reference clock.
2. time-to-digit converter as claimed in claim 1 is characterized in that: five groups of described NOT logic Men Weishi.
3. time-to-digit converter as claimed in claim 1 is characterized in that: described meticulous counting interface comprise one or, NAND gate, one and door, T trigger, the first d type flip flop, the second d type flip flop and a 3d flip-flop;
Described the first d type flip flop, the second d type flip flop and 3d flip-flop have respectively a CP end, a D end, a Q output, an Enable Pin and a CLR end; Described T trigger has an input, an input end of clock, an output; The Q output of described the first d type flip flop is connected with an input described or door; The Q output of described the second d type flip flop is connected with another input described or door; The D end of described 3d flip-flop is connected with output described or door, and the Q output of described 3d flip-flop is connected with an input of described NAND gate;
Output described or door is connected with another input of described NAND gate;
The output of described NAND gate is connected with a described input with door;
The described end with the CLR of described the first d type flip flop, the second d type flip flop and 3d flip-flop respectively with the output of door is connected;
The input of described T trigger is connected with the output of described NAND gate.
4. time-to-digit converter as claimed in claim 1 is characterized in that, described circuit of measurement and control unit comprises the programmable logic cells based on FPGA.
5. time-to-digit converter as claimed in claim 1 is characterized in that: the output of described meticulous counting unit is provided with the first register group that the trailing edge that is used for latching of series connection triggers and is used for isolating the second register group that metastable rising edge triggers.
6. time-to-digit converter as claimed in claim 1, it is characterized in that: describedly bilaterally comprise odd number counter that rising edge triggers, even number counter that trailing edge triggers and with the data selector of clock as the gating control signal along counter, described odd number counter and even number counter are in parallel, and the output of described odd number counter and even number counter is connected to described data selector.
7. a method that realizes the time figure conversion with time-to-digit converter claimed in claim 1 is characterized in that, may further comprise the steps:
(1) sends beginning pulse signal and stop pulse signal by described circuit of measurement and control unit;
(2) when described meticulous counting interface unit is received described beginning pulse signal, described meticulous counting unit to described beginning pulse signal rising edge and the quantity of the gate that described beginning pulse delay signal passes through in the interval between first rising edge clock signal subsequently count, obtain meticulous count results Nf1 and deposit in the internal register unit;
(3) when described meticulous counting interface unit receives the stop pulse signal, described meticulous counting unit to described stop pulse signal rising edge and the quantity of the gate that described stop pulse signal passes through in the interval between first rising edge clock signal subsequently count, obtain meticulous count results Nf2 and deposit in the internal register unit;
(4) described thick counting unit is counted the rising edge clock between described beginning pulse signal and the described stop pulse signal, obtains count results Nc and deposits in the internal register unit;
(5) described alignment unit is calibrated inner reference clock, obtains count results Nj and deposits in the internal register unit;
(6) calibrated after, described post-processing unit begins that (Nc+ (Nf1-Nf2)/Nj) carries out computing, and acquired results is exactly the time interval between described beginning pulse signal and the stop pulse signal according to formula T=Tclk.
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| CN106527099B (en) * | 2016-12-09 | 2019-07-26 | 深圳市锐能微科技股份有限公司 | A kind of time-to-digit converter and its time measuring circuit and method |
| CN106886146A (en) * | 2017-01-06 | 2017-06-23 | 南京理工大学 | A kind of TOA estimating circuits based on digital delay circuit |
| CN106886146B (en) * | 2017-01-06 | 2019-08-30 | 南京理工大学 | A kind of TOA estimating circuit based on digital delay circuit |
| CN107037721A (en) * | 2017-06-16 | 2017-08-11 | 中国科学技术大学 | One kind reviews one's lessons by oneself eurymeric time-to-digit converter |
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| CN116844620A (en) * | 2022-03-23 | 2023-10-03 | 长鑫存储技术有限公司 | Signal sampling circuit and semiconductor memory |
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| CN116087628A (en) * | 2023-04-10 | 2023-05-09 | 国仪量子(合肥)技术有限公司 | Measurement method, device and storage medium |
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