CN104614976A - FPGA (field programmable gate array) based time-digital converter - Google Patents
FPGA (field programmable gate array) based time-digital converter Download PDFInfo
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Abstract
The invention discloses an FPGA (field programmable gate array) based time-digital converter comprising a pulse signal generator, a multi-tab signal delay chain, a trigger array, a connection network, a signal change edge searching and encoding circuit and a time stamp output circuit. The pulse signal generator is triggered by a measured signal to generate a falling edge and feeds the falling edge into a signal delay chain. The trigger array is controlled by a system clock to latch tap states of the signal delay chain and transmit the tap states to the connection network. The connection network resorts and extracts the latched taps according to distribution of delay width of delay units of the signal delay chain measured in advance and transmits the tap states to the signal change edge searching and encoding circuit. The FPGA based time-digital converter has the advantages that the influence of the 0 delay unit on the signal delay chain and nonlinear error can be maximally eliminated, bubbling in thermometer code under the tap state is decreased, and performance indexes, namely measuring precision, measuring dead time and resource usage, are reasonably balanced, and a high-performance TDC (time to digital) measuring system is achieved.
Description
Technical field
The invention belongs to the digitized measurement field of time quantum, be specifically related to a kind of time-digital converter based on FPGA.
Background technology
Time measurement refers to the moment that measurement event occurs, or measures the time interval between two events.Time measurement technology all has important application in a lot of fields, such as high-energy physics experiment research, nuclear medicine, military and civilian radar, and the field such as laser ranging all needs high-precision time measurement technology.Time-digital converter (TDC:Time-Digital-Convertor) is exactly that a kind of digital quantity that is converted into by time quantum is to realize the function element of the record of an event generation time.For the measurement in the time interval between two events, generally can be measured the generation moment of two events respectively by two TDC, the difference in two generation moment is exactly the time interval of these two events.At present, the realizing carrier and can be divided into based on ASIC (Application Specific IntegratedCircuit) special chip with based on FPGA (Field Programmable Gate Array) programming device two kinds of TDC.Along with the development of FPGA technology, the logical resource amount that monolithic FPGA can provide is increasing, and the dirigibility of its programmable configuration is also more and more stronger, and FPGA has become the platform of digital display circuit Integrated design.On this platform, such as, if the measurement of some physical quantitys can be realized, the measurement of time quantum simultaneously, significant to the data acquisition and processing system that the user based on FPGA is special undoubtedly.In recent years, TDC designing technique based on FPGA grows a lot, wherein most important a kind of approach utilizes the carry chain in FPGA basic logic resource to form multitap signal transmission delay chain (TDL:Tapped Delay Line), thus the interpolation realizing time quantum is to improve the measuring accuracy of TDC.
TDL type TDC based on FPGA has multiple possible specific implementation, and the TDC measuring accuracy that different schemes can realize is different with the measurement dead time, and the fpga logic stock number shared by single channel TDC is also different.The little measurement dead time can improve the measurement handling capacity of TDC, and few logical resource occupancy can save other parts of the data acquisition and processing system that FPGA resource designs for user, or can realize the hyperchannel TDC system on monolithic FPGA.But current TDC implementation can not improve measuring accuracy, reduce and measure the dead time and reduce the index all obtained in resource occupation amount these three.
For ease of understanding, first realize temporal interpolation to utilizing the carry chain logical resource of fpga chip to form many taps transmission delay chain (TDL:Tapped Delay Line), thus the principle improving TDC measuring accuracy is simply introduced.
The most simple realization method of the digitized measurement of event generation time can be realize with a high-frequency clock counter.When measured signal arrives, record the state of counter at that time, this state is exactly the time measured value of event generation time.The TDC precision of the method is exactly the cycle of counter clock signal.In order to obtain high measurement accuracy, very high clock frequency must be used.Maximum clock frequency at present based on FPGA is approximately 710MHz, and namely highest measurement precision is about 1.408ns.In order to improve the measuring accuracy of TDC, a kind of common method at present based on FPGA technology manages to construct a delay chain be unified into by multiple delay cell.The total delay time of this delay chain is greater than the cycle of a system clock, and the state of each delay cell is drawn by tap.Transmit in this delay chain of measured signal feed-in, record the state of clock counter and the state of delay chain in the arrival moment of each system clock simultaneously.The former is the thick time mark of measured signal, and the latter is the thin time mark of measured signal, is exactly the accurate results of measured signal by both combinations.Use this temporal interpolation technology, the measuring accuracy of TDC depends primarily on size and the precision of delay cell in delay chain.At present, be utilize carry chain in FPGA arithmetic logical operation resource to form delay chain mostly, the length of each delay cell is exactly the transmission delay amount of corresponding carry chain.The trigger that use and carry chain are in same resource units can be drawn the state of each for retardation tap, exports the coding of retardation state for subsequent conditioning circuit.For the situation in the time interval requiring measurement two events, can adopt two TDC passages, record the generation moment of two events respectively, difference is therebetween exactly the time interval.
The delay width of each delay cell has heterogeneity, and each measured node exists measuring error.Above-mentioned heterogeneity and measuring error can be represented respectively with differential nonlinearity and integral nonlinearity.Differential nonlinearity can be defined as the delay width of actual delay unit and the difference of ideal delay width, general with ideal delay width (1 LSB) for unit represents.Integral nonlinearity can be defined as the differential nonlinearity of all delay cells from first delay cell to place measured node and.Its represents the error between the reading value of place measured node and desirable measured value, generally also with ideal delay width (LSB) for unit represents.In TDC measures, correct by unit if do not used, integral nonlinearity is exactly the measuring error of each measured node, therefore will remove the needs by cell correcting circuit, must improve integral nonlinearity as far as possible.
Summary of the invention
While the present invention is intended to effectively to improve the measuring accuracy of TDC, reduces it and measure dead time and reduce the fpga logic stock number that single TDC passage will take.
For solving the problems of the technologies described above, the present invention proposes a kind of time-digital converter based on FPGA, comprise thick clock counter, pulse signal generator, signal delay chain, flip-flop array, interconnection network, signal intensity along finding and coding circuit, and timestamp output circuit, wherein, thick clock counter is driven by clock signal of system, for generation of the thick timestamp of measured signal; So described pulse signal generator transmits with producing a pulse with change edge and be fed in described signal delay chain under the triggering of measured signal; Described signal delay chain is used for carrying out delay transport to measured signal, and be made up of multiple delay cell, and have tap at the rear of each delay cell, first delay cell front also has tap; Described flip-flop array is used for latching each tap state of signal delay chain, and the tap state of latch is passed to described interconnection network according to the natural ordering of described tap; Described interconnection network is used for the tap state received to convert according to the annexation preset, then passes to described signal intensity along finding and coding circuit; Described signal intensity edge searching and coding circuit for finding the change edge of the pulse transmitted in described signal delay chain be latched, and generate according to the position on described change edge the binary code representing thin timestamp; Described timestamp output circuit is used for according to signal intensity along finding and being converted into the arrival timestamp of measured signal together with the thin timestamp of binary code of coding circuit output and the thick timestamp that exports of thick clock counter and being exported.
According to the specific embodiment of the present invention, the conversion that the tap state received is carried out according to the annexation preset comprises by described interconnection network: each tap of described signal delay chain reordered, and determines a kind of annexation described flip-flop array being connected to the searching of described signal intensity edge and coding circuit.
According to the specific embodiment of the present invention, described in reorder and comprise: the tap position of the tap of 0 width delay cell and next delay cell is exchanged.
According to the specific embodiment of the present invention, described reordering can repeatedly be carried out, the delay width of each delay cell is measured after once adjustment order, judge that whether the delay cell number of 0 width is more than a threshold value, if, then again reorder, until the number of 0 width delay cell is no more than described threshold value.
According to the specific embodiment of the present invention, the delay width of each delay cell of described measurement is the delay width adopting code density method to measure each delay cell.
According to the specific embodiment of the present invention, the conversion that the tap state received is carried out according to the annexation preset comprises by described interconnection network: extract each tap of described signal delay chain, determines a kind of annexation described flip-flop array being connected to the searching of described signal intensity edge and coding circuit.
According to the specific embodiment of the present invention, the rule of described extraction is: the integral nonlinearity that the temporal interpolation done based on described signal delay chain is measured is minimum.
According to the specific embodiment of the present invention, described extraction is: the total tap number after being extracted in first setting signal delay chain is R, then according to system clock cycle T
clockcalculate the ideal delay length w:w=T of the groups of delay cells formed after extracting
clock/ R T
clock, and complete extraction according to this ideal delay length w.
According to the specific embodiment of the present invention, extraction be the tap S meeting following formula
l, 1≤l≤n:
Wherein, if the delay width of original each delay cell is B
1, B
2, B
3..., B
n, n is the number of delay cell, and the output tap of each original delay cell is designated as S respectively
1, S
2, S
3..., S
n, the B used in above formula
0a dummy delay amount of adding to be above formula establishment, B
0=0, the tap after extraction is designated as T
1, T
2, T
3..., T
r, above formula, to each given i, all can calculate a minimum l, the tap S that this minimum l value is corresponding
lbe exactly the T after extracting
i.
According to the specific embodiment of the present invention, described signal intensity generates one along searching and coding circuit according to the tap state received from described interconnection network and represents the thermometer-code of change along position, generate for representing change " one-hot " code along position according to this thermometer-code, then the binary code that " one-hot " code conversion is expression timestamp will be somebody's turn to do.
According to the specific embodiment of the present invention, described signal intensity is along to find and described thermometer-code cutting is obtained 2 by the window of a movement by turn by coding circuit
nindividual window value, n=2
n, n is the number of delay cell, and the bit wide of described window is that m, m are natural number and 2≤m≤2
n, and obtain " one-hot " code corresponding with described thermometer-code by the true value corresponding to window value described in sequential.
According to the specific embodiment of the present invention, the truth table changed between all possible window value and corresponding true value is stored in the basic logic unit LUT in FPGA.
According to the specific embodiment of the present invention, when described signal intensity along find and coding circuit for finding the negative edge of thermometer-code time, in described truth table, only have last to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0; Or only have last to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1.
According to the specific embodiment of the present invention, described change along find and coding circuit for " one-hot " code represented with " 1 ", by calculating 2
n-1the logical "or" computing of individual " one-hot " code word obtains the coding of each of binary code; For " one-hot " code represented with " 0 ", by calculating 2
n-1the logic "and" operation of individual " one-hot " code word obtains the coding of each of binary code.
According to the specific embodiment of the present invention, described change realizes described logical "or" computing or logic "and" operation along the LUT found and coding circuit utilizes pipeline organization to combinationally use FPGA, the logical "or" computing that every one-level of streamline is one or several parallel dependence LUT and realizes or logic "and" operation.
In addition, the present invention also proposes the code conversion method of a kind of thermometer-code based on FPGA to binary code, and described thermometer-code has 2
nposition, described binary code has N position, and N is natural number, and described method comprises: by the window of a movement by turn, described thermometer-code cutting is obtained 2
nindividual window value, the bit wide of described window is that m, m are natural number and 2≤m≤2
n, and obtain " one-hot " code corresponding with described thermometer-code by the true value corresponding to window value described in sequential; Described " one-hot " code is converted to binary code.
According to the specific embodiment of the present invention, the truth table changed between all possible window value and corresponding true value is stored in the basic logic unit LUT in FPGA.
According to the specific embodiment of the present invention, when described signal intensity is along when finding circuit for finding the rising edge of thermometer-code, in described truth table, only have first to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0; Or only have first to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1; When described signal intensity is along when finding circuit for finding the negative edge of thermometer-code, in described truth table, only having last to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0; Or only have last to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1.
According to the specific embodiment of the present invention, at described " one-hot " code in the transfer process of binary code, for " one-hot " code represented with " 1 ", by calculating 2
n-1the logical "or" computing of individual " one-hot " code word obtains the coding of each of binary code; For " one-hot " code represented with " 0 ", by calculating 2
n-1the logic "and" operation of individual " one-hot " code word obtains the coding of each of binary code.
According to the specific embodiment of the present invention, the LUT utilizing pipeline organization to combinationally use FPGA realizes described logical "or" computing or logic "and" operation, the logical "or" computing that every one-level of streamline is one or several parallel dependence LUT and realizes or logic "and" operation.
The present invention also proposes the code conversion device of a kind of thermometer-code based on FPGA to binary code, and described thermometer-code has 2
nposition, described binary code has N position, and N is natural number, and described code conversion device comprises signal intensity along finding circuit with " one-hot " code to binary code change-over circuit, wherein, described thermometer-code cutting is obtained 2 along finding the window of circuit by a movement by turn by described signal intensity
nindividual window value, the bit wide of described window is that m, m are natural number and 2≤m≤2
n, and obtain " one-hot " code corresponding with described thermometer-code by the true value corresponding to window value described in sequential; Described " one-hot " code is used for described " one-hot " code to be converted to binary code to binary code change-over circuit.
According to the specific embodiment of the present invention, the conversion truth table between all possible window value and corresponding true value is stored in the LUT of fpga logic resource.
According to the specific embodiment of the present invention, when described signal intensity is along when finding circuit for finding the rising edge of thermometer-code, in described truth table, only have first to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0; Or only have first to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1; When described signal intensity is along when finding circuit for finding the negative edge of thermometer-code, in described truth table, only having last to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0; Or only have last to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1.
According to the specific embodiment of the present invention, described " one-hot " code to binary code change-over circuit for " one-hot " code represented with " 1 ", by calculating 2
n-1the logical "or" computing of individual " one-hot " code word obtains the coding of each of binary code; For " one-hot " code represented with " 0 ", by calculating 2
n-1the logic "and" operation of individual " one-hot " code word obtains the coding of each of binary code.
According to the specific embodiment of the present invention, the LUT utilizing pipeline organization to combinationally use FPGA realizes described logical "or" computing or logic "and" operation, the logical "or" computing that every one-level of streamline is one or several parallel dependence LUT and realizes or logic "and" operation.
TDC of the present invention can make measuring accuracy, measure the performance index of dead time and these three aspects of resource occupation amount reaches reasonable balance, thus can realize high performance TDC measuring system, has significant application value in the association area of time measurement.
Accompanying drawing explanation
Fig. 1 is TDC structural representation of the present invention;
The TDC overall system composition frame chart that Fig. 2 provides for one embodiment of the present of invention;
Fig. 3 a to put in order the delay cell width distribution figure obtained measured by lower use code density method naturally for delay chain tap that embodiment of the present invention provides;
Fig. 3 b is the differential nonlinearity figure obtained according to the delay cell width calculation of Fig. 3 a;
Fig. 3 c is the integral nonlinearity figure obtained according to the delay cell width calculation of Fig. 3 a;
The delay cell width distribution figure obtained measured by code density method is used after the delay chain tap status re-arrangement sequence that Fig. 4 provides for embodiment of the present invention;
The rear differential nonlinearity figure using the measurement of code density method to obtain of delay chain tap state extraction that Fig. 5 a provides for the embodiment of the present invention;
The integral nonlinearity figure that use code density method measurement after the delay chain tap state that Fig. 5 b provides for the embodiment of the present invention extracts obtains;
In the delay chain tap state former Nature Link output situation that Fig. 6 a provides for the embodiment of the present invention, the measurement histogram in the double T DC channel measurement 3.3ns time interval;
The delay chain tap state that Fig. 6 b provides for the embodiment of the present invention through the present invention convert export after annexation when, the measurement histogram in the double T DC channel measurement 3.3ns time interval;
The basic look-up table configuration schematic diagram of Kintex-7FPGA that Fig. 7 provides for embodiment of the present invention;
The use sliding window structure that Fig. 8 provides for embodiment of the present invention finds signal intensity along principle schematic;
Fig. 9 realizes 128 logical "or" operating structure schematic diagram for the use pipeline organization that embodiment of the present invention provides;
Figure 10 is the standard error graph of a relation that sum and the double T DC channel measurement 3.3ns time interval are extracted in embodiment tap of the present invention.
Embodiment
Fig. 1 is the structural representation of the time-digital converter based on FPGA provided by the invention.As shown in Figure 1, it comprises thick clock counter, pulse signal generator, signal delay chain, flip-flop array, interconnection network, the searching of signal intensity edge and coding circuit and timestamp output circuit.
Thick clock counter is driven by clock signal of system, and for generation of the thick timestamp of measured signal.
Pulse signal generator is external trigger, so it transmits with producing a pulse being fed in signal delay chain with change edge under the triggering of measured signal.Described change is along being chosen as rising edge or negative edge.
Signal delay chain is used for carrying out delay transport to measured signal, and it is made up of multiple delay cell, and has tap in the front end of each delay cell, and therefore signal delay chain is multitap signal delay chain.
Flip-flop array is used under the control of system clock, latches, and the tap state of this latch is passed to described interconnection network according to natural ordering to each tap state of signal delay chain.
Interconnection network, for the tap state of the latch received being converted according to the annexation preset, then passes to described signal intensity along finding and coding circuit;
The searching of signal intensity edge and coding circuit for finding the change edge of the pulse transmitted in signal delay chain be latched, and generate according to the position on described change edge the binary code representing thin timestamp.Usually, the tap state of signal delay chain is one and represents the thermometer-code of change along position, signal intensity generates for representing change " one-hot " code along position along searching and coding circuit according to this thermometer-code, to be somebody's turn to do " one-hot " code conversion is again the binary code representing timestamp, and this timestamp is a thin timestamp.
Thermometer-code shows as continuous several " 1 " (can be envisioned as the mercury slug of thermometer) and several " 0 " of residue composition, or on the contrary." one-hot " code then refer to except one of them, all identical coding in other position, such as ... 00001000 ..., or ... 111110111 ...The former also can be described as " one-hot " code represented by " 1 ", and the latter also can be described as " one-hot " code represented by " 0 ".
According to the present invention, the default annexation of described interconnection network is that tap state flip-flop array latched sends described signal intensity to along finding and coding circuit according to original natural ordering.Under default connection, the described time-digital converter based on FPGA can use the measurement of code density method to obtain the distribution results of each delay units delay width, on this basis, to each tap of signal delay chain respectively through reordering (tap realignment) and/or extracting (tap decimation), determine that a kind of tap stateful connection flip-flop array latched is to described signal intensity along the annexation found between coding circuit.Described interconnection network, according to this annexation, is flowed to described signal intensity along finding and coding circuit after the tap state transformation that flip-flop array is exported.
A kind of mode reordered is: exchanged by the tap position of the tap of 0 width delay cell and next unit.This sequencer procedure can repeatedly carry out, that is: after once adjustment order, measure the delay width of each delay cell, judge whether the delay cell that also there is 0 width, or whether the delay cell number of 0 width is no more than a threshold value, if, then again adjustment order, until the number of 0 width delay cell satisfies condition.Wherein, the retardation of each delay cell is measured by code density method.
Extracting (decimate) to the tap (tap) of delay cell is the heterogeneity (i.e. differential nonlinearity) of delay width in order to reduce each delay cell and the measuring error (i.e. integral nonlinearity) of each tap node.Described " extracting (tap decimation) " in the present invention refers to that the tap (output tap) to each delay cell is chosen, to make each delay cell to be divided into according to selected tap the groups of delay cells arranged in order.Described extraction and described reordering can be applied separately, also can be combined, but are more preferably and extract after reordering.
Described signal intensity along find and coding circuit reception be the tap state of groups of delay cells after reordering and/or extracting.The measuring error (i.e. integral nonlinearity) that " extraction " can make the temporal interpolation done based on this delay chain measure is minimum, improves the consistance (i.e. differential nonlinearity) postponed between groups of delay cells between width simultaneously.Thus, the present invention when not by by cell correcting circuit, can obtain higher measuring accuracy.
The process nature of described " extraction " is several continuous print delay cell is coupled together formation tap close to ideal delay cell width as far as possible, a kind of rule of extraction is that the integral nonlinearity making to measure in each tap node is minimum.For the signal delay chain of the number of given delay cell, although the tap sum that will extract generally all can be less than original tap sum, the tap sum occurring extracting also is allowed to be more than or equal to the situation of original tap number.
Unit between each tap after extraction can be regarded as reconfiguring of the delay cell of original continuous, therefore can be described as groups of delay cells.Because the tap sum after extracting can equal, be less than or greater than original tap number, therefore in groups of delay cells, the number of continuous print delay cell can be 1, also can be greater than 1, or 0.When the number of continuous print delay cell is 0, is equivalent to the extraction more than 1 time has been carried out for same tap and creates the dummy delay unit group that a delay width is 0.
As previously mentioned, one of decimation rule makes in the error (i.e. integral nonlinearity) of each measurement point minimum, and no matter whether this tap is pumped through above.When a tap is repeated to extract, will inevitably produce the delay cell of 0 width, such result remains the minimum needs of integral nonlinearity.Because the delay chain formed based on FPGA internal carry chain generally all has differential nonlinearity and the integral nonlinearity of non-constant, to the reading extracting the rear new delay chain state be made up of groups of delay cells formed, non-linear (integral nonlinearity and/or the differential nonlinearity) of final time measurement all can be made to be greatly improved.
A kind of embodiment extracted is that the total tap number after being extracted in first setting signal delay chain is R, then according to system clock cycle T
clockcalculate the ideal delay length w:w=T of the groups of delay cells formed after extracting
clock/ R, and complete extraction according to this ideal delay length w.
If the delay width of each delay cell is B
1, B
2, B
3..., B
n, n is the number of delay cell, and the output tap of each delay cell front end is designated as S respectively
1, S
2, S
3..., S
n, the tap of the groups of delay cells after extraction is designated as T
1, T
2, T
3..., T
r.For the tap T of the groups of delay cells after extraction
i, 1≤i≤R, then what it extracted is meet following formula minimum l value correspondence tap S
l, 1≤l≤n:
Wherein, B
0a dummy delay amount of adding to make above formula set up, B
0=0.
Interconnection network in FIG represents above-mentioned reordering and the way of realization of extraction process.In fact, also exist in the TDC structure that this interconnection network realizes at existing FPGA, only there uses sequenced annexation (i.e. above-mentioned default annexation).The present invention have passed through reordering of delay cell and extracts, utilization be the reconfigurable feature of FPGA, the annexation of interconnection network is changed accordingly.
For avoiding the interference of " bubbling " phenomenon, change of the present invention is preferably along searching and coding circuit and adopts sliding window method thermometer-code to be converted to " one-hot " code.The process obtaining " one-hot " code corresponding with thermometer-code is exactly find the process on signal intensity edge in fact.At this, we set the tap number of signal delay chain as n=2
n, then thermometer-code has 2
nposition, the binary code be converted to is N position, and N is natural number.
Specifically, first described thermometer-code cutting is obtained 2 by the window of a movement by turn by sliding window method of the present invention
nindividual window value, the bit wide of described window is that m, m are natural number and 2≤m≤2
n, and obtain " one-hot " code corresponding with described thermometer-code by the true value corresponding to window value described in sequential.
In addition, in order to eliminate the impact of " bubbling ", in this regulation, when described change along find and coding circuit for finding the negative edge of thermometer-code time, only have last to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0 (" one-hot " code for being represented by " 1 "); Or only have last to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1 (" one-hot " code for being represented by " 0 ").Conversion truth table between all possible window value and corresponding true value is stored in the LUT of fpga logic resource.
Described change along find and coding circuit for " one-hot " code represented with " 1 ", by calculating 2
n-1the logical "or" computing of individual " one-hot " code word obtains the coding of each of binary code; For " one-hot " code represented with " 0 ", by calculating 2
n-1the logic "and" operation of individual " one-hot " code word obtains the coding of each of binary code.When being realized by FPGA, the LUT that pipeline organization can be utilized to combinationally use FPGA realizes described logical "or" computing or logic "and" operation, the logical "or" computing that every one-level of streamline is one or several parallel dependence LUT and realizes or logic "and" operation.
Timestamp output circuit was used for according to signal intensity along the arrival time finding and be converted into together with the binary code of coding circuit output and the count signal that exports of thick clock counter measured signal.
Description below by the technical scheme to one embodiment of the present of invention make feature of the present invention and beneficial effect clearly, complete.Should understand, embodiment described herein is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 2 is the TDC overall system composition frame chart that one embodiment of the present of invention provide.It comprises a pulse signal generator, the TDL be made up of carry chain (Tapped Delay Line), flip-flop array, a signal intensity edge searching and a coding circuit and the coarse counter driven by system clock and timestamp output circuit.The fpga chip that the present embodiment uses is Kintex-7xc7k325t-2ffg900.
In the present embodiment, the system clock frequency of FPGA is 710MHz, and the cycle is 1.408ns.The total delay time length of the TDL be made up of carry chain is greater than the cycle of a system clock, and its total tap number is less than 200, and whole TDL can intactly utilizing the logical resource in a clock zone to realize.Do like this and can avoid due to TDL cross clock domain, occur larger delay cell at the boundary of two clock zones.Each measured signal arrives, and all the output signal of trigger generator can change to low level by high level, this signal transmits along TDL, and flip-flop array latches the state of TDL at the rising edge of next system clock.This state will be given signal and be found and coding circuit along change.The result of coding is exactly the position of signal intensity edge in TDL, namely thin timestamp.The output of described coarse counter is the thick timestamp of measured signal.Be exactly the time mark measured after surveying by the combination of thin timestamp and thick timestamp, exported by timestamp output circuit.
Retardation due to delay cell each in TDL is generally unequal, the clock signal networks of adding control trigger array the clock control end of each trigger exist Skew (namely due to clock network path-length not etc. reason cause the moment of the tap state of flip/flops latch simultaneously strict), not etc., even effective delay width of some unit is not 0 to the delay width (time delay) that can cause each showed delay cell.Can by measuring the delay width obtaining each delay cell.
Code density method is a kind of method being usually used in measuring each delay units delay amount size, it produces one in outside with the incoherent square-wave signal of system clock as external trigger signal, each rising edge of this signal can produce (the attention of a signal negative edge by trigger generator, in this embodiment, after the set time that negative edge produces, the output of pulse producer can revert to high level), carry out a time mark survey record.Because external trigger signal and systems clock signal is uncorrelated, the arrival moment of external trigger signal should be evenly distributed in the one-period of system clock.Thus the TDL state that latches of flip-flop array, the position of its negative edge should be distributed in one-period equiprobably.The example number (recording number of times) occurring in the negative edge of each delay cell conversely speaking, should be directly proportional with prolonging its slow cell width, accordingly, just can record the retardation width of each delay cell.
Fig. 3 a is primitive nature order (i.e. the order of connection of delay chain) of embodiment of the present invention according to delay chain, and utilize the delay cell width distribution figure that the measurement of code density method obtains, its transverse axis is tap sequence number, and the longitudinal axis postpones width.
Can find out from Fig. 3 a, the effective delay width having the quite delay cell of most is 0, and namely these unit always can not see the change edge of signal independently.The delay cell of 0 width is unfavorable to obtaining high temporal interpolation resolution, because the retardation of oneself has been added in other delay cell by it, cause unit retardation comparatively large, and effectively delay cell number reduces, temporal interpolation resolution reduces.On the other hand, the delay cell of zero width can produce " bubbling " in status switch thermometer-code.For negative edge, desirable status switch should be ... 11110000 ... but because the delay cell of zero width exists, likely there will be ... 11010000 ... status switch, wherein first 0 is exactly " bubbling ", this status code with " bubbling " can cause the searching of negative edge to be difficult to realize, and have found also inaccurate.In order to retrieve the loss that this part causes and the design difficulty reducing change edge searching circuit, the present invention proposes before the tap status switch that will latch sends into the searching of signal intensity edge and coding circuit, the tap of delay cell is reordered, is equivalent to the delay cell number carrying out the tap state of delay cell to reorder to reduce to greatest extent 0 width.
In this embodiment, according to each cell delay amount distribution plan that code density method measures, the tap position of the tap of 0 width unit and next unit is exchanged, code density method transfer delay cell width distribution plan is again used (to be similar to Fig. 3 a) after adjustment order, as also having the delay cell of 0 width to exist, just again by above-mentioned rule adjustment, again measure, again adjust, until the delay cell having little or no 0 width occurs.So far, reordered, the tap state then flip-flop array latched gives ensuing signal intensity along finding and coding circuit according to new order.
Fig. 4 measures the delay cell width distribution figure obtained after the embodiment of the present invention reorders as stated above, width all is not as seen 0.
Also can find out from Fig. 3 a, except front four delay cells seem to look like exception, the difference of the delay width of other each delay cells is very large.The integral nonlinearity figure of Fig. 3 b to be the differential nonlinearity figure of the delay width calculation according to Fig. 3 a, Fig. 3 c be delay width calculation according to Fig. 3 a.The horizontal ordinate of Fig. 3 b and Fig. 3 c is the tap number of delay chain, and the unit of ordinate is desirable delay cell width (a LSB:Least Significant Bit)).The nonlinearity erron showing the delay cell of this embodiment from Fig. 3 b and Fig. 3 c is very large.In prior art, so large nonlinearity erron is necessarily required to carry out correcting by unit to measurement result, general based in the TDC structure of signal delay chain, all to have online by cell correcting circuit, utilize the integral nonlinearity measured to demarcate measurement result each time.But as previously mentioned, the present invention eliminates above-mentioned nonlinearity erron by " extraction " technology, thus does not need by cell correcting circuit.
In this embodiment, when extracting, need first to set in this TDL the tap sum R needing to carry out extraction process, the present embodiment is set as R=80, then the desirable delay length of each delay cell can be calculated according to the clock period, the clock period of the present embodiment is 1.408ns, and desirable delay cell length (LSB) is 17.6ns.Because four delay cells starting in Fig. 3 a and pulse producer are in the same logical block of FPGA (SLICE), it postpones some exception of wide variety, directly ignores them, the 5th delay cell is demarcated as first B in the present embodiment
1.Next be exactly the extraction process of 80 taps, this process calculates realization by the MATLAB program of on PC according to following extraction formula.See Fig. 2, the delay width of each delay cell is designated as B
1, B
2..., B
n, the output tap of each delay cell is labeled as S respectively
1, S
2..., S
n, the tap after extraction is labeled as T
1, T
2..., T
r, R=80 in the present embodiment.Start to be set as B
0=0, T
iextract as S
l, l meets the following conditions:
Pass through
Calculate a minimum l, the tap S that this minimum l value is corresponding
lbe exactly the T after extracting
i.
The extraction process that above formula represents is the error minimize making integral nonlinearity.
Fig. 5 a and Fig. 5 b is the differential nonlinearity figure that measures of delay chain code density method after extracting and integral nonlinearity figure.Visible, compare with Fig. 3 c with Fig. 3 b, the nonlinearity erron that Fig. 5 a and Fig. 5 b shows improves a lot.
Reordering and extracting to delay cell in the present invention, utilization be the reconfigurable feature of FPGA, the annexation of interconnection network be changed accordingly, namely this interconnection network is directly by tap S
lbe connected to T
i.The Include file that this change can utilize MATLAB program automatically to change in FPGA synthesis tool software realizes, and does not need the participation of hand layouts.
In this embodiment, because measured signal triggers the negative edge of a pulse producer, this negative edge indicates the transmission of measured signal on TDL, the status code that TDL is latched has ... 11110000 ... form, now such code word gives signal intensity respectively along finding and coding circuit, found out the position of negative edge by it, and generate " one-hot " code of a mark negative edge position, and then be encoded to binary code output by " one-hot " code.This process nature is first-class is together by the basic problem of thermometer-code to the transform coding of binary code.
Signal intensity is all the basic look-up table in fpga chip in minimum logical resource unit along the fpga logic resource found and coding circuit uses.The specific constructive form of the basic look-up table resource in current two large main flow FPGA (Xilinx and Altera) is incomplete same, the key distinction is different with output signal number in the maximum bit wide of the input of basic look-up table, and the basic look-up table configuration of the Kintex-7FPGA that such as the present embodiment uses as shown in Figure 7.It has 6 input ends, 2 output terminals.This look-up table can be used as one 6 input look-up table (6-LUT), also can be used as 25 inputs look-up table (5-LUT), now 15 will be assigned 1.The look-up table of the FPGA of other series or other company is similar with this.The look-up table of Fig. 7 is used as 2 5-LUT by the present embodiment, and one of them is for the searching circuit of negative edge, and another for the time being need not.The searching principle on change edge as shown in Figure 8.Utilize sliding window structure is parallel finds in window whether have interested change edge, the width of each sliding window is 5, and it is the input bit wide of basic look-up table.If the input of last window is less than 5, then use " 1 " polishing.If be found to interested change edge in a window, the output of this window has been 1, otherwise is 0.TDL status code through having reordered just is transformed to " one-hot " code by output fenestrate like this.D is used in Fig. 8
irepresent " one-hot " code of negative edge, i is 0 or positive integer.
Table 1. changes the truth table along finding circuit
The truth table for changing the basic look-up table along searching with " bubbling " error correcting capability that table 1 provides for the embodiment of the present invention, wherein D
ibe only just 1 in 11110 situations, other situation is 0.
The arrangement of above-mentioned truth table, make change along find there is certain " bubbling " fault-tolerant ability, such as if there is ... 1111010000 ... code word, then last 1 will be left in the basket.In other words by the truth table assignment of look-up table, change has " bubbling " error correcting capability along finding.For the present embodiment, maximum can the situation of error correction be occur continuous 3 " bubblings ".This has been enough for the state code word through TDL status re-arrangement sequence, because in our practice, do not find that there is the generation of continuous two " bubbling " situations.
In " one-hot " code of the present embodiment, only have one 1, all the other are all 0, and wherein the position (certainly, also can be only have 0, all the other be all 1, and wherein the position of 0 is exactly the position on change edge) on change edge is indicated in the position of 1.The present embodiment will be converted into this " one-hot " code the binary code (A of 8
7, A
6, A
5, A
4, A
3, A
2, A
1, A
0).Adopt the thinking of encryption algorithm to be which code word is 1 the some code words in binary code can be caused to be 1 in " one-hot " code.
With A
6encryption algorithm be example, " one-hot " code that table 2 provides for the embodiment of the present invention is to the encoding operation algorithmic descriptions table of binary code.
Table 2. makes coding export all D of A6=1
isituation
| A 7 | A 6 | A 5 | A 4 | A 3 | A 2 | A 1 | A 0 | D i |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D 64 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D 65 |
| … | … | … | … | … | … | … | … | … |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D 127 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D 128+64 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D 128+65 |
| … | … | … | … | … | … | … | … | … |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D 128+127 |
It can be A that table 2 lists
6all D of=1
i, have 128 D
ia can be made when equaling 1
6=1.Therefore A
6encryption algorithm should be exactly this logical "or" of 128.This position of 128 can be expressed as x1xxxxxx simply, wherein x respectively value be 0 and 1.Equally, other all positions in binary code are all corresponding 128 D
ilogical "or", there is same expression formula these positions of 128, such as, make A
3all positions of=1 are on xxxx1xxx position.
The realizing circuit principle of above-mentioned encryption algorithm as shown in Figure 9.Here still use basic look-up table, but it is used as 6-LUT here.Three class pipeline structure is utilized to realize the coding inclusive-OR operation of the present embodiment.Wherein the first order is made up of 22 6-LUT, and can receive 132 inputs altogether, there are 4 6-LUT the second level, and the third level only has a 6-LUT, by d type flip flop array buffer data between every grade.The truth table of all 6-LUT is all inclusive-OR operation.The A finally exported
irepresent in binary code.For 8 binary codes of the present embodiment negative edge, need above-mentioned pipeline operation circuit 8 to overlap altogether, their concurrent operations, pipeline organization makes the speed of encoding operation to reach system clock frequency.
The present invention is towards the minimized TDC method for designing of nonlinearity erron.Nonlinearity erron minimizes the raising that must bring measuring accuracy.In order to show the raising of the measuring accuracy that the present invention brings, in the described embodiment, with delay chain as shown in Figure 3 a, achieve the TDC of two passages, do not use by unit bearing calibration, do not adopt yet and of the present inventionly reorder and extract, measure a fixed time interval.Measured by the histogram that obtains as Fig. 6 a.Equally, we reorder and abstracting method towards nonlinearity erron is minimized with of the present invention, and realize the TDC of two passages, measure the same time interval, the histogram obtained is as Fig. 6 b.Fig. 5 a is compared with Fig. 5 b, visible histogrammic alteration of form, the standard error of measurement is also improved as 12.7ps by 30.9ps.Provable thus, the present invention when not needing by unit correction hardware or software, can obtain high Measurement Resolution.
It should be noted that for a given delay chain, there is a best total tap number of extraction.Figure 10 give the present embodiment realize TDC and measure the standard error of a Fixed Time Interval along with total extraction number variation relation, wherein transverse axis is the total tap number extracted, and the longitudinal axis is the standard error that binary channels TDC measures the 3.3ns time interval.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1., based on a time-digital converter of FPGA, comprise thick clock counter, pulse signal generator, signal delay chain, flip-flop array, interconnection network, signal intensity along finding and coding circuit, and timestamp output circuit, wherein
Described thick clock counter is driven by clock signal of system, for generation of the thick timestamp of measured signal;
So described pulse signal generator transmits with producing a pulse with change edge and be fed in described signal delay chain under the triggering of measured signal;
Described signal delay chain is used for carrying out delay transport to measured signal, be made up of, and the front end of each delay cell has tap multiple delay cell;
Described flip-flop array is used for latching each tap state of signal delay chain, and the tap state of latch is passed to described interconnection network according to the natural ordering of described tap;
Described interconnection network is used for the tap state received to convert according to the annexation preset, then passes to described signal intensity along finding and coding circuit;
Described signal intensity edge searching and coding circuit for finding the change edge of the pulse transmitted in described signal delay chain be latched, and generate according to the position on described change edge the binary code representing thin timestamp;
Described timestamp output circuit is used for according to signal intensity along finding and being converted into the arrival timestamp of measured signal together with the thin timestamp of binary code of coding circuit output and the thick timestamp that exports of thick clock counter and being exported.
2. as claimed in claim 1 based on the time-digital converter of FPGA, it is characterized in that, the conversion that the tap state received is carried out according to the annexation preset comprises by described interconnection network: each tap of described signal delay chain reordered, and determines a kind of annexation described flip-flop array being connected to the searching of described signal intensity edge and coding circuit.
3., as claimed in claim 2 based on the time-digital converter of FPGA, it is characterized in that, described in reorder and comprise: the tap position of the tap of 0 width delay cell and next delay cell is exchanged.
4. as claimed in claim 3 based on the time-digital converter of FPGA, it is characterized in that, described reordering can repeatedly be carried out, the delay width of each delay cell is measured after once adjustment order, judge that whether the delay cell number of 0 width is more than a threshold value, if so, then again reorder, until the number of 0 width delay cell is no more than described threshold value.
5. as claimed in claim 4 based on the time-digital converter of FPGA, it is characterized in that, the delay width of each delay cell of described measurement is the delay width adopting code density method to measure each delay cell.
6. the time-digital converter based on FPGA according to any one of claim 1 to 5, it is characterized in that, the conversion that the tap state received is carried out according to the annexation preset comprises by described interconnection network: extract each tap of described signal delay chain, determines a kind of annexation described flip-flop array being connected to the searching of described signal intensity edge and coding circuit.
7. as claimed in claim 6 based on the time-digital converter of FPGA, it is characterized in that, the rule of described extraction is: the integral nonlinearity that the temporal interpolation done based on described signal delay chain is measured is minimum.
8., as claimed in claim 7 based on the time-digital converter of FPGA, it is characterized in that, described extraction is: the total tap number after being extracted in first setting signal delay chain is R, then according to system clock cycle T
clockcalculate the ideal delay length w:w=T of the groups of delay cells formed after extracting
clock/ R T
clock, and complete extraction according to this ideal delay length w.
9., as claimed in claim 8 based on the time-digital converter of FPGA, it is characterized in that, extraction be the tap S meeting following formula
l, 1≤l≤n:
Wherein, if the delay width of original each delay cell is B
1, B
2, B
3..., B
n, n is the number of delay cell, and the output tap of each original delay cell is designated as S respectively
1, S
2, S
3..., S
n, the tap after extraction is designated as T
1, T
2, T
3..., T
r, set up to make above formula and need increase by measure B
0, and set: B
0=0; The i given to each, to calculate the minimum l value that meets above formula, the tap S that this minimum l value is corresponding
lbe exactly the T after extracting
i.
10. as claimed in claim 1 based on the time-digital converter of FPGA, it is characterized in that, described signal intensity generates one along searching and coding circuit according to the tap state received from described interconnection network and represents the thermometer-code of change along position, generate for representing change " one-hot " code along position according to this thermometer-code, then the binary code that " one-hot " code conversion is expression timestamp will be somebody's turn to do.
11., as claimed in claim 10 based on the time-digital converters of FPGA, is characterized in that, described signal intensity is along to find and described thermometer-code cutting is obtained 2 by the window of a movement by turn by coding circuit
nindividual window value, n=2
n, n is the number of delay cell, and the bit wide of described window is that m, m are natural number and 2≤m≤2
n, and obtain " one-hot " code corresponding with described thermometer-code by the true value corresponding to window value described in sequential.
12. as claimed in claim 11 based on the time-digital converter of FPGA, and it is characterized in that, the truth table changed between all possible window value and corresponding true value is stored in the basic logic unit LUT in FPGA.
13. as claimed in claim 12 based on the time-digital converter of FPGA, it is characterized in that, when described signal intensity along find and coding circuit for finding the negative edge of thermometer-code time, in described truth table, only have last to be 0, true value corresponding to window value that all the other are 1 be 1, true value corresponding to all the other window value is 0; Or only have last to be 0, true value corresponding to window value that all the other are 1 be 0, true value corresponding to all the other window value is 1.
14., as claimed in claim 10 based on the time-digital converters of FPGA, is characterized in that, described change along searching and coding circuit for " one-hot " code represented with " 1 ", by calculating 2
n-1the logical "or" computing of individual " one-hot " code word obtains the coding of each of binary code; For " one-hot " code represented with " 0 ", by calculating 2
n-1the logic "and" operation of individual " one-hot " code word obtains the coding of each of binary code.
15. as claimed in claim 14 based on the time-digital converter of FPGA, it is characterized in that, described change realizes described logical "or" computing or logic "and" operation along the LUT found and coding circuit utilizes pipeline organization to combinationally use FPGA, the logical "or" computing that every one-level of streamline is one or several parallel dependence LUT and realizes or logic "and" operation.
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