CN106227026B - A kind of time-interval counter of double delay interpolation methods - Google Patents
A kind of time-interval counter of double delay interpolation methods Download PDFInfo
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- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
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Abstract
The present invention provides a kind of time-interval counters of double delay interpolation methods, base delay chain clock synchronization base reference signal is postponed when delay being used to constitute for the delay cell of n Δ τ, is latched using the time-base signal collection that delay obtains to state of the event signal after event delay chain.The delay for choosing delay cell in event delay chain is (n-1) Δ τ, the time difference for being less than individual event delay cell time delay in time interval to be measured can be then further separated out after repeatedly latching, the measurement accuracy of Δ τ can be obtained using the delay cell that delay is n Δ τ and (n-1) Δ τ by handling by the data obtained to latch.The present invention can provide theory and technology reference for the design of high precision time interval measurement equipment.In addition, the present invention is simple to manufacture, the cost of high precision time measurement equipment can significantly reduce, convenient for marketization operation.
Description
Technical field
The present invention relates to a kind of high precision time interval counters, belong to Measuring and Testing Technologies and Instruments subject.
Background technique
Time-interval counter (Time Interval Counter, TIC) is a kind of for two physics things of precise measurement
The instrument of part interval time, it is not only basic in atomic nucleus and particle physics research, gravitational wave detection, geodynamic study etc.
Research field has important application, while being widely used in such as aerospace, deep space communication, satellite navigation, geological mapping, electric power
In terms of the national defence such as transmission and scientific algorithm and the development of the national economy.
The time measurement module of current time interval counter mainly uses interpolation measuring technique, by time interval to be measured point
Two parts are surveyed for " thick " survey and " essence ", " thick " survey part measures portion's complete cycle of time interval to be measured using direct counting method
Point, " essence " surveys part and carries out precise measurement using aperiodic component of the interpositioning to time interval to be measured.But it is adopted at present
The time-interval counter of " thin " time measurement is realized with delay chain interpolation method, Measurement Resolution and measurement accuracy are by inside it
The transmission delay of single delay cell determines in delay chain, must use the delay of smaller delay to obtain higher measurement accuracy
Unit increases device fabrication difficulty, manufacturing cost, and power consumption increases.
Summary of the invention
For overcome the deficiencies in the prior art, the time-interval counter that the present invention provides a kind of double delay interpolation methods is set
Meter, the delay cell being delayed greatly using two kinds obtains higher time Measurement Resolution, while having reached saving device fabrication
Cost, the purpose for reducing power consumption.
The technical solution adopted by the present invention to solve the technical problems is: including Signal Pretreatment unit, compensation of delay list
First, double delay interpolation structures, storage unit and control unit；
The Signal Pretreatment unit generates reference signal according to measured signal and clock reference signal, control is believed
Number and reset signal, first clock reference signal after wherein reference signal and measured signal arrive is synchronous, and control is believed
Number reference signal is lagged behind, reset signal lags behind control signal；Signal Pretreatment unit by the reference signal,
Reset signal is sent to double delay interpolation structures and the control signal is sent to control unit；
The compensation of delay unit postpones measured signal, generate measured pulse signal, delay when it is a length of when
Delay of the clock reference signal after Signal Pretreatment cell processing with reference signal；
Double delay interpolation structures include tested delay chain, reference delay chain and latch arrays；
Wherein, the tested delay chain includes N number of delay cell, each delay cell include the first data input pin,
Second data input pin and data output end, the first data input pin of first delay cell receives measured pulse signal, other
First data input pin of delay cell is connect with the data output end of its previous delay cell, the second data of each delay cell
Input terminal resets the signal in tested delay chain after receiving reset signal for receiving reset signal；
The reference delay chain includes M delay cell, and each delay cell includes data input pin and data output
End, for the input terminal of first delay cell for receiving reference signal, the data input pin of other delay cells is previous with it
The data output end of delay cell connects；The reference delay chain is for generating equally spaced reference signal collection { clki, 1≤i
≤M；
The latch arrays include M group trigger, and every group of trigger includes N number of trigger, N in every group of trigger
A trigger and the output end of delay cell in tested delay chain connect one to one, the number of N number of trigger in every group of trigger
It connects one to one according to the output end after latching end and connecting with delay cell in reference delay chain；The latch arrays are for remembering
It records and the latch time for exporting M same intervals is tested the state of delay chain；
The control unit sends register instructions to deposit unit after receiving the control signal；The storage receipt
First clock falling edge of the member after being connected to the register instructions stores the output data of the latch arrays.
The Signal Pretreatment unit includes quad latch, wherein outside the data input pin welding system of the first trigger
Portion's measured signal input terminal, the data input pin of remaining trigger connect the data output end of a trigger, quad latch
Input end of clock welding system external clock reference signal input terminal；The output end of second trigger negates rear and the first trigger
Output end phase and generate the reference signal, the output end of third trigger negates the output end with the second trigger afterwards
Phase negates afterwards and described in the output end phase of third trigger and generation with the control signal, the output end of the 4th trigger is generated
Reset signal.
In the tested delay chain delay cell be two input and door, single gate delay τ E=(n-1) Δ τ, wherein
Δ τ is the Measurement Resolution that counter is realized in advance, and the minimal design that (n-1) Δ τ is greater than delay cell is delayed, and delay cell
Number N=Tref/ τ E+n, Tref is the period of the clock reference signal.
In the reference delay chain delay cell be two input with door or two input or door, two of each delay cell
Input terminal simultaneously connects, single gate delay τ C=n Δ τ, and the number of delay cell is M=Tref/ τ C.
The invention also includes coarse counter modules, carry out complete cycle to the clock reference signal of input in time interval to be measured
Phase counts, and measured signal is terminated after reaching and counted, and is sent into count results in the register instructions for receiving described control unit
Deposit unit saves, and is zeroed out after receiving the reset signal then to arrive to the count value in coarse counter module.
The invention also includes data processing modules, handle the data stored in deposit unit, when exporting to be measured
Between be spaced numerical value.
The beneficial effects of the present invention are: benchmark is believed by the delay cell with delay respectively n Δ τ and (n-1) Δ τ
Number and measured signal postponed, utilize reference signal collection after delay to lock the thin time interval measurement that tested delay chain generates
Value, measurement result can achieve the time Measurement Resolution of Δ τ.One work of covering is gone with a large amount of smaller delay units are used
The conventional method of clock cycle is compared, and double delay interpolation type structures only need general delay delay cell that is less, being easier to realization
High-precision time interval measurement can be realized, while reducing delay cell usage quantity, reduce the system of measuring device
Difficulty and manufacturing cost are made, and reduces the power consumption of equipment to a certain extent.
Detailed description of the invention
Fig. 1 is a kind of time-interval counter schematic diagram of double delay interpolation methods disclosed in the embodiment of the present application；
Fig. 2 is the schematic diagram of Signal Pretreatment unit disclosed in the embodiment of the present application；
Fig. 3 is the output schematic diagram of Signal Pretreatment unit disclosed in the embodiment of the present application；
Fig. 4 is a kind of double delay interpolation structural schematic diagrams disclosed in the embodiment of the present application.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples, and the present invention includes but are not limited to following implementations
Example.
The present invention provides a kind of time-interval counter of double delay interpolation methods, including Signal Pretreatment unit, delay are mended
Repay unit, double delay interpolation structures, storage unit and control unit, wherein
The Signal Pretreatment unit, measured signal and clock reference signal for being inputted according to system generate benchmark ginseng
Signal, control signal and reset signal are examined, first clock reference after wherein reference signal and measured signal arrive is believed
Number synchronization controls signal lag in reference signal, and reset signal lags behind control signal, then believes the reference
Number, reset signal is sent to double delay interpolation structures and the control signal is sent to control unit；
The measured signal that the compensation of delay unit is used to input system postpones, and compensation is passed through by clock reference signal
Signal Pretreatment unit generates measured pulse signal to the delay of reference signal output end；
Double delay interpolation structures, for being delayed to the measured pulse signal, and at different times to prolonging
When result locked, stored, mainly have: tested delay chain, reference delay chain and latch arrays are constituted, wherein
The tested delay chain includes N number of delay cell, and the delay cell includes the first data input pin, the second data
Input terminal and data output end, the first data input pin of first delay cell are other for receiving the measured pulse signal
First data input pin of delay cell is connect with the data output end of its previous delay cell, the second data of each delay cell
Input terminal resets the signal in tested delay chain after receiving the reset signal for receiving the reset signal；
The reference delay chain includes M delay cell, and the delay cell includes data input pin and data output end,
For the input terminal of first delay cell for receiving the reference signal, the data input pin of other delay cells is previous with it
The data output end of delay cell connects, and the delay chain is for generating equally spaced reference signal collection { clki, 1≤i≤M；
The latch arrays are made of M group trigger identical with delay cell quantity in the reference delay chain, often
A trigger group is made of N number of trigger identical with delay cell quantity in the tested delay chain, and each triggering
Device and the output end of the tested delay cell connect one to one, and the data of N number of trigger latch end simultaneously in every group of trigger
The output end of reference delay unit described in Lian Houyu connects one to one.The latch arrays are for recording M same intervals
Latch time be tested delay chain state；
Described control unit for receiving the control signal of Signal Pretreatment unit generation, and is receiving the control
Register instructions are sent after signal to deposit unit；
The deposit unit, for receiving the register instructions of described control unit, and after being connected to the register instructions
First clock falling edge stores the data of the latch arrays.
Preferably, the delay cell of the tested delay chain is two inputs and door, and single gate delay is τ E=(n-1) Δ
τ, wherein Δ τ is the Measurement Resolution that counter is realized in advance, and (n-1) Δ τ should be greater than setting the hardware capabilities energy of timing delays unit
The smallest delay realized, and the number N of delay cell=Tref/ τ E+n, Tref is the period of the clock reference signal.
Preferably, delay cell is two inputs and door or two inputs or door in the reference delay chain, when use two
Input terminal simultaneously connects, and single gate delay is τ C=n Δ τ, and the number of delay cell is M=Tref/ τ C.
Preferably, further includes:
Coarse counter module, by being carried out based on complete cycle in time interval to be measured to the clock reference signal of system input
Number, can realize in FPGA inside programming, carry out addition meter to the reference clock signal that system inputs by binary adder
Number.Coarse counter module should with Signal Pretreatment unit generate reset signal, measured pulse signal, system input reference when
It is connected between clock signal and the deposit signal of control unit output.Coarse counter module is to reference clock after system starts
Signal is counted, and measured signal is terminated after reaching and counted, and will be counted and tied in the register instructions for receiving described control unit
Fruit is sent into deposit unit and saves, and carries out after receiving the reset signal then to arrive to the count value in coarse counter module clear
Zero, to be ready for thick value counting next time.The module can be used as a part of time-interval counter for extending
The range of measuring instrument can also cancel the part, and the measurement accuracy and resolution ratio of instrument are constant at this time, but can only measure and be less than ginseng
Examine the time interval of clock cycle.
Data processing module exports time interval number to be measured for handling the data stored in deposit unit
Value.The functions of modules can also be provided by external system, and measuring system should design data channel and facilitate deposit unit at this time
Data output.
Preferably, the Signal Pretreatment unit, is made of quad latch, wherein the data input pin of the first trigger
Measured signal input terminal outside welding system, the data input pin of remaining trigger connect the data output end of a trigger, and four
The input end of clock welding system external clock reference signal input terminal of position trigger.The output end of second trigger negate after with the
The output end phase and the generation reference signal, the output end of third trigger of one trigger negate rear and the second trigger
Output end phase and generate the control signal, the output end of the 4th trigger negate afterwards with the output end phase of third trigger with
Generate the reset signal.
Fig. 1 is a kind of time-interval counter of double delay interpolation methods disclosed in the embodiment of the present application；
Shown in Figure 1, which includes: Signal Pretreatment unit, compensation of delay unit, in double delays
Inserting structure, control unit and deposit unit.
Signal Pretreatment unit generates benchmark ginseng according to the measured signal of system input and clock reference signal referring to fig. 2
Signal, control signal and reset signal are examined, and reference signal and reset signal are sent to double delay interpolation structures respectively,
And send control signals to control unit.
Compensation of delay unit and the first data of system measured signal input terminal and the first delay cell of tested delay chain are defeated
Enter end to be connected, for being delayed to the measured signal that system inputs, generates measured pulse signal, compensating clock reference signal warp
Input signal processing unit generates the response delay of reference signal, can be used identical with reference signal is generated in Fig. 2
Structure carries out delay process realization to signal.
Double delay interpolation structures, referring to fig. 4, comprising: tested delay chain, reference delay chain and latch arrays.
Tested delay chain is delayed to measured pulse using N number of delay cell, and delay cell is inputted including the first data
End, the second data input pin and data output end, the first data input pin of first delay cell connect the defeated of compensation of delay unit
First data input pin of outlet, other delay cells is connect with the data output end of its previous delay cell, each delay cell
The second data input pin be used to receive the reset signal of Signal Pretreatment unit generation, it is clear after receiving the reset signal
Signal in the tested delay chain of sky, the signal emptied at this time are remaining letters in tested delay chain after the preceding one-shot measurement thin time
Number.The delay time length of delay cell is τ in tested delay chainE, the delay length for being tested delay chain is T1=N* τE, answer
Not less than the period of clock reference signal.
Reference delay chain includes that M delay cell postpones reference signal, generates M equally spaced latch times,
Latch reference is provided for latch arrays.This group of delay cell includes data input pin and output end, the number of first delay cell
The reference signal that Signal Pretreatment unit generates is received according to input terminal, the data input pin of remaining delay cell is previous with it
The data output end of delay cell connects.It can be seen that Signal Pretreatment unit generates by the waveform of reference signal in Fig. 3
Be that signal value is kept to 0 to pulse signal after a period of time, therefore, no signal is residual in reference delay chain in measurement next time
It stays, so there is no need to be zeroed out to it.The delay length of delay cell is τ in reference delay chainC, the delay length of reference delay chain
For T2=M* τC, value should be equal with the period of clock reference signal.
Latch arrays are made of M group trigger identical with reference delay element number, the data lock of each group trigger
It deposits end and the data output end of the reference delay unit connects one to one, provide M equally spaced locks for each group trigger
Deposit the moment.Each trigger group is made of N number of trigger identical with tested delay cell quantity, and each trigger number
It connects one to one according to input terminal and the output of the tested delay cell, for recording tested delay chain in data latch time
State, when measured pulse signal is propagated in tested delay chain, when passing to some delay cell output end, corresponding trigger
Trigger will obtain the signal of high level, therefore pass through the available corresponding lock of the state of trigger groups different in latch arrays
Deposit the specific location of moment measured pulse signal some delay unit in tested delay chain.
The delay cell that measured signal is propagated in delay chain when traditional delay interpolation method is arrived using clock signal
It counts to quantify time interval to be measured, quantization error is the transmission delay of single delay cell.In double delays that the application proposes
The method of inserting is single to being less than using the delay inequality of the delay cell of used reference delay chain and the delay cell of tested delay chain
The time difference further fine quantization of tested delay cell transmission delay.If high level touches in the first trigger of latch time group for the first time
The quantity for sending out device is K1, then K is flowed through1The signal of+1 delay cell is not detected because not reaching delay cell signal output end
It arrives, causes to flow through K1The time of+1 delay cell is unrecognized.The reference delay unit delay selected due to double delay interpolation methods
Be delayed big Δ τ than tested delay cell, therefore, next latch time latch signal will than measured pulse signal lag Δ τ,
Then at this point, flowing through K1The time of+2 delay units will flow through K than a upper latch time1The time of+1 delay cell reduces Δ τ, such as
This assumes to pass through K2K is flowed through after secondary latch1+K2The time of delay cell is 0, then knows to flow through K when latching for the first time1+ 1 delay is single
The time of member is (K2- 1) thus Δ τ can further measure the time difference less than delay cell transmission delay, obtain high-precision
Measurement result.
First to be tested in delay chain as unit of the delay length of single delay cell, pass through the latch knot of the first trigger group
Fruit shows first order fine measurement；Again using the delay inequality of reference delay unit and tested delay cell as linear module, pass through
It searches the trigger group position more not increased than previous group of first high level trigger number in latch arrays and realizes the second level
Fine measurement.Fine time interval can be measured by the two-stage measurement structure that latch arrays construct in this way.
Control unit receives the control signal of Signal Pretreatment unit output, and sends deposit upon receiving the control signal
Instruction value deposit unit, the register instructions are used to control deposit unit under first reference clock after control signal issues
Drop stores the data in double delay structures in latch arrays along the moment.Signal Pretreatment unit exports after storing
Reset signal empties the signal remained in tested delay chain, waits the measurement of next time.
Deposit unit receives the register instructions of described control unit, and in first reference after controlling signal and sending
The clock failing edge moment stores the record result in memory array.
Reference signal is carried out M grades of delays, utilizes the base obtained after delay by time-interval counter disclosed in the present embodiment
Calibration signal collection latches transmission state of the measured pulse signal in tested delay chain, is recorded using latch arrays different
Latch time is tested the signal in delay chain and propagates position, is not increased by initial latch value and first high level trigger number
The position building two Stage interpolation result of trigger group obtains the measurement result of thin time.With the delay list for using a large amount of minimum delays
Member goes the conventional method of one operating clock cycle of covering to compare, double delay interpolation methods only need it is some be easier to realize be delayed greatly
Delay cell, so that it may realize high-precision time measurement, the manufacturing cost of measuring device be greatly reduced, in conjunction with coarse counter
Module carries out thick time measurement, it can be achieved that a wide range of, the high-precision time measures, convenient for large-scale production and application.
Specifically, input signal processing unit is made of quad latch, pass through the clock reference signal inputted to system
It carries out processing and generates reference signal, control signal and reset signal.As shown in Fig. 2, the data of first order trigger input
Terminating systems measured signal input terminal, the data input pin of remaining trigger connect the data output end of its upper level trigger, respectively
The input end of clock of grade trigger connects external clock reference signal input terminal.After the inverted device of the output end of second level trigger with
The output end phase of first order trigger and reference signal is generated, with second after the inverted device of the output end of third level trigger
The output end phase of grade trigger and generate control signal, after the inverted device of the output end of fourth stage trigger with third level trigger
Output end phase and generate reset signal.Since measured signal successively reaches flip-flop datas at different levels by four rising edge clocks
Output end, therefore the width of inverted device and two inputs and the signal pulse exported behind the door is the height electricity an of reference clock cycle
Between usually, between three signals between be divided into the low level time of a reference clock cycle, so both can guarantee prolonging thereafter
Slow stable structure work, but the processing timing that can avoid each unit module occurs normally, making system steady operation.
Delay cell in delay chain is tested in delay structure disclosed in the present embodiment can be used two inputs and door, alternative number
It is realized according to similar units such as selectors.
Two inputs and door or two inputs or door can be used in unit in reference delay chain in delay structure disclosed in the present embodiment
Similar units are realized, and are inputted and are held and connect.Delay structure can also be realized in FPGA in ASIC, general
Property is strong.
The Method Of Time Measurement of the time interval counter using double delay interpolations is introduced below.Time interval to be measured
By two pulse startings and the forward position time interval between measuring signal can be terminated:
T=tIt terminates-tStarting
Wherein, t is time interval to be measured, tIt terminatesIndicate the forward position moment of termination signal measuring signal, tStartingIndicate starting
The forward position moment of measuring signal.Pass through the forward position moment of the time-interval counter measuring signal of double delay interpolation methods, measurement
Result can indicate are as follows:
T=tSlightly+tEssence
In formula, tSlightlyFor the measurement result for being slightly worth counter, tEssenceFor the measurement result of double delay interpolation methods；
T=tSlightly+tEssence _ 1+tEssence _ 2
In formula, tEssence _ 1For what is obtained by the first of latch arrays group register, when delay cell single with tested delay chain
Prolong the first order accurate results for unit, tEssence _ 2To be obtained by first group of high level number in latch without increased trigger group
It arrives, the second level measurement result as unit of reference delay unit and tested delay cell delay inequality；
T=K*Tref+K1*τE+(K2-1)*(τE-τC)
In formula, K is the count results of thick value counter, TrefFor the period of the reference clock signal of system input, K*Tref
Namely the measurement result of thick value counter, K1For the high level quantity that first order trigger group latches, K2For first high level
Number is without increased register group serial number, τE=(n-1) * Δ τ is the delay time of delay cell in tested delay chain, τE=n* Δ τ
For the delay time of delay cell in benchmark delay chain；
T=K*Tref+(K1*(n-1)*Δτ+(K2-1)*Δτ)
=K*Tref+((n-1)*K1+K2-1)*Δτ
In this way, the starting Measurement channel by the time-interval counter can to the forward position measurement result of starting measuring signal
It indicates are as follows:
tStarting=KStarting*Tref+((n-1)*K1_ starting+K2_ starting -1)*Δτ
Similarly, Measurement channel is terminated by the another way of the time-interval counter to survey the forward position for terminating measuring signal
Measure result are as follows:
tIt terminates=KIt terminates*Tref+((n-1)*K1_ is terminated+K2_ terminates -1)*Δτ
In turn, obtaining the time interval to be measured according to the measurement result of this two-way may be expressed as:
T=tStarting-tIt terminates
=KIt terminates*Tref+((n-1)*K1_ is terminated+K2_ is terminated-1)*Δτ-(KStarting*Tref+((n-1)*K1_ starting+K2_ starting-1)*Δτ)
=(KIt terminates-KStarting)*Tref+(n-1)*(K1_ is terminated-K1_ starting)*Δτ+(K2_ is terminated-K2_ starting)*Δτ
Finally, it is to be noted that, each embodiment in this specification is described in a progressive manner, first to it is entire when
Between interval counter carry out whole introduction, then introduce the specific implementation of each part in time-interval counter.
Illustrate the foregoing description of disclosed embodiment to this, it is therefore an objective to make those skilled in the art can be realized or
Use the application.Carrying out a variety of modifications to these embodiments is easy to accomplish, sheet for those skilled in the art
General Principle proposed in text can be real in other embodiments without departing from the spirit or scope of the application
It is existing.Therefore, the application is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The widest scope consistent with features of novelty.
Claims (6)
1. a kind of time-interval counter of double delay interpolation methods, including Signal Pretreatment unit, compensation of delay unit, double delays
Interpositioning, storage unit and control unit, it is characterised in that:
The Signal Pretreatment unit according to measured signal and clock reference signal generate reference signal, control signal and
Reset signal, first clock reference signal after wherein reference signal arrives with measured signal is synchronous, and control signal is stagnant
Afterwards in reference signal, reset signal lags behind control signal；Signal Pretreatment unit by the reference signal, reset
Signal is sent to double delay interpolation structures and the control signal is sent to control unit；
The compensation of delay unit postpones measured signal, generates measured pulse signal, the when a length of clock ginseng of delay
Examine delay of the signal after Signal Pretreatment cell processing with reference signal；
Double delay interpolation structures include tested delay chain, reference delay chain and latch arrays；
Wherein, the tested delay chain includes N number of delay cell, and each delay cell includes the first data input pin, second
First data input pin of data input pin and data output end, first delay cell receives measured pulse signal, other delays
First data input pin of unit is connect with the data output end of its previous delay cell, the second data input of each delay cell
End resets the signal in tested delay chain after receiving reset signal for receiving reset signal；
The reference delay chain includes M delay cell, and each delay cell includes data input pin and data output end, head
For the input terminal of a delay cell for receiving reference signal, the data input pin of other delay cells and its previous delay are single
The data output end connection of member；The reference delay chain is for generating equally spaced reference signal collection { clki, 1≤i≤M；
The latch arrays include M group trigger, and every group of trigger includes N number of trigger, N number of triggering in every group of trigger
Device and the output end of delay cell in tested delay chain connect one to one, and the data of N number of trigger latch in every group of trigger
Output end after holding and connecting with delay cell in reference delay chain connects one to one；The latch arrays for record and it is defeated
The latch time of M same intervals is tested the state of delay chain out；
The control unit sends register instructions to deposit unit after receiving the control signal；The deposit unit exists
First clock falling edge after being connected to the register instructions stores the output data of the latch arrays.
2. the time-interval counter of double delay interpolation methods according to claim 1, it is characterised in that: the signal is pre-
Processing unit includes quad latch, wherein measured signal input terminal outside the data input pin welding system of the first trigger,
The data input pin of remaining trigger connects the data output end of a trigger, outside the input end of clock welding system of quad latch
Portion's clock reference signal input terminal；The output end of second trigger negates afterwards and described in the output end phase of the first trigger and generation
Reference signal, the output end of third trigger negates to be believed with the output end phase of the second trigger and the generation control afterwards
Number, the output end of the 4th trigger negate afterwards with the output end phase of third trigger and generate the reset signal.
3. the time-interval counter of double delay interpolation methods according to claim 1, it is characterised in that: described tested to prolong
Delay cell is two inputs and door in slow chain, and single gate delay τ E=(n-1) Δ τ, wherein Δ τ is the survey that counter is realized in advance
Resolution ratio is measured, the minimal design that (n-1) Δ τ is greater than delay cell is delayed, and the number N of delay cell=Tref/ τ E+n, Tref
For the period of the clock reference signal.
4. the time-interval counter of double delay interpolation methods according to claim 1, it is characterised in that: the benchmark prolongs
Delay cell is that two inputs simultaneously connect, single door with door or two inputs or door, two input terminals of each delay cell in slow chain
Be delayed τ C=n Δ τ, and the number of delay cell is M=Tref/τC。
5. the time-interval counter of double delay interpolation methods according to claim 1, it is characterised in that: further include slightly counting
Device module, carries out counting complete cycle to the clock reference signal of input in time interval to be measured, and measured signal terminates after reaching
It counts, and count results is sent into deposit unit in the register instructions for receiving described control unit and are saved, receiving then
The count value in coarse counter module is zeroed out after the reset signal of arrival.
6. the time-interval counter of double delay interpolation methods according to claim 1, it is characterised in that: further include at data
Module is managed, the data stored in deposit unit are handled, time interval numerical value to be measured is exported.
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| CN106814595B (en) * | 2017-02-08 | 2022-03-18 | 中国科学院精密测量科学与技术创新研究院 | High-precision TDC based on equivalent subdivision and equivalent measurement method thereof |
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