CN108736885B - Phase-locked loop clock edge triggered clock phase-splitting method - Google Patents

Abstract

The invention discloses a phase-locked loop clock edge triggered clock phase-splitting method, belongs to the field of time interval measurement, and aims to solve the problems of low resolution, high system running frequency and low performance of the conventional clock phase-splitting method. The specific process of the invention is as follows: inputting a clock signal of 100MHz to an input end of a phase-locked loop; frequency multiplication is carried out on the clock signal to 315MHz, and eight phase shifts are carried out on the high-level section; taking the edge of the clock signal after the frequency multiplication and phase shift of the phase-locked loop as a trigger signal; carrying out clock synchronization processing on the detected signal; respectively carrying out time sequence constraint on each transmission path of the clock signal and the signal to be tested; extracting the position where the level of the detected signal jumps at the trigger moment; outputting a high level when the rising edge detection function of the detected signal or the falling edge detection function of the detected signal has a rising edge, otherwise outputting a low level; and obtaining the relative position of the rising edge or the falling edge of the measured signal in one clock period. The invention is used for time interval measurement.

Description

Phase-locked loop clock edge triggered clock phase-splitting method

Technical Field

The invention relates to a time interval measuring method, and belongs to the field of time interval measurement.

Background

Time is one of the basic units of physics. What we generally say is time in two senses: one meaning refers to time of day and the other meaning refers to time intervals. Time of day refers to a certain instant of time that elapses continuously, which refers to when a certain event occurs; and the time interval refers to how long the interval between two instants is, it refers to the duration of a certain event.

The precise time is used as a basic physical parameter in aspects of scientific research, scientific experiments and engineering technology, and provides an essential time-based coordinate for measurement and quantitative research of all dynamic systems and time sequence processes. The precise time plays an important role in the basic research fields of atomic nucleus physical research, particle physical research, earth dynamics research, relativistic research, pulsar cycle research, artificial satellite dynamics geodesic research and the like, is also commonly applied in application research, national defense and national economy construction, such as aerospace, deep space communication, satellite launching and monitoring, geological mapping, navigation communication, power transmission, scientific metering and the like, and is almost beyond the aspects of social life of people.

With the increasing living standard of people, high-resolution time interval measurement technology is more and more applied to various civil fields. The research on the time interval measuring method can greatly promote the development of key technologies in the scientific and technical and civil fields of China. However, with the development of technology and the requirement of high precision and various limitations of analog measurement methods, the conventional time interval measurement method is far from meeting the requirement of time interval measurement, so how to utilize digital measurement time interval becomes more important, now digital measurement mainly takes FPGA and ASIC as main parts, but the ASIC has a limited application range due to the defects of long design period, large version change investment, poor flexibility and the like. The FPGA becomes a main platform for people to realize digital logic due to the advantages of high running speed, programmability, short development period, strong flexibility and the like, so that the research on the high-speed precise time interval measurement technology based on the FPGA has important practical significance.

The time-to-digital conversion circuit is a basic means for time measurement, and converts an analog signal carrying time information into a digital signal for digitalization, thereby realizing the measurement of the time information. On the other hand, absolute time information is often not of much significance, but relative time information is of significance, so that many occasions are measurements of time interval information.

In many applications, some measurements of physical quantities may be converted into measurements of time quantities, such as flow, thickness, density, temperature, frequency, and phase shift.

For example, pulse laser ranging is similar to radar ranging in principle, and generally a laser diode is aligned with a target to emit laser pulses, the laser pulses are reflected by the target and then scattered in various directions, and part of scattered light returns to a sensing receiver and is received by an optical system and then imaged on an avalanche photodiode. The avalanche photodiode is an optical sensor having an amplification function therein, and thus it can detect an extremely weak optical signal. The round trip time from the emission of a light pulse to the return being received is recorded and processed, and the distance to be measured is multiplied by the speed of light (30 ten thousand kilometers per second) times one half of the round trip time. If the light travels in air at a speed c and the time t is taken to make a round trip at A, B, the distance D between points A, B can be expressed as:

D＝ct/2 (1)

the existing widely used hand-held and portable range finders have an operating distance of hundreds of meters to tens of kilometers and a measurement precision of about five meters. The high-precision distance measuring instrument for satellite distance measurement developed in China has the measurement precision of several centimeters. Because the speed of light is too fast, the transit time laser sensor must measure transit time extremely accurately, and to achieve resolution, the electronic circuitry of the transit time ranging sensor must be able to resolve the following extremely short time intervals.

Alternatively, in some applications it is desirable to control the thickness of the sheet metal and the pipe wall, etc., where the thickness is to be measured. The corresponding thickness information can be calculated by utilizing the ultrasonic waves reflected by the surface and the back of the object to be measured and the speed of the ultrasonic waves in the corresponding medium, wherein the most important is the time interval measurement between the reflected ultrasonic waves. Therefore, the research on the high-speed precise time interval measurement technology has very important practical significance.

In the early stage of time measurement technology development, electronic technologies such as semiconductor integrated circuits have lagged behind, and in this period, analog measurement is the mainstream method of time interval measurement. Such as time amplification, time-to-voltage conversion, etc., which integrate the current over the time interval to be measured, convert the amount of time that cannot be directly measured into a measurable amount of voltage or charge, and convert the amount of voltage or charge into a digital value through an a/D conversion circuit.

The demand for time measurement is constantly increasing, driving the development of time measurement technology. The analog measurement is increasingly disadvantageous in that it is sensitive to temperature, easily disturbed by external disturbance, complex in design, and requires a relatively long conversion time. Especially in high-energy physical experiments, the analog circuit measurement system is difficult to meet the requirements, but the digital technology gradually becomes the development direction of the electronic system of the detector due to the advantages of flexibility, stability, high speed, parallel processing, low cost and the like. Accordingly, digital measurement techniques are beginning to be favored and popular by researchers.

With the development of microelectronic technology and technology, digital integrated circuits are gradually developed from electronic tubes, transistors, medium and small scale integrated circuits, and very large scale integrated circuits to today's application specific integrated circuits. The implementation of time-to-digital conversion techniques has also accomplished a transition from discrete devices to FPGAs and ASICs. Undoubtedly, the advent of ASIC (application specific integrated circuit) has reduced the production cost of products, improved the reliability of systems, reduced the physical size of designs, and promoted the progress of digitization in society. However, the ASIC has its limited application range due to its defects, and the FPGA has its own strong advantages, so that the FPGA becomes a main application platform for time-to-digital conversion.

In many time-to-digital measurement techniques, the characteristics of the time-to-digital conversion technique based on the FPGA are mainly reflected in the special hardware structure and the small logic gate delay of the FPGA. For example, time delay line methods, Delay Locked Loop (DLL) techniques, etc., all utilize the delay of the device itself to measure the time interval. The basic idea is to find a basic delay unit in the device, cascade the units in a certain way to form a delay chain structure, and allow the time to be measured to pass through the delay chain to realize the time interpolation. This time interval is finally represented by the number of elementary delay units, thus achieving the conversion from time to number.

Disclosure of Invention

The invention aims to solve the problems of low resolution, high system running frequency and low performance of the conventional clock phase-splitting method, and provides a clock phase-splitting method triggered by a clock edge of a phase-locked loop.

The invention relates to a clock phase-splitting method triggered by a clock edge of a phase-locked loop, which comprises the following specific processes:

step 1, inputting a clock signal of 100MHz to an input end of a phase-locked loop;

step 2, frequency doubling the clock signal 100MHz to 315MHz, carrying out eight phase shifts on the high level section of the input clock, and setting the phase shift angles CLK [0] to CLK [7] as 0 degree, 22.5 degrees, 45 degrees, 66.5 degrees, 90 degrees, 112.5 degrees, 135 degrees and 157.5 degrees respectively;

step 3, taking the edges of the eight paths of clock signals after the frequency multiplication and phase shift of the phase-locked loop as sixteen trigger signals;

step 4, performing clock synchronization processing on the detected signal;

step 5, respectively carrying out time sequence constraint on each transmission path of the clock signal and the signal to be tested;

step 6, judging whether the measured signal levels Count [0] to Count [15] at sixteen trigger moments are 0 or 1, and extracting the positions of 0 → 1 jump and 1 → 0 jump in the Count [0] to Count [15 ];

step 7, recording the rising edge detection function event _ up [ n ] or the rising edge/falling edge of the detected signal falling edge detection function event _ down [ n ] by using event _ up _ reg [ n ] or event _ down _ reg [ n ], outputting a high level by using event _ up _ reg [ n ] or event _ down _ reg [ n ] when the rising edge of the detected signal rising edge detection function event _ up [ n ] or the detected signal falling edge detection function event _ down [ n ] occurs, and otherwise outputting a low level by using event _ up _ reg [ n ] or event _ down _ reg [ n ];

and 8, acquiring the relative position of the rising edge or the falling edge of the detected signal in 315MHz of a clock cycle, and completing clock phase splitting.

The invention has the advantages that: the clock phase-splitting method triggered by the clock edge of the phase-locked loop can finish time interval measurement with high performance and high resolution, and compared with the prior art, the time measurement resolution is improved, and the running frequency of a system is reduced. Firstly, a simple binary counter is used for completing a coarse measurement part of a time interval, a fine measurement part adopts a clock phase splitting method, only a high-level part (a half clock period) of a clock is subjected to eight phase shifts, the original resolution is improved by 16 times and can be higher than 165ps, the equivalent measurement frequency of the method is 6080MHz (the input clock is 100MHz, and the frequency after frequency multiplication is 315MHz), the resolution can be higher than 165ps, and the conventional clock phase splitting method is used for carrying out average phase shift on the whole clock period.

Drawings

FIG. 1 is a schematic diagram of a pulse counting method;

FIG. 2 is a schematic diagram of an interpolation time measurement method;

FIG. 3 is a general block diagram of a data acquisition portion;

FIG. 4 is a schematic diagram of a phase locked loop frequency doubling phase shift;

FIG. 5 is a schematic diagram of a data transmission path with a clock edge as a trigger signal;

FIG. 6 is a schematic diagram of the clock phase shift interpolation overall output;

fig. 7 is a waveform diagram of the measured output of the "thin" measurement section.

Detailed Description

The first embodiment is as follows: the clock phase-splitting method triggered by the clock edge of the phase-locked loop in the embodiment specifically comprises the following processes:

step 1, inputting a clock signal of 100MHz to an input end of a phase-locked loop;

step 2, frequency doubling the clock signal 100MHz to 315MHz, carrying out eight phase shifts on the high level section of the input clock, and setting the phase shift angles CLK [0] to CLK [7] as 0 degree, 22.5 degrees, 45 degrees, 66.5 degrees, 90 degrees, 112.5 degrees, 135 degrees and 157.5 degrees respectively;

step 3, taking the edges of the eight paths of clock signals after the frequency multiplication and phase shift of the phase-locked loop as sixteen trigger signals;

step 4, performing clock synchronization processing on the detected signal;

step 5, respectively carrying out time sequence constraint on each transmission path of the clock signal and the signal to be tested;

step 6, judging whether the measured signal levels Count [0] to Count [15] at sixteen trigger moments are 0 or 1, and extracting the positions of 0 → 1 jump and 1 → 0 jump in the Count [0] to Count [15 ];

step 7, recording the rising edge detection function event _ up [ n ] or the rising edge/falling edge of the detected signal falling edge detection function event _ down [ n ] by using event _ up _ reg [ n ] or event _ down _ reg [ n ], outputting a high level by using event _ up _ reg [ n ] or event _ down _ reg [ n ] when the rising edge of the detected signal rising edge detection function event _ up [ n ] or the detected signal falling edge detection function event _ down [ n ] occurs, and otherwise outputting a low level by using event _ up _ reg [ n ] or event _ down _ reg [ n ];

and 8, acquiring the relative position of the rising edge or the falling edge of the detected signal in 315MHz of a clock cycle, and completing clock phase splitting.

In this embodiment, the edge of the clock signal after the frequency doubling and phase shifting is used as the trigger signal, and theoretically, the frequency after the frequency doubling can be subdivided by 16 times, so as to achieve higher frequency. As shown in fig. 4, the PLL is a Phase Locked Loop.

The second embodiment is as follows: in this embodiment, the first embodiment is further described, and the edges of the eight clock signals in step 3 include rising edges and falling edges of the eight clock signals.

The third concrete implementation mode: in this embodiment, a first embodiment is further described, in step 5, the method for extracting the positions where the 0 → 1 jump and the 1 → 0 jump occur in the Count [0] to Count [15] includes:

the Count [ n ] and Count [ n +1] are calculated:

when an event _ up [ n ] (-Count [ n ]) & Count [ n +1] occurs, the position is a 0 → 1 jump position;

when event _ down [ n ] (-Count [ n +1]) & Count [ n ] occurs, it is the position of the 1 → 0 jump;

wherein n is 0,1, …, 15.

The invention provides a precise time interval measurement method based on an FPGA (field programmable gate array). the time interval measurement is divided into a coarse measurement part and a fine measurement part, wherein the coarse measurement part is used for carrying out preliminary measurement by using a counter, and the fine measurement part is mainly realized by carrying out time interpolation by a clock phase-splitting method, so that higher time resolution is obtained.

The most basic method in the conventional time interval measurement technique is the pulse counting method. The pulse IN the pulse counting method refers to a reference clock signal CLK _ IN, which is a time reference for the pulse counting method, and is also called a time base signal. The measured event part consists of a start signal (start signal) and a stop signal (stop signal). The measurement principle of the pulse counting method is based on comparison of physical quantities of the same dimension. The measured time interval is padded with a time-based signal and quantized by counting pulses of the time-based signal. The specific operation principle is shown in FIG. 1, where the start signal is at T₁The counter is opened at the moment, and the stop counting signal is at T₂The counter is stopped at the moment, and the time interval Δ T between the start signal edge and the stop signal edge is measured and counted by a counter clocked by clk.

The method realizes time-to-digital conversion, and has simple structure and logic. The resolution is determined by the clock period, the dynamic range of the measurement is determined by the number of bits of the counter, and the accuracy of the measurement is determined by the stability of the clock.

Because the resolution of the pulse counting method is low, in order to improve the time measurement resolution, a time interpolation method is adopted. Temporal interpolation is a horological technique for obtaining high resolution on the basis of a low resolution time base.

The measurement resolution of the time interpolation is smaller than the time base period, as shown in FIG. 2, and the start signal is at T₁The counter is opened at the moment, and the stop counting signal is at T₂The counter is stopped at a time, the time interval Δ T between the start signal edge and the stop signal edge is measured and counted by a counter clocked with clk, T_clkIs the period of the reference clock signal CLK _ IN, n is the counterNumerical values. Delta T₁Is the time interval, Δ T, between the rising edge of the event signal under test and the rising edge of the time-based signal₂Is the time interval, Δ T, between the falling edge of the event signal and the rising edge of the time-base signal₁And Δ T₂Is a temporally interpolated measurement object. By time interpolation, Δ T can be adjusted₁And Δ T₂These small time intervals, which are smaller than the time base period, are further quantized.

In FIG. 2, the lower middle part is Δ T₁And Δ T₂With arrows representing further quantization scales. Since the time base signal period is a known fixed value, the same interpolation effect can be achieved for the measurements of two different measurement objects. The time interpolation method adopted by the invention is a clock phase splitting method.

The clock phase splitting technology is to utilize multiple phases of a clock cycle to achieve higher time resolution, and is widely applied to high-speed digital system design. Under certain measuring environments, after certain measuring accuracy is met, factors such as system construction, resource consumption and measuring period are considered, and the realization of the TDC based on the FPGA by using the clock phase splitting technology is a good selection scheme.

Fig. 3 is a general structure diagram of a data acquisition part, and a key part is an intermediate FPGA-based TDC method. In the method, the rising edge of an input signal is a time signal to be measured, a coarse time measurement method is constructed by a synchronous parallel counter method, the resolution is the period of a system clock CLK _ sys, and a plurality of channels use coarse time measurement units. The fine time measuring unit comprises a time interpolation time sampling unit based on a multi-phase clock, a data buffering unit and a coding unit.

The model of the chip adopted by the invention is the model of the Stratix IV series EP4SGX230KF40C2, and an internally integrated group phase-locked loop (PLL) is utilized to realize a multi-phase clock circuit, thereby obtaining higher time measurement resolution. The dedicated global clock network (GCLK), local clock network (RCLK), and peripheral clock network (PCLK) in the Stratix IV device constitute a clock architecture with a hierarchical structure that provides up to 236 single clock domains (16GCLK +88RCLK +132PCLK) and supports up to 71 single GCLK, RCLK, and PCLK clock sources (16GCLK +22RCLK +33PCLK) in each device quadrant. Table 1 lists the available clock resources in the stratxiv device.

TABLE 1 clock resources in Stratix IV devices

The stratix iv device provides up to 16 GCLKs that can drive functional blocks (e.g., Adaptive Logic Modules (ALMs), Digital Signal Processing (DSP) modules, TriMatrix memory modules, and PLLs) within the entire device, providing low-skew clock resources. The StratixIV device I/O cells (IOEs) and internal logic can create internally generated global clocks and other high fanout control signals by driving GCLK, such as: synchronous or asynchronous clear and clock enable signals.

The signal under test is selectively transmitted via the global clock line so that the signal under test reaches each acquisition point as close to the same time as possible, so that the implementation of the clock split-phase interpolation is facilitated.

As shown in fig. 5, the data transmission paths are data transmission paths with clock edges as trigger signals, the delay time of each measurement path is analyzed by using the timesest Timing Analyzer, and the particular transmission path is subjected to Timing constraint by using the timesest Timing Analyzer, so that the delay times of the adjacent data transmission paths are as same as possible.

And dividing the fine measurement part into a rising edge part and a falling edge part of the measured signal to carry out time sequence constraint respectively, and selecting proper delay time to carry out time sequence constraint on each path respectively according to the previous measurement result.

And logically locking the module with the timing constraint completed by using LogicLock in a Chip Planner so as to enable subsequent programming to inherit the path delay with good constraint as much as possible.

After the "thin" portion is completed, the "thick" portion and the "thin" portion are integrated together, as shown in fig. 6.

The program was loaded on a DE4 development board (model number of the chip is Stratix IV series EP4SGX230KF40C2), the Signal generator Agilent 33220A generated the Signal under test (square wave, frequency 120MHz), the Signal Tap was used to observe the measured output waveform of the "thin" test part, and the achievable resolution was checked, as shown in fig. 7.

The experimental data actual measurement part takes 5 groups of different time intervals for measurement, 20 data are measured in each group, and the 5 groups of time intervals are preset to be 100ns, 200ns, 500ns, 1000ns and 1500ns respectively.

The resolution was about 165ps from experimental measurements. The time interval is preset to be a small error value of 211ps (relative to oscilloscope measurements) of 100 ns; the time interval is preset to a minimum error value of 274ps for 200ns (relative to oscilloscope measurements); the time interval is preset to a minimum error value of 310ps for 500ns (relative to oscilloscope measurements); the minimum error value for a time interval preset to 1000ns is 257ps (relative to oscilloscope measurements); the time interval is preset to be 1500ns with a minimum error value of 312ps (relative to oscilloscope measurements).

The equivalent time measuring frequency of 100MHz clock input is 6080MHz, thereby effectively improving the time measuring resolution.

Claims (2)

1. The phase-locked loop clock edge triggered clock phase splitting method is characterized by comprising the following specific processes:

step 1, inputting a clock signal of 100MHz to an input end of a phase-locked loop;

step 2, frequency doubling the clock signal 100MHz to 315MHz, carrying out eight phase shifts on the high level section of the input clock, and setting the phase shift angles CLK [0] to CLK [7] as 0 degree, 22.5 degrees, 45 degrees, 66.5 degrees, 90 degrees, 112.5 degrees, 135 degrees and 157.5 degrees respectively;

step 3, taking the edges of the eight paths of clock signals after the frequency multiplication and phase shift of the phase-locked loop as sixteen trigger signals;

step 4, performing clock synchronization processing on the detected signal;

step 5, respectively carrying out time sequence constraint on each transmission path of the clock signal and the signal to be tested;

step 6, judging whether the measured signal levels Count [0] to Count [15] at sixteen trigger moments are 0 or 1, and extracting the positions of 0 → 1 jump and 1 → 0 jump in the Count [0] to Count [15 ];

step 7, recording the rising edge and the falling edge of the detected signal rising edge detection function event _ up [ n ] by using event _ up _ reg [ n ], recording the rising edge and the falling edge of the detected signal falling edge detection function event _ down [ n ] by using event _ down _ reg [ n ],

when the rising edge detection function event _ up [ n ] of the detected signal has a rising edge, the event _ up _ reg [ n ] outputs a high level,

when the falling edge detection function event _ down [ n ] of the detected signal has a rising edge, the event _ down _ reg [ n ] outputs a high level,

when the rising edge detection function event _ up [ n ] of the detected signal has a falling edge, the event _ up _ reg [ n ] outputs a low level,

when the falling edge detection function event _ down [ n ] of the detected signal has a falling edge, the event _ down _ reg [ n ] outputs a low level;

wherein n is 0,1, …, 15;

and 8, acquiring the relative position of the rising edge or the falling edge of the detected signal in 315MHz of a clock cycle, and completing clock phase splitting.

2. The phase-locked loop clock edge-triggered clock splitting method as claimed in claim 1, wherein the edges of the eight clock signals in step 3 comprise rising edges and falling edges of the eight clock signals.

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