CN101520640A - Time interval measuring instrument based on FPGA - Google Patents
Time interval measuring instrument based on FPGA Download PDFInfo
- Publication number
- CN101520640A CN101520640A CN200810046525A CN200810046525A CN101520640A CN 101520640 A CN101520640 A CN 101520640A CN 200810046525 A CN200810046525 A CN 200810046525A CN 200810046525 A CN200810046525 A CN 200810046525A CN 101520640 A CN101520640 A CN 101520640A
- Authority
- CN
- China
- Prior art keywords
- time interval
- fpga
- interval measuring
- pxi
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims abstract description 28
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 238000011161 development Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000036541 health Effects 0.000 claims description 2
- 238000012360 testing method Methods 0.000 abstract description 8
- 230000006870 function Effects 0.000 description 21
- 238000000034 method Methods 0.000 description 17
- 238000013461 design Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 5
- 238000013139 quantization Methods 0.000 description 5
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 3
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 3
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 3
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000003750 conditioning effect Effects 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 241001269238 Data Species 0.000 description 2
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000011426 transformation method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The invention provides a time interval measuring instrument based on an FPGA. The time interval measuring instrument is designed into a virtual instrument by taking a PXI interface as a platform, one PXI system can be inserted with a plurality of PXI board cards, each board card can carry out time interval measurement on signals of 1 starting channel and a plurality of stopping channels, and simultaneously the pulse width of a stopping pulse is measured. The time interval measuring instrument of the invention utilizes the phase-locked loop frequency multiplication and clock phase splitting technology, the measuring resolution can reach 1ns, and the measuring range can reach 20 ns-200 ms. Because the virtual instrument structure is adopted, and the PXI platform and the computer are combined to form the automatic test system, the time interval measuring instrument has the characteristics of simple structure, convenience in use, high reliability, strong expandability and high measuring efficiency.
Description
Technical field
The invention belongs to the data acquisition technology field, be specifically related to a kind of time interval measuring instrucment, be used to measure the time interval between an initial pulse and a plurality of stop pulse and the pulse width of stop pulse based on FPGA.
Background technology
The precise time-time-interval measurement is widely used in the various scientific experimentations, and the instrument that is used as time interval measurement comprises that universal counter, digital storage oscilloscope, hyperchannel time interval measuring instrucment all have characteristics separately.Universal counter costs an arm and a leg, and operation inconvenience, measures passage seldom, gradually post-set time interval measurement occasion.Oscillograph is capturing main status always in electronic measuring instrument, but when independently test point quantity reached tens hundreds ofs, it is very few that oscillographic number of channels just seems, a hundreds of test point just needs to buy up to a hundred oscillographs, and prices are rather stiff.Though oscillograph has strong functions, when being used for the multichannel time interval measurement specially, the most functions of it other all are difficult to use, and this has just caused waste on fund.Oscillograph quantity is too much, can reduce the reliability of experiment to a certain extent, has also increased the integrated difficulty of whole experimental system.The TSN-632 type multichannel precision digital measuring apparatus of THO, No. 32 homemade time interval measuring instrucments are because of simple to operate, measurement accurately and more than the measurement port number are used in scientific experiment in a large number.But along with the development and the experimental requirements of technology are more and more higher, time interval measuring instrucment still requires further improvement, the one, and its serial line interface can not satisfy the requirement of test macro robotization; The 2nd, circuit part mostly is the discrete element, and integrated level is not high, thereby complex structure, and inconvenience is installed, and reliability also needs to improve; The 3rd, cabinet is too heavy, insufficient strength, and bearing capacity is relatively poor, and dismounting inconvenience, has brought difficulty to maintenance.
Chinese patent literature publication number 101013304A discloses the patented claim technology that name is called " a kind of high precision time interval measurement PCI card ", and this technology is owing to adopt special chip, and it is less to measure passage, and extensibility is relatively poor; Because adopt PCI as data-interface, reliability and anti-interference are relatively poor, are not suitable for the high occasions of measurement requirement such as high reliability, hyperchannel.
Summary of the invention
The invention provides a kind of time interval measuring instrucment based on FPGA.
A kind of time interval measuring instrucment based on FPGA of the present invention is formed virtual instrument by hardware system and Control Software, wherein hardware system comprises integrated circuit board and the PXI system that is used for time interval measurement, integrated circuit board is the core of time interval measurement with FPGA, and integrated circuit board is nursed one's health unit, time/Date Conversion Unit, data interface unit by front end signal and formed; The Control Software that is mounted on the PXI system comprises with Windriver to be the driver of development platform and to be the development platform control program with VB.
A kind of time interval measuring instrucment of the present invention based on FPGA, with the PXI interface is that platform design becomes virtual instrument, a PXI system can insert a plurality of PXI integrated circuit boards, each integrated circuit board can carry out time interval measurement to 1 initial passage and a plurality of signal that stops passage, measures the pulse width of stop pulse simultaneously.Time interval measuring instrucment of the present invention utilizes frequency multiplication of phase locked loop and clock phase-splitting technology, and Measurement Resolution can reach 1ns, and measurement range can reach 20ns～200ms.Function only realizes in a slice FPGA during survey on each integrated circuit board of the time interval measuring instrucment based on FPGA of the present invention, owing to adopt the virtual instrument structure, utilize the PXI platform to set up into Auto-Test System jointly with computer structure, not only simple in structure, easy to use, and the reliability height, extensibility is strong, has greatly improved efficiency of measurement.
Description of drawings
The theory diagram of Fig. 1 a kind of time interval measuring instrucment based on FPGA of the present invention
The level Four clock phase-splitting sequential synoptic diagram of Fig. 2 a kind of time interval measuring instrucment embodiment based on FPGA of the present invention
The hardware block diagram of Fig. 3 a kind of time interval measuring instrucment based on FPGA of the present invention
The software architecture diagram of Fig. 4 a kind of time interval measuring instrucment based on FPGA of the present invention
The front end signal conditioning structured flowchart of Fig. 5 a kind of time interval measuring instrucment based on FPGA of the present invention
The clock multiplier and the clock phase-splitting design concept figure of Fig. 6 a kind of time interval measuring instrucment based on FPGA of the present invention
Four design concept figure that counter is counted respectively minute phase clock of Fig. 7 a kind of time interval measuring instrucment based on FPGA of the present invention
Fig. 8 a kind of time interval measuring instrucment data processing and data transmission block diagram in FPGA of the present invention based on FPGA
The Control Software general flow chart of Fig. 9 a kind of time interval measuring instrucment based on FPGA of the present invention
The application software interface of Figure 10 a kind of time interval measuring instrucment based on FPGA of the present invention
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Fig. 1 is a kind of quantization delay method-hour hands phase-splitting of the raising Measurement Resolution of a kind of time interval measuring instrucment based on FPGA of the present invention.Accurately the method for measuring intervals of TIME comprises direct count method, interpolation method, time voltage transformation method etc.From the simple as far as possible angle of taking into account measuring accuracy simultaneously of structure, the present invention has adopted a kind of time interval measurement method based on delay line technique-quantization delay method.The quantization delay method is along with the application of large scale integrated circuit in recent years grows up, and it is that signal or clock are done to measure respectively after the certain time-delay, thereby improves the method for measuring accuracy.The realization of quantization delay thought depends on the time-delay stability of delay unit, and its resolution depends on the time delay of unit delay unit.The ultimate principle of quantization delay method is " serial postpones, parallel counting ", and is different from the serial method of counting of conventional counter.Its implementation has two kinds, and a kind of is to allow signal pass through a series of delay unit, relies on the time-delay stability of delay unit, utilizes high steady clock that each time delayed signal is counted respectively, and this method is called as signal lag; A kind of is that enable clock passes through a series of delay unit, utilizes the clock of respectively delaying time that signal is counted respectively and does data processing again, and this method is called as the clock phase-splitting, as Fig. 1.Signal lag and clock phase-splitting are identical at root, and just implementation method is slightly different, and sometimes in order to realize higher resolution, and two kinds of methods also are combined and are used in the system when surveying.The present invention considers from design and use scope aspect, has adopted hour hands phase-splitting technology.
Fig. 2 is the level Four clock phase-splitting sequential chart of a kind of time interval measuring instrucment based on FPGA of the present invention, the 250MHz clock frequency is postponed through level Four, 90 ° of every grade of phase lags, be all to be every grade of time delay 1ns, single with a clock CLK1 during to the time interval measurement of initial stop signal, remember 4 clock period, the result who obtains is 16ns, and resolution is 4ns.If adopt clock phase-splitting technology, because the clock number of remembering from CLK1 to CLK3 is 4, CLK4 remembers that the clock number is 3, and available result is 12ns+1ns * 3=15ns, and resolution is 1ns, and this is actually Measurement Resolution has been improved 4 times.
Device as delay unit can be passive lead, active gate device or other circuit.Wherein, the time delay of lead (coaxial cable) is shorter, can realize delay, but, need numerous tap in order to realize high-acruracy survey near light velocity propagation, thereby circuit is huge, make this technology can't promote in early days, along with development of semiconductor, the particularly development of large scale integrated circuit, this method is transplanted on the integrated circuit, is just promoted rapidly.The time delay of gate circuit is longer relatively.Along with the fast development of electronic technology, have the people Counter Design in ASIC, realize Direct Digital coding, but its cost is very high to the time.The appearing as us new selection be provided of much relatively inexpensive large scale integrated circuit.Deadline of the present invention main change-over circuit at interval is exactly again to realize in the field programmable gate array (FPGA).
Fig. 3 is the hardware block diagram of a kind of time interval measuring instrucment based on FPGA of the present invention.Precise time-time-interval gauge systems structure adopts typical virtual instrument structure.Virtual instrument generally is made up of the hardware components of finishing data acquisition function and the software section of finishing data analysis function.Hardware components is generally various forms of data acquisition equipments, is behind the electric signal in the input computing machine with the various forms of conversion of signals that collect.Computing machine is realized reading of data from each class interface of computing machine by software, and realizes the analyzing and processing process of signal result being shown with software.The hardware foundation of precise time-time-interval measuring instrument is exactly a data collecting card based on the PXI interface, and structure as shown in Figure 3.Pulse signal input to be measured is after signal condition is sent into the FPGA module converts, and the data after the conversion are delivered to interface chip PLX9054, pass to PC through the PXI bus, and wait software is made post-processed.
Fig. 4 is the software architecture diagram of a kind of time interval measuring instrucment based on FPGA of the present invention.Wherein finish data-interface function by hardware and software based on the hardware drive program of WinDriver developing instrument, finish the configuration of hardware and the functions such as conversion of data based on the data processor of VB developing instrument, finish the functions such as demonstration of process user incident and measurement result based on the user interface program of VB.Because a lot of work of measuring system is all given computing machine and finished, thereby not only the intelligent degree and the extensibility of system improve, and She Ji complexity and design cycle all reduce greatly simultaneously.
Fig. 5 is the front end signal conditioning structured flowchart of a kind of time interval measuring instrucment based on FPGA of the present invention.Signal attenuation is finished in front end signal conditioning unit, clamper, and amplitude compares and the level conversion function, and its structured flowchart is as shown in Figure 5.Amplitude fading adopts resistance-capacitance network to realize, the amplitude clamper adopts fast diode to realize that comparer is selected the quick comparer MAX9602 of the voltage of MAXIM company for use, to consider the invalid signals that removes less than threshold voltage.MAX9602 is the PECL comparer of four-way, and the transmission delay of 500ps and precision can reach 30ps, also has Latch in addition and enables and can recall to stagnant function.The Latch control function can realize the tracking of operating and keep function, return the swing that stagnant function can be eliminated The noise and can reduce input signal.The threshold voltage of comparer is provided by resistor network dividing potential drop or AD5235, and AD5235 is the two-channel digital potentiometer that AD company produces, and its setting is controlled by interface by software.Adopt the threshold voltage that AD5235 can online adjusting comparer, easy to use flexibly, but can increase circuit complexity; Adopt resistor network to regulate the threshold voltage of comparer, but simplicity of design is reliable by changing resistance or voltage reference size.The actual conditions of consider using, the use occasion that needs online change threshold voltage seldom so adopt resistor network to realize among the design.
Fig. 6 is a kind of clock multiplier and the clock phase-splitting design concept figure of time interval measuring instrucment in QuartusII based on FPGA of the present invention.The present invention realizes that the approach of main time interval measurement function is to utilize FPGA to research and develop special chip voluntarily.FPGA can adopt the EP1C6Q240C6 of the Cylone of altera corp series, embedded memory, and Clock management is convenient and cost performance is high.The design software of FPGA has utilized the QuartusII of altera corp.We adopt 20MHz high stability constant-temperature crystal oscillator, and utilize two phaselocked loops (PLL) among the FPGA that the clock frequency frequency multiplication is arrived 320MHz, divide CLK1, CLK2, CLK3, CLK4 four tunnel outputs with clock, every road phase differential is 90 °, and four fixed delay amount sums just cover a clock period.Direct census can make Measurement Resolution reach 3.125ns.
Fig. 7 is a kind of four the design concept figures that counter to minute phase clock respectively count of time interval measuring instrucment in QuartusII based on FPGA of the present invention.Utilize clock to divide phase method, utilize 44 digit counters, CLK1 after the frequency multiplication, CLK2, this four road clock of CLK3, CLK4 independently (are about to the pulse width that the initial stop pulse time interval shows as timechannel1 to same time interval timechannel1, this rising edge of a pulse is synchronous with the start signal rising edge, negative edge and stop pulse rising edge are synchronous) counting, utilize clock to divide phase method can make Measurement Resolution reach 0.78125ns.
Fig. 8 is a kind of time interval measuring instrucment data processing and data transmission block diagram in FPGA based on FPGA of the present invention.The present invention stops channel signal with 8 the tunnel and be divided into 16 the tunnel in the front end signal modulate circuit for reducing the circuit shake, and FPGA is actually 16 tunnel stop signals that receive are carried out independent processing.Initial channel signal with respectively stop at first being treated to time interval pulse after channel signal enters FPGA by both rising edges, send into 32 set of counters counting together respectively with stop signal again, every group comprises 1 32 coarse counter and 44 thin counters, so the data of set of counters output are 48.One-shot measurement comprises 16 time interval datas and 16 stop pulse width datas, this time data of 32 48 is split 192 8 bit data and is mapped among the RAM and stored by sequence of addresses in address mapping unit, by the local bus of FPGA and interface chip PLX9054, realize local data communication according to the PLX9054 interface protocol.In the native system, local data bus and address bus all are 8.
Fig. 9 is a kind of precise time-time-interval measuring instrument Control Software general flow chart based on FPGA of the present invention.Control Software is developed under based on the framing program under the VB, the built-in function visit bottom hardware that provides by driver, the deadline at interval and the collection of pulse width data, and the implementation algorithm program write the operation of control system.Major function has data sampling, triggers interruption, the importing and exporting of System self-test, data.Wherein:
Data sampling: the Plx9054_ReadByte function reading of data of utilizing WinDriver to provide, deposit data in array, to be calculated according to algorithm, the time interval data or the pulse width that calculate are presented in the form.
Trigger and interrupt: enable interrupt function, hardware produces interruption at every turn, interrupts being called automatically by the WinDriver kernel, handles in the routine at interrupt function and calls the data sampling function.
System self-test: measuring system is detected, hardware is sent self-test signal, hardware system is carried out self-checking function and the self check data is returned Control Software after receiving this signal.
Importing and exporting of data: the importing of data is that all data importings of this collection are also preserved in electrical form excel, and the derivation of data is to be presented in the active sheet from existing excel file derived data.
Figure 10 is a kind of precise time-time-interval measuring instrument application software interface based on FPGA of the present invention.Be divided into time interval measurement, pulse width measuring and calibration value are provided with three tab.The time interval measurement tab as shown in figure 10.The pulse width measuring tab is the interface basically identical therewith, all comprises channel position, root mean square σ value, maximal value, minimum value and each time measured value, measured value can show on the interface 10 times, after measurement surpasses 10 times, the 11st time data will cover the 1st time data, and the rest may be inferred.The order of passage is relevant with the order that integrated circuit board inserts PXI cabinet expansion slot, and the passage number of different integrated circuit boards is distinguished with different colours, utilizes scroll bar can show later passage No. 35.
Claims (2)
1. time interval measuring instrucment based on FPGA, it is characterized in that: described time interval measuring instrucment is formed virtual instrument by hardware system and Control Software, wherein hardware system comprises integrated circuit board and the PXI system that is used for time interval measurement, integrated circuit board is the core of time interval measurement with FPGA, and integrated circuit board is nursed one's health unit, time/Date Conversion Unit, data interface unit by front end signal and formed; The Control Software that is mounted on the PXI system comprises with Windriver to be the driver of development platform and to be the development platform control program with VB.
2. the time interval measuring instrucment based on FPGA according to claim 1 is characterized in that: adopt frequency multiplication of phase locked loop and clock phase-splitting technology in described FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810046525A CN101520640A (en) | 2008-11-08 | 2008-11-08 | Time interval measuring instrument based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810046525A CN101520640A (en) | 2008-11-08 | 2008-11-08 | Time interval measuring instrument based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101520640A true CN101520640A (en) | 2009-09-02 |
Family
ID=41081277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810046525A Pending CN101520640A (en) | 2008-11-08 | 2008-11-08 | Time interval measuring instrument based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101520640A (en) |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976037A (en) * | 2010-11-29 | 2011-02-16 | 北京一朴科技有限公司 | Method and device for measuring time intervals of repeated synchronous interpolation simulation |
| CN102243474A (en) * | 2011-07-08 | 2011-11-16 | 四川省绵阳西南自动化研究所 | High-value pulse interval data acquisition device |
| CN102346236A (en) * | 2011-06-21 | 2012-02-08 | 电子科技大学 | Time parameter measurement system |
| CN102736511A (en) * | 2011-04-06 | 2012-10-17 | 中国科学院高能物理研究所 | Time measurement system and time measurement method |
| CN102914419A (en) * | 2012-09-25 | 2013-02-06 | 中国科学院安徽光学精密机械研究所 | Precision measurement system for relative time difference of two-channel feedback signals |
| CN103092060A (en) * | 2013-02-08 | 2013-05-08 | 西安电子科技大学 | Time interval measuring system and time interval measuring method which are based on field programmable gate array (FPGA) |
| CN103364819A (en) * | 2013-06-27 | 2013-10-23 | 南京邮电大学 | High-precision coincidence counter implementation method based on FPGA (field programmable gata array) |
| CN103425043A (en) * | 2013-09-11 | 2013-12-04 | 安徽问天量子科技股份有限公司 | High-precision time-to-digital converter based on USB |
| CN103472712A (en) * | 2013-09-26 | 2013-12-25 | 中国科学技术大学 | High-precision and high-integrality time-digital converter based on FPGA (Field Programmable Gate Array), and implementation method |
| CN103869123A (en) * | 2012-12-14 | 2014-06-18 | 北京普源精电科技有限公司 | Oscilloscope with pulse width measurement function |
| CN104035320A (en) * | 2014-06-16 | 2014-09-10 | 沈阳东软医疗系统有限公司 | System and method for implementing time interval measurement |
| CN104133367A (en) * | 2014-07-07 | 2014-11-05 | 中国电子科技集团公司第四十一研究所 | Circuit and method for extracting time interval parameters of clock signals to be measured |
| CN104569620A (en) * | 2014-12-30 | 2015-04-29 | 西安奇维科技股份有限公司 | Method for collecting high-precision digital pulse width |
| CN106019924A (en) * | 2016-07-21 | 2016-10-12 | 中国地震局地震研究所 | FPGA-based counting type high-precision time interval measuring system |
| CN106501621A (en) * | 2016-09-22 | 2017-03-15 | 珠海格力节能环保制冷技术研究中心有限公司 | pulse width acquisition method |
| CN108732912A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of measured signal edging trigger |
| CN108736885A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of phase-locked loop clock edging trigger |
| CN108768388A (en) * | 2018-05-28 | 2018-11-06 | 哈尔滨工业大学 | The clock phase-splitting method that phaselocked loop clock edge of connecting triggers |
| CN110488595A (en) * | 2019-08-29 | 2019-11-22 | 北京理工大学 | A kind of time-to-digit converter for the ranging of the frequency modulated continuous wave radar time difference |
| CN111665708A (en) * | 2020-06-10 | 2020-09-15 | 中国测试技术研究院电子研究所 | Sweep frequency time detection method based on FPGA circuit |
| CN112631114A (en) * | 2019-09-24 | 2021-04-09 | 精工爱普生株式会社 | Circuit device, physical quantity measuring device, electronic apparatus, and moving object |
| CN112824983A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN113064213A (en) * | 2021-03-10 | 2021-07-02 | 欧姆龙(上海)有限公司 | Light receiving device and photoelectric sensor |
| CN114326358A (en) * | 2021-12-20 | 2022-04-12 | 中国科学院上海光学精密机械研究所 | Multi-chain parallel segmentation high-precision FPGA time-to-digital conversion method |
-
2008
- 2008-11-08 CN CN200810046525A patent/CN101520640A/en active Pending
Cited By (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976037A (en) * | 2010-11-29 | 2011-02-16 | 北京一朴科技有限公司 | Method and device for measuring time intervals of repeated synchronous interpolation simulation |
| CN102736511A (en) * | 2011-04-06 | 2012-10-17 | 中国科学院高能物理研究所 | Time measurement system and time measurement method |
| CN102736511B (en) * | 2011-04-06 | 2014-08-20 | 中国科学院高能物理研究所 | Time measurement system and time measurement method |
| CN102346236A (en) * | 2011-06-21 | 2012-02-08 | 电子科技大学 | Time parameter measurement system |
| CN102346236B (en) * | 2011-06-21 | 2013-06-05 | 电子科技大学 | Time parameter measurement system |
| CN102243474A (en) * | 2011-07-08 | 2011-11-16 | 四川省绵阳西南自动化研究所 | High-value pulse interval data acquisition device |
| CN102914419A (en) * | 2012-09-25 | 2013-02-06 | 中国科学院安徽光学精密机械研究所 | Precision measurement system for relative time difference of two-channel feedback signals |
| CN102914419B (en) * | 2012-09-25 | 2016-03-16 | 中国科学院安徽光学精密机械研究所 | The accurate measuring systems of two-way feedback signal relative time error |
| CN103869123A (en) * | 2012-12-14 | 2014-06-18 | 北京普源精电科技有限公司 | Oscilloscope with pulse width measurement function |
| CN103092060B (en) * | 2013-02-08 | 2015-04-08 | 西安电子科技大学 | Time interval measuring system and time interval measuring method which are based on field programmable gate array (FPGA) |
| CN103092060A (en) * | 2013-02-08 | 2013-05-08 | 西安电子科技大学 | Time interval measuring system and time interval measuring method which are based on field programmable gate array (FPGA) |
| CN103364819A (en) * | 2013-06-27 | 2013-10-23 | 南京邮电大学 | High-precision coincidence counter implementation method based on FPGA (field programmable gata array) |
| CN103364819B (en) * | 2013-06-27 | 2015-12-02 | 南京邮电大学 | A kind of high precision coincide counter implementation method based on FPGA |
| CN103425043A (en) * | 2013-09-11 | 2013-12-04 | 安徽问天量子科技股份有限公司 | High-precision time-to-digital converter based on USB |
| CN103472712A (en) * | 2013-09-26 | 2013-12-25 | 中国科学技术大学 | High-precision and high-integrality time-digital converter based on FPGA (Field Programmable Gate Array), and implementation method |
| CN103472712B (en) * | 2013-09-26 | 2016-01-27 | 中国科学技术大学 | A kind of high precision high integration time-to-digit converter based on FPGA and implementation method |
| CN104035320A (en) * | 2014-06-16 | 2014-09-10 | 沈阳东软医疗系统有限公司 | System and method for implementing time interval measurement |
| CN104133367A (en) * | 2014-07-07 | 2014-11-05 | 中国电子科技集团公司第四十一研究所 | Circuit and method for extracting time interval parameters of clock signals to be measured |
| CN104133367B (en) * | 2014-07-07 | 2017-02-01 | 中国电子科技集团公司第四十一研究所 | Circuit and method for extracting time interval parameters of clock signals to be measured |
| CN104569620A (en) * | 2014-12-30 | 2015-04-29 | 西安奇维科技股份有限公司 | Method for collecting high-precision digital pulse width |
| CN106019924A (en) * | 2016-07-21 | 2016-10-12 | 中国地震局地震研究所 | FPGA-based counting type high-precision time interval measuring system |
| CN106501621A (en) * | 2016-09-22 | 2017-03-15 | 珠海格力节能环保制冷技术研究中心有限公司 | pulse width acquisition method |
| CN108768388B (en) * | 2018-05-28 | 2022-03-15 | 哈尔滨工业大学 | Clock phase splitting method triggered by serial phase-locked loop clock edge |
| CN108736885B (en) * | 2018-05-28 | 2022-04-12 | 哈尔滨工业大学 | Phase-locked loop clock edge triggered clock phase-splitting method |
| CN108768388A (en) * | 2018-05-28 | 2018-11-06 | 哈尔滨工业大学 | The clock phase-splitting method that phaselocked loop clock edge of connecting triggers |
| CN108736885A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of phase-locked loop clock edging trigger |
| CN108732912A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of measured signal edging trigger |
| CN110488595A (en) * | 2019-08-29 | 2019-11-22 | 北京理工大学 | A kind of time-to-digit converter for the ranging of the frequency modulated continuous wave radar time difference |
| CN112631114A (en) * | 2019-09-24 | 2021-04-09 | 精工爱普生株式会社 | Circuit device, physical quantity measuring device, electronic apparatus, and moving object |
| CN112824983A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN112824983B (en) * | 2019-11-20 | 2022-08-19 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN111665708A (en) * | 2020-06-10 | 2020-09-15 | 中国测试技术研究院电子研究所 | Sweep frequency time detection method based on FPGA circuit |
| CN111665708B (en) * | 2020-06-10 | 2022-05-03 | 中国测试技术研究院电子研究所 | Sweep frequency time detection method based on FPGA circuit |
| CN113064213A (en) * | 2021-03-10 | 2021-07-02 | 欧姆龙(上海)有限公司 | Light receiving device and photoelectric sensor |
| CN114326358A (en) * | 2021-12-20 | 2022-04-12 | 中国科学院上海光学精密机械研究所 | Multi-chain parallel segmentation high-precision FPGA time-to-digital conversion method |
| CN114326358B (en) * | 2021-12-20 | 2024-05-17 | 中国科学院上海光学精密机械研究所 | Multi-chain parallel segmentation high-precision FPGA time-digital conversion method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101520640A (en) | Time interval measuring instrument based on FPGA | |
| CN106850115B (en) | A kind of Multi-channel data acquisition synchronization system and method | |
| CN201331680Y (en) | Time interval measuring instrument based on FPGA | |
| CN101893464B (en) | High-precision and fast pulse metering method | |
| CN100468060C (en) | Equal observations method and measuring device of rotary table rate | |
| CN101976037B (en) | Method and device for measuring time intervals of repeated synchronous interpolation simulation | |
| CN104254761B (en) | Sensor time synchronization | |
| CN105676198A (en) | Echo pulse delay generating device for pulse type radar test | |
| CN105760330B (en) | A kind of channelized frequencies Acquisition Circuit with APB interface | |
| CN100510640C (en) | Adjustable sample-taking velocity high speed high-accuracy data collection card | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN106126384B (en) | A kind of method and device of acquisition performance monitoring unit PMU event | |
| CN101435842A (en) | Multifunctional integrated test system | |
| CN201421365Y (en) | Portable vibration measuring and analyzing instrument | |
| CN200993665Y (en) | Small digitalized prase-comparing measuring device | |
| CN106501605A (en) | One kind is than phase device | |
| CN101256210A (en) | Three-phase electric energy meter based on NIOS II microprocessor | |
| CN101871976A (en) | Power clock detecting device | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| CN108736885A (en) | The clock phase-splitting method of phase-locked loop clock edging trigger | |
| CN203929885U (en) | Based on FPGA etc. precision frequency testing system | |
| CN203811718U (en) | Intelligent diagnostic instrument of energy saving of special-line user | |
| CN101556325A (en) | Method for quickly verifying electric energy error | |
| CN205384320U (en) | Photoelectric detection means | |
| CN202720273U (en) | High-precision phase difference detection device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090902 |