CN102736511B - Time measurement system and time measurement method - Google Patents
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Abstract
The invention relates to a time measurement system, which comprises a start signal fine time measurement unit, a timing signal fine time measurement unit, a rough time measurement unit and a time calculation unit, wherein the start signal fine time measurement unit comprises a delay chain, a plurality of registers and a data converter; one end of the delay chain receives a start signal; outputs of delay units receiving the start signal are sequentially changed into second levels; each register reads and stores an output value of the corresponding delay unit at the rising edge of a first clock when the start signal is input; the data converter converts the stored data into time data to acquire start signal fine time; the timing signal fine time measurement unit is used for acquiring timing signal fine time; the working theory of the timing signal fine time measurement unit is similar to that of the start signal fine time measurement unit; the rough time measurement unit is used for measuring rough time under the driving of a field programmable gate array (FPGA) clock signal; and the time calculation unit is used for subtracting the timing signal fine time from a sum of the rough time and the start signal fine time to acquire time to be measured. According to the system, the precision and the instantaneity of time measurement are improved.
Description
Technical field
The application relates to a kind of measuring system, relates in particular to a kind of time measurement system and method.
Background technology
Split-second precision measuring technique all needs to be employed at the numerous areas of modern science and technology, such as telecom communication, laser ranging, satnav etc., especially the application in the each field of physics is more extensive, all be unable to do without split-second precision measuring technique fields such as atomic nuclear physics, high-energy physics, medical imaging physics.Time measurement generally comprises time examination and time figure conversion (Time-To-Digital Converter, TDC) two parts.
High precision TDC mainly contains ASIC (Application Specific Integrated Circuit at present, special IC), special TDC chip, FPGA (Field Programmable Gate Array, field programmable gate array) etc. multiple implementation, due to the reason of the aspect such as R&D costs and R&D cycle, the scheme that realizes TDC based on ASIC is very limited, and there is again the low and inconvenient problem with use of integrated level in special TDC chip.
Utilizing FPGA to carry out time measurement is a kind of newer Method Of Time Measurement, compares the implementation of ASIC and special TDC chip, and the method can reduce complicacy and the cost of measuring system.In patented claim CN1719353A, set forth the TDC device that a kind of FPGA of utilization realizes.The principal feature of this patented claim is to measure the meticulous time with FPGA internal latency line, multibit adder or look-up table LUT, the counter that utilizes two inversion clocks to drive is measured the thick time, and realizes meticulous time encoding by binary search and pipelining.But also there is following several respects defect in this technology, causes the practical application that is difficult to realize this technology.
1. this patented claim is not measured start time, and because start signal is provided by outside conventionally, with the not homology of high-frequency clock that TDC temporal interpolation uses, the phase place between the rising edge of start signal and clock forward position is uncertain.Therefore, to start signal, measurement does not greatly reduce the practicality of existing time measurement technology.
2. this patented claim adopts carry line, the LUT (Look-Up-Table of FPGA inside, look-up table), multibit adder etc. builds delay chain, constructed delay chain is even not, will have a strong impact on the precision of time measurement and delay chain performance is not good.
This patented claim realizes time encoding by binary search and pipelining, need to expend a large amount of fpga logic resources, and need to expend the longer time and could export measurement result.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to the basic comprehension about some aspect of the present invention is provided.Should be appreciated that this general introduction is not about exhaustive general introduction of the present invention.It is not that intention is determined key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only that the form of simplifying provides some concept, using this as the preorder in greater detail of discussing after a while.
A fundamental purpose of the present invention is to provide a kind of practical and time measurement precise time measuring system and method.
According to an aspect of the present invention, a kind of time measurement system, in order to measure the time to be measured, comprising:
The meticulous time measuring unit of start signal, comprise the first delay chain being in series by multiple the first delay cell, multiple the first registers and the first data converter, in the time there is no signal input, each the first delay cell output is the first level, each the first register and the corresponding connection of each the first delay cell, the first data converter is connected to each the first register, one end of the first delay chain is used for receiving start signal, make the output of the first delay cell that receives start signal become successively second electrical level, each the first register is used for the output valve of the first delay cell that reads connection corresponding to it in the time inputting first clock forward position of the reference signal after start signal and the data that read is preserved, the first data converter is converted to time data to obtain the meticulous time of start signal for the data that each the first register is preserved,
The meticulous time measuring unit of timing signal, comprise the second delay chain being in series by multiple the second delay cell, multiple the second registers and the second data converter, in the time there is no signal input, each the second delay cell output is the first level, each the second register and the corresponding connection of each the second delay cell, the second data converter is connected to each the second register, one end of the second delay chain is used for receiving timing signal, make the output of the second delay cell that receives timing signal become successively second electrical level, each the second register read during for first clock forward position of reference signal after timing signal is inputted the second delay chain connection corresponding to it the second delay cell output valve and the data that read are preserved, the second data converter is converted to time data to obtain the meticulous time of timing signal for the data that each the second register is preserved,
Thick time measuring unit, for measuring the thick time, the thick time is the time period between first clock period to first clock period of the reference signal after timing signal forward position of the reference signal after start signal forward position; And
Time calculating unit, for deducting the meticulous time of timing signal to obtain the time to be measured by thick time and the meticulous time sum of start signal.
According to an aspect of the present invention, a kind of Method Of Time Measurement, in order to measure the time to be measured, comprising:
One end of the first delay chain being in series by multiple the first delay cell receives start signal, make the output of the first delay cell that receives start signal become successively second electrical level, when first clock forward position of reference signal after start signal is inputted the first delay chain by correspondence be connected to the first delay cell each the first delay cell of multiple the first register reads output valve and the data that read are preserved, preserved data are converted to time data to obtain the meticulous time of start signal, wherein in the time there is no signal input, each the first delay cell output is the first level,
One end of the second delay chain being in series by multiple the second delay cell receives timing signal, make the output of the second delay cell that receives timing signal become successively second electrical level, when first clock forward position of reference signal after timing signal is inputted the second delay chain by correspondence be connected to the second delay cell each the second delay cell of multiple the second register reads output valve and the data that read are preserved, preserved data are converted to time data to obtain the meticulous time of timing signal, wherein in the time there is no signal input, each the second delay cell output is the first level,
Measure the thick time, the thick time is the time period between first clock period to first clock period of the reference signal after timing signal forward position of the reference signal after start signal forward position; And
Meticulous start signal time and thick time sum are deducted to the meticulous time of timing signal to obtain the time to be measured.
The present invention provides reference point by introducing the measurement that start signal is the time to be measured, and adopt interpolative delay chain to the time between start signal rising edge and first rising edge clock thereafter and timing signal forward position and the time between first rising edge clock is carried out meticulous measurement thereafter, the bigness scale amount being combined under clock signal driving is obtained the accurate time to be measured, solve the not high problem of the clock signal measuring accuracy that homology does not cause of start signal and fpga chip inside, introduced the start signal practicality that promotes time measurement as a reference point simultaneously.
Brief description of the drawings
Below with reference to the accompanying drawings illustrate embodiments of the invention, can understand more easily above and other objects, features and advantages of the present invention.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characterictic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the block scheme of time measurement system preferred embodiments of the present invention.
Fig. 2 is the emulation schematic diagram of reference clock signal, start signal and timing signal.
Fig. 3 is the schematic diagram when output data of delay chain are carried out to segment lookup.
Fig. 4 is the process flow diagram of Method Of Time Measurement preferred embodiments of the present invention.
Embodiment
Embodiments of the invention are described with reference to the accompanying drawings.The element of describing in an accompanying drawing of the present invention or a kind of embodiment and feature can combine with element and feature shown in one or more other accompanying drawing or embodiment.It should be noted that for purposes of clarity, in accompanying drawing and explanation, omitted expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and processing.
Please refer to Fig. 1, the time measurement system of the embodiment of the present invention is in order to measure the time to be measured, and it comprises thick time measuring unit 10, the meticulous time measuring unit 20 of start signal, the meticulous time measuring unit 30 of timing signal and time calculating unit 40.Time measurement system in the embodiment of the present invention can be integrated in fpga chip.
Alternatively, thick time measuring unit 10 is measured the thick time under the driving of the clock signal C LOCK of fpga chip.Alternatively, thick time measuring unit 10 can be the clock counter in fpga chip.
Time T to be measured is the mistiming between timing moment and initial time, and for example, with reference to figure 2, time T to be measured is the mistiming between timing signal Tstop and start signal Tstart to be measured.The time T to be measured of the embodiment of the present invention can be calculated by thick time T c, the meticulous time T f1 of start signal and the meticulous time T f2 of timing signal.
Thick time T c refers to the time recording by for example, time cycle counting to reference signal (, the CLOCK signal in Fig. 1 and Fig. 2).As shown in Figure 2, thick time T c is the mistiming between thick initial time Tc1 and thick timing moment Tc2.Thick initial time Tc1 refers to the time that starts timing in the time carrying out thick time measurement, and thick timing moment Tc2 refers to the time that stops timing while carrying out thick time measurement.In an example, as shown in Figure 2, thick time T c is that the forward position of first clock period of the reference signal after start signal Tstart forward position is to the time period between the forward position of first clock period of the reference signal after timing signal Tstop forward position, wherein, thick initial time Tc1 is the forward position of first clock period of start signal Tstart forward position reference signal afterwards.Thick timing moment Tc2 is the forward position of first clock period of the reference signal after timing signal Tstop forward position.
The meticulous time T f1 of start signal is the absolute value of the mistiming between thick initial time Tc1 and initial time, and the meticulous time T f2 of timing signal is the absolute value of the mistiming between timing moment and thick timing moment Tc2.In Fig. 2, the meticulous time T f1 of start signal refers to the absolute value of the mistiming between first clock forward position and the start signal Tstart forward position of the reference signal behind start signal Tstart forward position; The meticulous time T f2 of timing signal refers to the absolute value of the mistiming between timing signal Tstop forward position and first rising edge clock thereafter.Meticulous time of start signal and meticulous time of timing signal are all less than a clock period, therefore can not be recorded by clock counter.
So the time T to be measured of the embodiment of the present invention can, by thick time T c being added to the meticulous time T f1 of start signal, then deduct the meticulous time T f2 of timing signal and calculate.
In an example, reference signal can adopt the clock signal of FPGA inside.
Alternatively, the meticulous time measuring unit 20 of start signal can comprise the first delay chain being in series by multiple the first delay cell, multiple the first register and the first data converter.Each the first register be connected to form first register array corresponding to each the first delay cell, the first data converter is connected to each the first register.Alternatively, the first delay cell is the delay cell in fpga chip, i.e. carry unit (as MUXCY).Each the first delay cell can be connected in series by carry line.
The meticulous time measuring unit 20 of start signal is for receiving start signal Tstart, and this start signal Tstart can be provided by outside, also can produce by the time measurement system of embodiments of the invention is inner.In the time there is no signal input, each the first delay cell output is the first level (being for example low level), one end of the first delay chain receives start signal Tstart, makes the output of the first delay cell that respectively receives start signal Tstart become successively second electrical level (being for example high level).At thick initial time Tc1, namely, in Fig. 1 of the present embodiment, when first rising edge clock of CLOCK signal after start signal Tstart inputs the first delay chain, the output valve of the first delay cell of each the first register read connection corresponding to it is also preserved the data that read.The data that the first data converter is preserved each the first register are converted to time data, obtain the meticulous time T f1 of start signal.
Alternatively, the meticulous time measuring unit 30 of timing signal also comprises the second delay chain being in series by multiple the second delay cell, multiple the second register and the second data converter, the structure of the meticulous time measuring unit 20 of its structure and start signal is similar, each the second register be connected to form second register array corresponding to each the second delay cell, the second data converter is connected to each the second register.
It is similar that the meticulous time measuring unit 30 of timing signal obtains the principle that the meticulous time T f2 of timing signal and the meticulous time measuring unit 20 of start signal obtain the meticulous time T f1 of start signal, one end of the second delay chain is used for receiving timing signal Tstop, makes the output of the second delay cell that receives timing signal Tstop become successively second electrical level.At thick timing moment Tc2, namely, in Fig. 1 of the present embodiment, when first rising edge clock of CLOCK signal after timing signal is inputted the second delay chain, the output valve of the second delay cell of each the second register read connection corresponding to it is also preserved the data that read, and the second data converter is converted to time data to obtain the meticulous time T f2 of timing signal for the data that each the second register is preserved.
Alternatively, in embodiments of the invention, each the first register is the different time data of correspondence respectively, and each the second register is also distinguished corresponding different time datas.First, second data converter is searched the second electrical level data that first, second register array is stored, the terminal transmitting in the first or second delay chain of correspondence to search start signal Tstart or timing signal Tstop, and export the time data corresponding with this terminal by coding, just can obtain the meticulous time T f1 of start signal or the meticulous time T f2 of timing signal.
Alternatively, in embodiments of the invention, utilize segment lookup method to search the second electrical level data that first, second register array is stored.Figure 3 shows that example describes, the method for segment lookup is as follows:
Step 1: the output of the first or second register array is divided into successively to multiple groups from most significant digit to lowest order, as the group a in Fig. 3, b, c, d, the afterbody that wherein the most significant digit a6 of the highest group of a is delay chain, the stem that the lowest order d1 of minimum group of d is delay chain, first the lowest order a1 of the highest group of a of judgement, if the lowest order a1 of the highest group of a is second electrical level, illustrate that signal has transferred to herein, down search successively the terminal of start signal or timing signal transmission from the most significant digit a6 of the highest group of a, start down to search the position of first second electrical level from the most significant digit a6 of the highest group of a.
Step 2: if the lowest order a1 of the highest group of a is the first level, illustrate that signal not yet transfers to herein, the lowest order b1 of judgement time high group of b, if the lowest order b1 of inferior high group of b is second electrical level, starts down to search the position of first second electrical level from the most significant digit b6 of inferior high group of b.
Step 3: by that analogy, until find the position of first second electrical level, with the terminal that finds start signal or timing signal to transmit in the first or second delay chain of correspondence, the corresponding time data of terminal that the first or second data converter acquisition start signal Tstart or timing signal Tstop are transmitted in the first or second delay chain of correspondence, obtains the meticulous time T f1 of start signal or the meticulous time T f2 of timing signal.
Time calculating unit 40 calculates time T to be measured according to the thick measured measured meticulous time T f1 of start signal and the measured meticulous time T f2 of timing signal of the meticulous time measuring unit 30 of timing signal of the meticulous time measuring unit 20 of thick time T c, start signal of time measuring unit 10.In embodiments of the invention, time calculating unit 40 deducts the meticulous time T f2 of timing signal to obtain time T to be measured by meticulous start signal time T f1 with thick time T c sum.
Please refer to Fig. 4, the preferred embodiments of Method Of Time Measurement of the present invention comprises the following steps:
Step S1: one end of the first delay chain receives start signal Tstart, make the output of the delay cell that receives start signal Tstart become successively second electrical level, when first clock forward position of the reference signal of each the first register after start signal Tstart inputs the first delay chain, read connection corresponding to it the first delay cell output valve and the data that read are preserved, the data that data converter is preserved each register are converted to time data, obtain the meticulous time T f1 of start signal.The meticulous time T f1 of start signal is the time between start signal Tstart rising edge and first rising edge clock of reference signal thereafter.
Step S2: one end of the second delay chain receives timing signal Tstop, make the output of the second delay cell that receives timing signal Tstop become successively second electrical level, when first clock forward position of the reference signal of each the second register after timing signal Tstop inputs the second delay chain, read connection corresponding to it the second delay cell output valve and the data that read are preserved, the data that data converter is preserved each the second register are converted to time data, obtain the meticulous time T f2 of timing signal.The meticulous time T f2 of timing signal is the time between timing signal Tstop forward position and first rising edge clock of reference signal thereafter.
Step S3: thick time measuring unit 10 is measured the thick time.The thick time is first clock period of the reference signal after start signal Tstart forward position to arrive the time period between first clock period of reference signal afterwards of timing signal Tstop forward position.Alternatively, reference signal can be the clock signal C LOCK at fpga chip.
Step S4: time calculating unit 40 calculates time T to be measured according to the meticulous time T f2 of timing signal obtaining in the meticulous time T f1 of start signal obtaining in the thick time T c, the step S1 that obtain in step S3 and step S2.In this step, time calculating unit 40 can deduct the meticulous time T f2 of timing signal to obtain time T to be measured with thick time T c sum by meticulous start signal time T f1.
Alternatively, in step S2 and S3, utilize segment lookup method to search the second electrical level data that first, second register array is stored, the terminal transmitting in the first or second delay chain of correspondence to search start signal Tstart or timing signal Tstop, and export the time data corresponding with this terminal by coding, just can obtain the meticulous time T f1 of start signal or the meticulous time T f2 of timing signal.Segment lookup method illustrates in the foregoing description, does not repeat them here.
In embodiments of the invention, provide reference point by introducing start signal for the measurement in timing moment, and adopt interpolative delay chain to the time between start signal forward position and first clock forward position thereafter and timing signal forward position and the time between first clock forward position is carried out meticulous measurement thereafter, the bigness scale amount being combined under clock signal driving is obtained the accurate time to be measured, solve the not high problem of the clock signal measuring accuracy that homology does not cause of start signal and fpga chip inside, introduce the start signal practicality that promotes time measurement as a reference point simultaneously.
Embodiments of the invention adopt the inner carry unit of fpga chip to build time delay chain, compare the delay chain that adopts totalizer, LUT etc. to build, and have the more uniform advantage of delay, have promoted accuracy and the reliability of time measurement.
Embodiments of the invention are by timing signal access delay chain to be measured, and reference clock signal access register array, only can realize thick time measurement by a clock counter, simple in structure.
Embodiments of the invention adopt segment lookup method to read the output state of each delay cell in delay chain, searching of serial combination to delay chain changed into the parallel search of multiple serial segmentations, the result that can obtain searching within the utmost point short time, the experiment proved that, segment lookup can draw the result of searching within a clock period, greatly reduce the use amount of fpga logic resource, and reduced the acquisition time of time data.
In equipment of the present invention and method, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decomposition and/or reconfigure and should be considered as equivalents of the present invention.The step that also it is pointed out that the above-mentioned series of processes of execution can order naturally following the instructions be carried out in chronological order, but does not need necessarily to carry out according to time sequencing.Some step can walk abreast or carry out independently of one another.Simultaneously, in the above in the description of the specific embodiment of the invention, describe and/or the feature that illustrates can be used in same or similar mode in one or more other embodiment for a kind of embodiment, combined with the feature in other embodiment, or substitute the feature in other embodiment.
Claims (6)
1. a time measurement system, in order to measure the time to be measured, comprising:
The meticulous time measuring unit of start signal, comprise the first delay chain being in series by multiple the first delay cell, multiple the first registers and the first data converter, in the time there is no signal input, each the first delay cell output is the first level, each the first register and the corresponding connection of each the first delay cell, the first data converter is connected to each the first register, one end of the first delay chain is used for receiving start signal, make the output of the first delay cell that receives described start signal become successively second electrical level, each the first register is used for the output valve of the first delay cell that reads connection corresponding to it in the time inputting first clock forward position of the reference signal after start signal and the data that read is preserved, the first data converter is converted to time data to obtain the meticulous time of start signal for the data that each the first register is preserved,
The meticulous time measuring unit of timing signal, comprise the second delay chain being in series by multiple the second delay cell, multiple the second registers and the second data converter, in the time there is no signal input, each the second delay cell output is the first level, each the second register and the corresponding connection of each the second delay cell, the second data converter is connected to each the second register, one end of the second delay chain is used for receiving timing signal, make the output of the second delay cell that receives described timing signal become successively second electrical level, each the second register read during for first clock forward position of reference signal after timing signal is inputted the second delay chain connection corresponding to it the second delay cell output valve and the data that read are preserved, the second data converter is converted to time data to obtain the meticulous time of timing signal for the data that each the second register is preserved,
Thick time measuring unit, for measuring the thick time, the described thick time is the time period between first clock period to first clock period of the reference signal after described timing signal forward position of the reference signal after described start signal forward position; And
Time calculating unit, for deducting the meticulous time of timing signal to obtain the described time to be measured by described thick time and the meticulous time sum of start signal;
Respectively corresponding different time data of each the first register, also corresponding different time data respectively of each the second register, the meticulous time measuring unit of described start signal or the meticulous time measuring unit of timing signal also specifically for:
The output of the each first or second register is divided into successively to multiple groups from most significant digit to lowest order, and wherein the most significant digit of the highest group is the afterbody of the first or second delay chain of correspondence, and the lowest order of minimum group is the stem of the first or second delay chain of correspondence;
Judge the level state of the lowest order of the highest group, if the lowest order of the highest group is second electrical level, start down to search the position of first second electrical level from the most significant digit of the highest group;
If the lowest order of the highest group is the first level, judge the level state of the lowest order of inferior high group, if the lowest order of inferior high group is second electrical level, start down to search the position of first second electrical level from the most significant digit of inferior high group; And
By that analogy, until find the position of first second electrical level, with the terminal that finds start signal or timing signal to transmit in the first or second delay chain of correspondence, the corresponding time data of terminal transmitting in the first or second delay chain of correspondence to obtain start signal or timing signal, thus meticulous time of described start signal or meticulous time of timing signal obtained.
2. time measurement system as claimed in claim 1, is characterized in that, described thick time measuring unit is the clock counter in field programmable gate array chip.
3. time measurement system as claimed in claim 1, it is characterized in that, each the first delay cell, the second delay cell are the carry unit in field programmable gate array chip, and each the first delay cell is connected in series by carry line, and each the second delay cell is connected in series by carry line.
4. a Method Of Time Measurement, in order to measure the time to be measured, comprising:
One end of the first delay chain being in series by multiple the first delay cell receives start signal, make the output of the first delay cell that receives start signal become successively second electrical level, when first clock forward position of reference signal after start signal is inputted the first delay chain by correspondence be connected to the first delay cell each the first delay cell of multiple the first register reads output valve and the data that read are preserved, preserved data are converted to time data to obtain the meticulous time of start signal, wherein in the time there is no signal input, each the first delay cell output is the first level,
One end of the second delay chain being in series by multiple the second delay cell receives timing signal, make the output of the second delay cell that receives timing signal become successively second electrical level, when first clock forward position of reference signal after timing signal is inputted the second delay chain by correspondence be connected to the second delay cell each the second delay cell of multiple the second register reads output valve and the data that read are preserved, preserved data are converted to time data to obtain the meticulous time of timing signal, wherein in the time there is no signal input, each the second delay cell output is the first level,
Measure the thick time, the described thick time is the time period between first clock period to first clock period of the reference signal after described timing signal forward position of the reference signal after described start signal forward position; And
Meticulous described start signal time and thick time sum are deducted to the meticulous time of described timing signal to obtain the described time to be measured;
Each the first register is the different time data of correspondence respectively, and each the second register is also distinguished corresponding different time datas, and the step of described meticulous time of measurement start signal or meticulous time of timing signal comprises respectively:
The output of the each first or second register is divided into successively to multiple groups from most significant digit to lowest order, and wherein the most significant digit of the highest group is the afterbody of the first or second delay chain of correspondence, and the lowest order of minimum group is the stem of the first or second delay chain of correspondence;
Judge the level state of the lowest order of the highest group, if the lowest order of the highest group is second electrical level, start down to search the position of first second electrical level from the most significant digit of the highest group;
If the lowest order of the highest group is the first level, judge the level state of the lowest order of inferior high group, if the lowest order of inferior high group is second electrical level, start down to search the position of first second electrical level from the most significant digit of inferior high group; And
By that analogy, until find the position of first second electrical level, with the terminal that finds start signal or timing signal to transmit in the first or second delay chain of correspondence, the corresponding time data of terminal transmitting in the first or second delay chain of correspondence to obtain start signal or timing signal, thus meticulous time of described start signal or meticulous time of timing signal obtained.
5. Method Of Time Measurement as claimed in claim 4, is characterized in that, the step of described thick time of measurement comprises by the clock counter in field programmable gate array chip measures the described thick time.
6. Method Of Time Measurement as claimed in claim 4, it is characterized in that, each the first delay cell, the second delay cell are the carry unit in field programmable gate array chip, and each the first delay cell is connected in series by carry line, and each the second delay cell is connected in series by carry line.
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| US9432009B2 (en) * | 2013-11-15 | 2016-08-30 | Arm Limited | Circuit delay monitoring apparatus and method |
| KR101565098B1 (en) | 2014-04-30 | 2015-11-02 | 한국항공우주연구원 | Apparatus for input time measurement of input signal |
| CN104035320B (en) * | 2014-06-16 | 2017-11-03 | 沈阳东软医疗系统有限公司 | A kind of system and method for realizing time interval measurement |
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