CN102736511B - Time measurement system and time measurement method - Google Patents

Abstract

The invention relates to a time measurement system, which comprises a start signal fine time measurement unit, a timing signal fine time measurement unit, a rough time measurement unit and a time calculation unit, wherein the start signal fine time measurement unit comprises a delay chain, a plurality of registers and a data converter; one end of the delay chain receives a start signal; outputs of delay units receiving the start signal are sequentially changed into second levels; each register reads and stores an output value of the corresponding delay unit at the rising edge of a first clock when the start signal is input; the data converter converts the stored data into time data to acquire start signal fine time; the timing signal fine time measurement unit is used for acquiring timing signal fine time; the working theory of the timing signal fine time measurement unit is similar to that of the start signal fine time measurement unit; the rough time measurement unit is used for measuring rough time under the driving of a field programmable gate array (FPGA) clock signal; and the time calculation unit is used for subtracting the timing signal fine time from a sum of the rough time and the start signal fine time to acquire time to be measured. According to the system, the precision and the instantaneity of time measurement are improved.

Description

Time measuring system and time measuring method

technical field

The present application relates to a measurement system, in particular to a time measurement system and method.

Background technique

High-precision time measurement technology needs to be applied in many fields of modern science and technology, such as telecommunications, laser ranging, satellite positioning, etc., especially in various fields of physics, such as nuclear physics, high-energy physics, medicine Fields such as image physics are inseparable from high-precision time measurement technology. Time measurement generally includes two parts: time discrimination and time-to-digital conversion (Time-To-Digital Converter, TDC).

At present, high-precision TDC mainly includes ASIC (Application Specific Integrated Circuit, application specific integrated circuit), dedicated TDC chip, FPGA (Field Programmable Gate Array, field programmable gate array) and other implementation methods. Therefore, the scheme of implementing TDC based on ASIC is greatly limited, and the dedicated TDC chip has the problems of low integration and inconvenient use.

Using FPGA to measure time is a relatively new time measurement method, which can reduce the complexity and cost of the measurement system compared with the implementation of ASIC and dedicated TDC chips. In the patent application CN1719353A, a TDC device realized by FPGA is described. The main feature of this patent application is to use FPGA internal delay line, multi-bit adder or look-up table LUT to measure fine time, use two counters driven by inverse clocks to measure coarse time, and use half lookup and pipeline technology to realize fine time time code. However, this technology also has the following defects, which makes it difficult to realize the practical application of this technology.

1. This patent application does not measure the starting point of time. Since the starting signal is usually provided externally, which is different from the high-speed clock used in TDC time interpolation, the phase between the rising edge of the starting signal and the leading edge of the clock is uncertain. Therefore, not measuring the start signal greatly reduces the usefulness of existing time measurement techniques.

2. This patent application uses the carry connection, LUT (Look-Up-Table, look-up table) and multi-bit adder inside the FPGA to construct the delay chain. The delay chain constructed is not uniform enough, and the poor performance of the delay chain will seriously Affects the accuracy of time measurements.

This patent application uses binary search and pipeline technology to implement time encoding, which consumes a lot of FPGA logic resources and takes a long time to output measurement results.

Contents of the invention

A brief overview of the invention is given below in order to provide a basic understanding of some aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical parts of the invention nor to delineate the scope of the invention. Its purpose is merely to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

A main object of the present invention is to provide a time measurement system and method with strong practicability and accurate time measurement.

According to one aspect of the present invention, a kind of time measurement system, in order to measure the time to be measured, comprises:

The start signal fine time measurement unit includes a first delay chain formed by a plurality of first delay units connected in series, a plurality of first registers and a first data converter. When no signal is input, each first delay unit outputs All are at the first level, each first register is connected to each first delay unit correspondingly, the first data converter is connected to each first register, and one end of the first delay chain is used to receive the start signal, so that the start signal is received The output of the first delay unit of the signal changes to the second level in turn, and each first register is used to read the output of the first delay unit correspondingly connected to it when the first clock edge of the reference signal after the start signal is input value and save the read data, the first data converter is used to convert the data saved by each first register into time data to obtain the start signal fine time;

The timing signal fine time measurement unit includes a second delay chain formed by a plurality of second delay units connected in series, a plurality of second registers and a second data converter. When there is no signal input, the output of each second delay unit is is the first level, each second register is correspondingly connected to each second delay unit, the second data converter is connected to each second register, and one end of the second delay chain is used to receive a timing signal, so that the first end receiving the timing signal The output of the two delay units changes to the second level in turn, and each second register is used to read the output of the second delay unit connected to it when the timing signal is input to the first clock edge of the reference signal after the second delay chain value and save the read data, and the second data converter is used to convert the data saved by each second register into time data to obtain the fine time of the timing signal;

a coarse time measurement unit, configured to measure a coarse time, the coarse time being the time period between the first clock cycle of the reference signal after the leading edge of the start signal to the first clock cycle of the reference signal after the leading edge of the timing signal; and

The time calculation unit is used to subtract the fine time of the timing signal from the sum of the coarse time and the fine time of the starting signal to obtain the time to be measured.

According to one aspect of the present invention, a method for measuring time is used to measure the time to be measured, comprising:

One end of the first delay chain formed by a plurality of first delay units connected in series receives the start signal, so that the output of the first delay unit that receives the start signal becomes the second level in turn, and the start signal is input to the first When the first clock edge of the reference signal after the delay chain is read through a plurality of first registers correspondingly connected to the first delay unit, the output value of each first delay unit is read and the read data is saved, and the saved The data is converted into time data to obtain the fine time of the start signal, wherein when there is no signal input, the output of each first delay unit is the first level;

One end of the second delay chain formed by a plurality of second delay units in series receives the timing signal, so that the output of the second delay unit receiving the timing signal becomes the second level in turn, after the timing signal is input into the second delay chain When the first clock edge of the reference signal is connected to a plurality of second registers corresponding to the second delay unit, the output value of each second delay unit is read and the read data is saved, and the saved data is converted into Time data to obtain the fine time of the timing signal, wherein when there is no signal input, the output of each second delay unit is the first level;

measure the coarse time, which is the period between the first clock cycle of the reference signal after the leading edge of the start signal and the first clock cycle of the reference signal after the leading edge of the timing signal; and

Subtract the fine time of the timing signal from the sum of the fine time of the start signal and the coarse time to obtain the time to be measured.

The present invention provides a reference point for the measurement of the time to be measured by introducing a starting signal, and uses an interpolation delay chain to determine the time between the rising edge of the starting signal and the rising edge of the first clock thereafter, as well as the time between the rising edge of the timing signal and the first clock rising edge thereafter. The precise measurement of the time between the rising edges of two clocks, combined with the rough measurement driven by the clock signal to obtain the precise time to be measured, solves the problem of low measurement accuracy caused by the different sources of the start signal and the internal clock signal of the FPGA chip. problems, while introducing the starting signal as a reference point improves the practicability of time measurement.

Description of drawings

The above and other objects, features and advantages of the present invention will be more easily understood with reference to the following description of the embodiments of the present invention in conjunction with the accompanying drawings. The components in the drawings are only to illustrate the principles of the invention. In the drawings, the same or similar technical features or components will be denoted by the same or similar reference numerals.

Fig. 1 is a block diagram of a preferred embodiment of the time measuring system of the present invention.

FIG. 2 is a schematic diagram of a simulation of a reference clock signal, a start signal and a timing signal.

FIG. 3 is a schematic diagram of performing segment search on the output data of the delay chain.

Fig. 4 is a flowchart of a preferred embodiment of the time measurement method of the present invention.

Detailed ways

Embodiments of the present invention will be described below with reference to the drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity.

Please refer to FIG. 1 , the time measurement system of the embodiment of the present invention is used to measure the time to be measured, which includes a coarse time measurement unit 10 , a start signal fine time measurement unit 20 , a timing signal fine time measurement unit 30 and a time calculation unit 40 . The time measurement system in the embodiment of the present invention can be integrated in an FPGA chip.

Optionally, the coarse time measurement unit 10 measures the coarse time driven by the clock signal CLOCK of the FPGA chip. Optionally, the coarse time measuring unit 10 may be a clock counter in an FPGA chip.

The time to be measured T is the time difference between the timing moment and the start moment. For example, referring to FIG. 2 , the time to be measured T is the time difference between the timing signal Tstop and the start signal Tstart to be measured. The time T to be measured in the embodiment of the present invention can be calculated by the coarse time Tc, the fine time Tf1 of the start signal and the fine time Tf2 of the timing signal.

The coarse time Tc refers to a time measured by counting time periods of a reference signal (eg, the CLOCK signal in FIGS. 1 and 2 ). As shown in FIG. 2, the rough time Tc is the time difference between the rough start time Tc1 and the rough timing time Tc2. The rough start time Tc1 refers to the time at which time counting is started when performing rough time measurement, and the rough timing time Tc2 refers to the time at which time counting is stopped when performing rough time measurement. In one example, as shown in FIG. 2, the coarse time Tc is between the leading edge of the first clock cycle of the reference signal after the leading edge of the start signal Tstart to the leading edge of the first clock cycle of the reference signal after the leading edge of the timing signal Tstop The time period between, wherein, the rough start time Tc1 is the leading edge of the first clock period of the reference signal after the leading edge of the start signal Tstart. The coarse timing instant Tc2 is the leading edge of the first clock cycle of the reference signal following the leading edge of the timing signal Tstop.

The start signal fine time Tf1 is the absolute value of the time difference between the coarse start time Tc1 and the start time, and the timing signal fine time Tf2 is the absolute value of the time difference between the timing time and the coarse timing time Tc2. In Figure 2, the fine time Tf1 of the start signal refers to the absolute value of the time difference between the first clock edge of the reference signal after the leading edge of the start signal Tstart and the leading edge of the start signal Tstart; the fine time Tf2 of the timing signal is the specified time The absolute value of the time difference between the leading edge of the signal Tstop and the first clock rising edge thereafter. Both the start signal fine time and the timing signal fine time are less than one clock period and therefore cannot be measured by the clock counter.

Therefore, the time to be measured T in the embodiment of the present invention can be calculated by adding the coarse time Tc to the fine time Tf1 of the start signal, and then subtracting the fine time Tf2 of the timing signal.

In an example, the reference signal may be a clock signal inside the FPGA.

Optionally, the start signal fine time measurement unit 20 may include a first delay chain formed by connecting a plurality of first delay units in series, a plurality of first registers and a first data converter. Each first register is correspondingly connected to each first delay unit to form a first register array, and the first data converter is connected to each first register. Optionally, the first delay unit is a delay unit in the FPGA chip, that is, a carry unit (such as MUXCY). The first delay units may be connected in series through carry lines.

The start signal fine time measurement unit 20 is used to receive the start signal Tstart, which can be provided externally or generated internally by the time measurement system of the embodiment of the present invention. When there is no signal input, the output of each first delay unit is the first level (for example, low level), and one end of the first delay chain receives the start signal Tstart, so that each first delay unit that receives the start signal Tstart The output of the delay unit changes to the second level (for example, high level) in sequence. At the rough start time Tc1, that is, in Figure 1 of this embodiment, when the first clock rising edge of the CLOCK signal after the start signal Tstart is input to the first delay chain, each first register reads its corresponding connection The output value of the first delay unit and save the read data. The first data converter converts the data stored in each first register into time data, that is, obtains the start signal fine time Tf1.

Optionally, the timing signal fine time measurement unit 30 also includes a second delay chain formed in series by a plurality of second delay units, a plurality of second registers and a second data converter, the structure of which is the same as that of the start signal fine time measurement The structure of the unit 20 is similar, and each second register is correspondingly connected with each second delay unit to form a second register array, and the second data converter is connected to each second register.

The timing signal fine time measurement unit 30 obtains the timing signal fine time Tf2 and the starting signal fine time measurement unit 20 obtains the principle similar to the start signal fine time Tf1, and one end of the second delay chain is used to receive the timing signal Tstop, so that the timing signal is received The output of the second delay unit of the signal Tstop becomes the second level in turn. At the rough timing time Tc2, that is, in FIG. 1 of this embodiment, when the first clock rising edge of the CLOCK signal after the timing signal is input into the second delay chain, each second register reads the correspondingly connected first clock edge. The output value of the second delay unit is used to store the read data, and the second data converter is used to convert the data stored in each second register into time data to obtain the fine time Tf2 of the timing signal.

Optionally, in this embodiment of the present invention, each first register corresponds to different time data, and each second register also corresponds to different time data. The first and second data converters search the second-level data stored in the first and second register arrays to find the end point of the transmission of the start signal Tstart or the timing signal Tstop in the corresponding first or second delay chain, And by encoding and outputting the time data corresponding to the end point, the fine time Tf1 of the start signal or the fine time Tf2 of the timing signal can be obtained.

Optionally, in this embodiment of the present invention, the second-level data stored in the first and second register arrays is searched for using a segmented search method. Taking Figure 3 as an example for illustration, the segmented search method is as follows:

Step 1: Divide the output of the first or second register array into multiple groups sequentially from the highest bit to the lowest bit, such as groups a, b, c, and d in Figure 3, where the highest bit a6 of the highest group a is the delay At the end of the chain, the lowest bit d1 of the lowest group d is the head of the delay chain, first judge the lowest bit a1 of the highest group a, if the lowest bit a1 of the highest group a is the second level, it means that the signal has been transmitted here, then from The highest bit a6 of the highest group a searches downwards in turn for the end of the transmission of the start signal or timing signal, that is, starts from the highest bit a6 of the highest group a and searches for the position of the first second level.

Step 2: If the lowest bit a1 of the highest group a is the first level, it means that the signal has not been transmitted here, then judge the lowest bit b1 of the second highest group b, if the lowest bit b1 of the second highest group b is the second level, Then search for the position of the first second level from the highest bit b6 of the second highest group b.

Step 3: By analogy, until the position of the first second level is found, to find the end point of the start signal or timing signal transmitted in the corresponding first or second delay chain, so that the first or second data The converter obtains the time data corresponding to the end of transmission of the start signal Tstart or the timing signal Tstop in the corresponding first or second delay chain, that is, obtains the fine time Tf1 of the start signal or the fine time Tf2 of the timing signal.

The time calculating unit 40 is based on the coarse time Tc measured by the coarse time measuring unit 10, the start signal fine time Tf1 measured by the start signal fine time measuring unit 20, and the timing signal fine time Tf2 measured by the timing signal fine time measuring unit 30 Calculate the waiting time T. In the embodiment of the present invention, the time calculation unit 40 subtracts the fine time Tf2 of the timing signal from the sum of the fine time Tf1 of the start signal and the coarse time Tc to obtain the time T to be measured.

Please refer to Fig. 4, the preferred embodiment of time measuring method of the present invention comprises the following steps:

Step S1: one end of the first delay chain receives the start signal Tstart, so that the output of the delay unit receiving the start signal Tstart becomes the second level in turn, and each first register is input to the first delay chain after the start signal Tstart When the first clock edge of the reference signal is read, the output value of the first delay unit connected to it is read and the read data is saved, and the data converter converts the data saved in each register into time data, that is, the starting value is obtained Start signal fine time Tf1. The start signal fine time Tf1 is the time between the rising edge of the start signal Tstart and the first clock rising edge of the subsequent reference signal.

Step S2: one end of the second delay chain receives the timing signal Tstop, so that the output of the second delay unit receiving the timing signal Tstop becomes the second level in turn, and each second register is input to the second delay chain after the timing signal Tstop When the first clock edge of the reference signal is read, the output value of the second delay unit correspondingly connected to it is read and the read data is stored, and the data converter converts the data stored in each second register into time data, that is, Timing signal fine time Tf2. The timing signal fine time Tf2 is the time between the leading edge of the timing signal Tstop and the first clock rising edge of the subsequent reference signal.

Step S3: The rough time measurement unit 10 measures a rough time. The coarse time is a time period between the first clock cycle of the reference signal after the leading edge of the start signal Tstart and the first clock cycle of the reference signal after the leading edge of the timing signal Tstop. Optionally, the reference signal may be the clock signal CLOCK on the FPGA chip.

Step S4: The time calculation unit 40 calculates the time to be measured T according to the coarse time Tc obtained in step S3, the start signal fine time Tf1 obtained in step S1, and the timing signal fine time Tf2 obtained in step S2. In this step, the time calculation unit 40 may subtract the fine time Tf2 of the timing signal from the sum of the fine time Tf1 of the start signal and the coarse time Tc to obtain the time T to be measured.

Optionally, in steps S2 and S3, the second-level data stored in the first and second register arrays is searched for using a segmentation search method, so as to search for start signal Tstart or timing signal Tstop at the corresponding first or second level data. The end point of the transmission in the second delay chain, and by encoding and outputting the time data corresponding to the end point, the fine time Tf1 of the start signal or the fine time Tf2 of the timing signal can be obtained. The segmentation search method has been explained in the above description, and will not be repeated here.

In the embodiment of the present invention, a reference point is provided for the measurement of the timing moment by introducing a start signal, and an interpolation delay chain is used to measure the time between the front edge of the start signal and the first clock edge thereafter and the time between the front edge of the timing signal and the subsequent clock edge. The time between the leading edge of the first clock is finely measured, combined with the rough measurement driven by the clock signal to obtain the accurate time to be measured, which solves the low measurement accuracy caused by the different sources of the start signal and the internal clock signal of the FPGA chip At the same time, the introduction of the starting signal as a reference point improves the practicability of time measurement.

The embodiment of the present invention adopts the internal carry unit of the FPGA chip to construct the time delay chain, which has the advantage of more uniform delay compared with the delay chain constructed by the adder, LUT, etc., and improves the accuracy and reliability of time measurement.

In the embodiment of the present invention, the timing signal to be measured is connected to the delay chain, and the reference clock signal is connected to the register array, and only one clock counter can realize the coarse time measurement, and the structure is simple.

Embodiments of the present invention use the segmented search method to read the output states of each delay unit in the delay chain, and convert the search of the serial combination of the delay chain into a parallel search of multiple serial segments, which can be performed in a very short time The result of the search is obtained. It is proved by experiments that the segmentation search can obtain the search result within one clock cycle, which greatly reduces the usage of FPGA logic resources and reduces the acquisition time of time data.

In the device and method of the present invention, obviously, each component or each step can be decomposed, combined and/or recombined after decomposing. These decompositions and/or recombinations should be considered equivalents of the present invention. It should also be pointed out that the steps for executing the above series of processes can naturally be executed in chronological order according to the illustrated order, but it does not need to be executed in chronological order. Certain steps may be performed in parallel or independently of each other. Meanwhile, in the above descriptions of specific embodiments of the present invention, features described and/or shown for one embodiment can be used in one or more other embodiments in the same or similar manner, and combination of features, or replace features in other embodiments.

Claims (6)

1. A time measuring system for measuring the time to be measured, comprising: The start signal fine time measurement unit includes a first delay chain formed by a plurality of first delay units connected in series, a plurality of first registers and a first data converter. When no signal is input, each first delay unit outputs are all at the first level, each first register is correspondingly connected to each first delay unit, the first data converter is connected to each first register, and one end of the first delay chain is used to receive a start signal, so that the received The output of the first delay unit of the start signal changes to the second level in turn, and each first register is used to read the correspondingly connected first delay unit when the first clock edge of the reference signal after the start signal is input and save the read data, the first data converter is used to convert the data saved by each first register into time data to obtain the fine time of the start signal; The timing signal fine time measurement unit includes a second delay chain formed by a plurality of second delay units connected in series, a plurality of second registers and a second data converter. When there is no signal input, the output of each second delay unit is is the first level, each second register is correspondingly connected to each second delay unit, the second data converter is connected to each second register, and one end of the second delay chain is used to receive a timing signal, so that when the timing signal is received The output of the second delay unit changes to the second level in turn, and each second register is used to read the second delay unit correspondingly connected to it when the timing signal is input to the first clock edge of the reference signal after the second delay chain The output value and the read data are stored, and the second data converter is used to convert the data stored in each second register into time data to obtain the fine time of the timing signal; A coarse time measurement unit, configured to measure a coarse time, the coarse time is between the first clock cycle of the reference signal after the leading edge of the start signal and the first clock cycle of the reference signal after the leading edge of the timing signal period of time; and a time calculation unit, configured to subtract the fine time of the timing signal from the sum of the coarse time and the fine time of the start signal to obtain the time to be measured; Each first register corresponds to different time data respectively, and each second register also corresponds to different time data respectively, and the fine time measurement unit for the start signal or the fine time measurement unit for the timing signal is also specifically used for: The output of each first or second register is sequentially divided into multiple groups from the highest bit to the lowest bit, wherein the highest bit of the highest group is the tail of the corresponding first or second delay chain, and the lowest bit of the lowest group is the corresponding the header of the first or second delay chain; Judging the level state of the lowest bit of the highest group, if the lowest bit of the highest group is the second level, start from the highest bit of the highest group to find the position of the first second level; If the lowest bit of the highest group is the first level, then judge the level state of the lowest bit of the second highest group, if the lowest bit of the second highest group is the second level, start searching from the highest bit of the second highest group the location of the first second level; and By analogy, until the position of the first second level is found, to find the end point of the start signal or timing signal transmitted in the corresponding first or second delay chain, to obtain the start signal or timing signal at the corresponding The time data corresponding to the end point transmitted in the first or second delay chain, so as to obtain the fine time of the start signal or the fine time of the timing signal. 2. The time measurement system according to claim 1, wherein the coarse time measurement unit is a clock counter in a field programmable gate array chip. 3. time measurement system as claimed in claim 1, is characterized in that, each first delay unit, the second delay unit are carry units in the field programmable gate array chip, and each first delay unit is connected in series by carry line , each second delay unit is connected in series through a carry line. 4. A time measurement method for measuring the time to be tested, comprising: One end of the first delay chain formed by a plurality of first delay units connected in series receives the start signal, so that the output of the first delay unit that receives the start signal becomes the second level in turn, and the start signal is input to the first When the first clock edge of the reference signal after the delay chain is read through a plurality of first registers correspondingly connected to the first delay unit, the output value of each first delay unit is read and the read data is saved, and the saved The data is converted into time data to obtain the fine time of the start signal, wherein when there is no signal input, the output of each first delay unit is the first level; One end of the second delay chain formed by a plurality of second delay units in series receives the timing signal, so that the output of the second delay unit receiving the timing signal becomes the second level in turn, after the timing signal is input into the second delay chain When the first clock edge of the reference signal is connected to a plurality of second registers corresponding to the second delay unit, the output value of each second delay unit is read and the read data is saved, and the saved data is converted into Time data to obtain the fine time of the timing signal, wherein when there is no signal input, the output of each second delay unit is the first level; measuring a coarse time, the coarse time being the time period between the first clock cycle of the reference signal after the leading edge of the start signal to the first clock cycle of the reference signal after the leading edge of the timing signal; and subtracting the fine time of the timing signal from the sum of the fine time of the starting signal and the coarse time to obtain the time to be measured; Each first register corresponds to different time data respectively, and each second register also corresponds to different time data respectively, and the steps of measuring the fine time of the starting signal or the fine time of the timing signal respectively include: The output of each first or second register is sequentially divided into multiple groups from the highest bit to the lowest bit, wherein the highest bit of the highest group is the tail of the corresponding first or second delay chain, and the lowest bit of the lowest group is the corresponding the header of the first or second delay chain; Judging the level state of the lowest bit of the highest group, if the lowest bit of the highest group is the second level, start from the highest bit of the highest group to find the position of the first second level; If the lowest bit of the highest group is the first level, then judge the level state of the lowest bit of the second highest group, if the lowest bit of the second highest group is the second level, start searching from the highest bit of the second highest group the location of the first second level; and By analogy, until the position of the first second level is found, to find the end point of the start signal or timing signal transmitted in the corresponding first or second delay chain, to obtain the start signal or timing signal at the corresponding The time data corresponding to the end point transmitted in the first or second delay chain, so as to obtain the fine time of the start signal or the fine time of the timing signal. 5. The time measurement method according to claim 4, wherein the step of measuring the coarse time comprises measuring the coarse time by a clock counter in a field programmable gate array chip. 6. time measuring method as claimed in claim 4, it is characterized in that, each first delay unit, the second delay unit are carry units in the field programmable gate array chip, each first delay unit is connected in series by carry line , each second delay unit is connected in series through a carry line.