CN110442012A - A kind of precision time interval measurement method and system based on FPGA - Google Patents
A kind of precision time interval measurement method and system based on FPGA Download PDFInfo
- Publication number
- CN110442012A CN110442012A CN201910661291.1A CN201910661291A CN110442012A CN 110442012 A CN110442012 A CN 110442012A CN 201910661291 A CN201910661291 A CN 201910661291A CN 110442012 A CN110442012 A CN 110442012A
- Authority
- CN
- China
- Prior art keywords
- time interval
- result
- fpga
- bigness scale
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
Abstract
The present invention relates to a kind of precision time interval measurement methods based on FPGA, include the following steps, the bigness scale amount of the time interval between two pulses is carried out using pulse stuff counting method, obtains the bigness scale result of time interval；The phase difference less than a clock cycle is carefully measured based on FPGA tap time delay chain, obtains the thin survey result of time interval；According to the bigness scale result and the thin final measurement surveyed result and determine the time interval.The present invention is by combining bigness scale amount and accurate measurement amount, using the high-precision time-delay interval of tens picosecond of FPGA delay cell, makes it possible to measure large-scale time interval, and obtain higher measurement accuracy.The high precision time interval measurement system based on FPGA that the invention also includes a kind of.
Description
Technical field
The invention belongs to time interval measurement fields, and in particular to a kind of high precision time interval measurement side based on FPGA
Method and system.
Background technique
With the rapid development of science and technology, the measurement of time interval is especially high-precision time interval measurement technology and exists
It plays an important role, especially has in fields such as navigator fix, satellite time transfer, laser rangings very extensive in scientific research
Using, while being also the research hotspot in time and frequency measurement field.
Time interval measurement technology is usually to be used to measure the time interval that two or more physical events occur in succession, together
When time interval that measurement is obtained be converted into corresponding number, therefore this technology is also referred to as time-to-digital converter technology
(Time to Digital Conversion, TDC).There are many method of time interval measurement technology at present, wherein using most
Be the measurement method based on TDC chip.The typical resolution of TDC chip measurement is 50ps, therefore can be received and paid out with precise measurement
The phase difference of second grade；But the chip has biggish the disadvantage is that its measurement range is relatively narrow, generally all in nanosecond to a Microsecond grade left side
The right side, for being just difficult to meet actual requirement of engineering compared with wide-measuring range.
Summary of the invention
The present invention provides between a kind of split-second precision based on FPGA to solve the technical problem in above-mentioned background technique
Every measurement method and system.
The technical scheme to solve the above technical problems is that using between two pulses of progress of pulse stuff counting method
Time interval bigness scale amount, obtain the bigness scale result of time interval；Based on FPGA tap time delay chain to less than one clock week
The phase difference of phase is carefully measured, and the thin survey result of time interval is obtained；It is true according to the bigness scale result and the thin survey result
The final measurement of the fixed time interval.
The beneficial effects of the present invention are: respectively postponing list using FPGA time delay chain by combining bigness scale amount and accurate measurement amount
Tens picoseconds ps grade of high-precision time-delay interval of member, makes it possible to measure large-scale time interval, and acquirement compared with
High measurement accuracy.
Further, the bigness scale amount that the time interval between two pulses is carried out using pulse stuff counting method, is obtained
The bigness scale result of time interval, comprising: the pulse number N in gate spacer is calculated by pulse counter, according to described
The pulse number N and clock cycle T0The bigness scale of time interval is obtained as a result, TN=N*T0。
Beneficial effect using above-mentioned further scheme is, using the larger feature of rolling counters forward range of using tricks is counted, to realize
Long interval of time measurement.
Further, the pulse counter uses gray code counter.
Beneficial effect using above-mentioned further scheme is that there was only one every time using gray code counter can jump
Characteristic, as much as possible reduction switch noise and metastable state phenomenon occur probability, improve the stability of measurement.
Further, the counting pulse that the pulse stuff counting method uses is phase-locked loop pll in FPGA according to atomic clock
What the frequency signal frequency multiplication of output generated.
Beneficial effect using above-mentioned further scheme is to pass through the small, FPGA using shake inside phase-locked loop pll and time delay
Inside has the characteristic of dedicated clock network resource wiring, by using the atomic clock clock signal of high accuracy and stability
As benchmark, the counting pulse of high stability and accuracy is generated, to improve the reliability and accuracy of bigness scale amount.
It is further, described that the phase difference less than a clock cycle is carefully measured based on FPGA tap time delay chain,
Obtain the thin survey result of time interval, comprising: one group of delay cell is cascaded into the tapped delay chain to be formed, each delay cell
Delay time is τ, and a tap is drawn in each delay cell and is latched with corresponding trigger；Make measured signal
Rising edge transmits in the tap time delay chain, and when the rising edge of the signal strobe arrives, each trigger is to the pumping
The current state of each tap in head delay chain is sampled, and is sentenced according to the number m of each trigger output signal Q=1
Passing time of the rising edge of disconnected measured signal in the tapped delay chain, t=m* τ.
Beneficial effect using above-mentioned further scheme is, using FPGA internal delay cells delay time usually tens
Picosecond and the relatively stable characteristic that is delayed realize the high-acruracy survey to tested time interval.
Further, determine that the final measurement of the time interval is tied according to the bigness scale result and the thin result of surveying
Fruit, comprising: the time interval T between described two pulsesd=TN+T1-T2；The bigness scale result T of the time intervalN=N*T0；Institute
It states time interval and carefully surveys result T1=m1* τ, T2=m2* τ.
Further, the delay cell is that configuration FPGA internal searching table obtains, and the internal searching table has
Tetra- kinds of input ports of DATAA, DATAB, DATAC, DATAD, in one group of delay cell, input port type is identical.
Beneficial effect using above-mentioned further scheme is, by making to select the same input port of internal searching table
The delay time for obtaining each delay cell is consistent, avoids because selecting different input ports to lead to the different of delay units delay time
It causes, and influences measurement accuracy.And internal searching table quantity resource inside FPGA is larger, uses internal searching table single as delay
Member can reduce the waste of FPGA internal resource.
Further, described to be the delay unit by logical locking.
Beneficial effect using above-mentioned further scheme is, by carrying out logical locking to delay unit, to avoid delay single
Member be integrated into when comprehensive or by the other circuits of FPGA influence, improve the stability of delay unit.
The high precision time interval measurement system based on FPGA that the present invention also provides a kind of, using such as above-mentioned measurement side
Method, including bigness scale module, accurate measurement module and computing module, in which: the bigness scale module, for using pulse stuff counting method into
The bigness scale amount of time interval between two pulses of row, obtains the bigness scale result of time interval；The accurate measurement module, for being based on
FPGA tap time delay chain carefully measures the phase difference less than a clock cycle, obtains the thin survey result of time interval；Institute
Computing module is stated, for according to the bigness scale result and the thin final measurement surveyed result and determine the time interval.
Beneficial effect using the above scheme is, each using FPGA time delay chain by combining bigness scale amount and accurate measurement amount
The high-precision time-delay interval that tens picoseconds ps grades of delay cell makes it possible to measure large-scale time interval, and
Obtain higher measurement accuracy.
Further, the thick side form block uses gray code counter, for being calculated by gray code counter in lock
Pulse number N in door interval, according to the pulse number N and the clock cycle T0The bigness scale of time interval is obtained as a result, TN
=N*T0；
The thin survey module is that one group of delay cell is cascaded the tapped delay chain to be formed, when the delay of each delay cell
Between be τ, draw and a tap and latched with corresponding trigger in each delay cell；
For transmitting the rising edge of measured signal in the tap time delay chain, when the rising edge of the signal strobe arrives
When coming, each trigger samples the current state of each tap in the tapped delay chain, according to each trigger
The number m of output signal Q=1 judges passing time of the rising edge of measured signal in the tapped delay chain, t=m* τ；
The computing module, for calculating the time interval T between described two pulsesd=TN+T1-T2；
Wherein, the bigness scale result T of the time intervalN=N*T0；The time interval carefully surveys result T1=m1* τ, T2=
m2*τ。
Beneficial effect using the above scheme is, by using gray count, as much as possible reduction switch noise and Asia
The probability that steady state phenomena occurs；By using tap time delay chain, higher measurement accuracy is realized.
Detailed description of the invention
Fig. 1 is the work flow diagram provided according to the embodiment of the present invention；
Fig. 2 is the bigness scale process chart provided according to the embodiment of the present invention.
Fig. 3 is the accurate measurement function structure chart provided according to the embodiment of the present invention；Fig. 4 is to be mentioned according to the embodiment of the present invention
A kind of high precision time interval measurement system structure diagram based on FPGA supplied.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
The present embodiment provides a kind of precision time interval measurement method based on FPGA, work flow diagram such as Fig. 1 institutes
Show, this method includes that step is implemented as follows: carrying out the bigness scale amount of the time interval between two pulses using pulse stuff counting method,
Obtain the bigness scale result of time interval；The phase difference less than a clock cycle is carefully surveyed based on FPGA tap time delay chain
Amount, obtains the thin survey result of time interval；The time interval is determined most according to the bigness scale result and the thin survey result
Whole measurement result.
In FPGA, there is delay time T such as transmitted between look-up table LUT, register, RAM, each basic unit of wiring,
Delay time T of the delay time T usually between tens picoseconds, one species basic unit is almost the same, which can
By being obtained with simulation softwares such as modelsim, quartus2.
In above-described embodiment, by constructing the multi-tap time chain being made of basic unit, higher measurement essence may be implemented
Degree.In addition, pulse stuff counting method can be realized larger range step-by-step counting.It, can by combining bigness scale amount and accurate measurement amount
A wide range of time interval is measured with realizing, can also obtain higher measurement accuracy.
Optionally, as shown in Fig. 2, the bigness scale for carrying out the time interval between two pulses using pulse stuff counting method
Amount, obtains the bigness scale result of time interval, comprising: calculate the pulse number N in gate spacer, root by pulse counter
According to the pulse number N and the clock cycle T0The bigness scale of time interval is obtained as a result, TN=N*T0。
In above-described embodiment, using the larger feature of rolling counters forward range of using tricks is counted, long interval of time measurement is realized.
Optionally, the pulse counter uses gray code counter.
Gray code meter, which only has one every time, to be jumped, and common binary counter is then at least when counting
One jumps, and is easy to generating metastable phenomenon when multidigit jumps simultaneously, and entanglement occurs so as to cause count results.With
The raising of FPGA working frequency, the probability of generating metastable phenomenon significantly increase.And Gray code only has one every time and jumps
Become, the probability that can reduce switch noise and the generation of metastable state phenomenon as much as possible is counted by using gray encoding.
Further, the counting pulse that the pulse stuff counting method uses is phase-locked loop pll in FPGA according to atomic clock
What the frequency signal frequency multiplication of output generated.The counting pulse can be, and be exported using phase-locked loop pll inside FPGA to atomic clock
10MHz frequency signal frequency multiplication obtain the counting pulse that frequency is 200MHz, i.e. the clock cycle can achieve 5ns, namely count
The clock cycle T of pulse0For 5ns.
In above-described embodiment, by the way that there is dedicated clock inside small, FPGA using shake inside phase-locked loop pll and time delay
The characteristic of Internet resources wiring generates high steady by using the atomic clock clock signal of high accuracy and stability as benchmark
The counting pulse of fixed degree and accuracy, to improve the reliability and accuracy of bigness scale amount.
It is further, described that the phase difference less than a clock cycle is carefully measured based on FPGA tap time delay chain,
The thin survey of time interval is obtained as a result, as shown in Figure 3, comprising: one group of delay cell is cascaded into the tapped delay chain to be formed, each
The delay time of delay cell is τ, and a tap is drawn in each delay cell and is latched with corresponding trigger；Make
The rising edge of measured signal transmits in the tap time delay chain, when the rising edge of the signal strobe arrives, each triggering
Device samples the current state of each tap in the tapped delay chain, according to each trigger output signal Q=1's
Number m judges passing time of the rising edge of measured signal in the tapped delay chain, t=m* τ.
Using the lag characteristic of each basic unit grades such as FPGA internal searching table LUT, register, RAM, wiring, made
For form tapped delay chain delay cell, and to delay cell tap connect register, store time delay, prolonged with reaching with tap
The purpose at interval when slow chain survey high-acruracy survey.The delay time of delay cell, difference, the basic unit used with it are different
And it is different, can be required according to different measurement accuracy, select different basic units as delay cell, realize to it is tested when
Between the high-acruracy survey that is spaced.
Optionally, the final measurement of the time interval is determined according to the bigness scale result and the thin survey result,
It include: the time interval T between described two pulsesd=TN+T1-T2；The bigness scale result T of the time intervalN=N*T0；When described
Between be spaced and thin survey result T1=m1* τ, T2=m2* τ.
Optionally, the delay cell be configuration FPGA internal searching table obtain, the internal searching table have DATAA,
Tetra- kinds of input ports of DATAB, DATAC, DATAD, in one group of delay cell, input port type is identical.
It is consistent substantially single by being arranged by select the same input port of internal searching table in above-described embodiment
Meta structure avoids so that the delay time of each delay cell is consistent because selecting different input ports to lead to delay units delay
Time it is inconsistent, and influence measurement accuracy.And internal searching table quantity resource inside FPGA is larger, uses internal searching table
As the more convenient realization of delay cell, and the waste of FPGA internal resource can be reduced.
Optionally, described to be the delay unit by logical locking.
In above-described embodiment, by carrying out logical locking to delay unit, delay unit is avoided to be integrated into when comprehensive
Or influenced by the other circuits of FPGA, improve the stability of delay unit.
The high precision time interval measurement system based on FPGA that the present invention also provides a kind of, using such as above-mentioned measurement side
Method, including bigness scale module, accurate measurement module and computing module, structural block diagram are as shown in Figure 4, in which: the bigness scale module, for adopting
The bigness scale amount of time interval between carrying out two pulses with pulse stuff counting method obtains the bigness scale result of time interval；It is described
Accurate measurement module obtains the time for carefully being measured based on FPGA tap time delay chain the phase difference less than a clock cycle
The thin survey result at interval；The computing module, for being determined between the time according to the bigness scale result and the thin survey result
Every final measurement.
In above-described embodiment, by combining bigness scale amount and accurate measurement amount, each delay cell of FPGA tap time delay chain is utilized
The high-precision time-delay interval of tens picoseconds makes it possible to measure large-scale time interval, and obtains higher
Measurement accuracy.
Further, the thick side form block uses gray code counter, for being calculated by gray code counter in lock
Pulse number N in door interval, according to the pulse number N and the clock cycle T0The bigness scale of time interval is obtained as a result, TN
=N*T0；
The thin survey module is that one group of delay cell is cascaded the tapped delay chain to be formed, when the delay of each delay cell
Between be τ, draw and a tap and latched with corresponding trigger in each delay cell；
For transmitting the rising edge of measured signal in the tap time delay chain, when the rising edge of the signal strobe arrives
When coming, each trigger samples the current state of each tap in the tapped delay chain, according to each trigger
The number m of output signal Q=1 judges passing time of the rising edge of measured signal in the tapped delay chain, t=m* τ；
The computing module, for calculating the time interval T between described two pulsesd=TN+T1-T2；
Wherein, the bigness scale result T of the time intervalN=N*T0；The time interval carefully surveys result T1=m1* τ, T2=
m2*τ。
In above-described embodiment, by using gray count, reduction switch noise and metastable state phenomenon as much as possible occurs
Probability；By using tap time delay chain, higher measurement accuracy is realized.
Hereinafter, in conjunction with the 1PPS (1 Pulse Per Second) that satellite reception field multimode GNSS receiver is exported into
Row measurement, the in detail process of narration measurement.
In technical field of satellite time service, need for local zone time to be synchronized with Coordinated Universal Time(UTC) UTC time, time synchronization relies on
In high-precision time interval measurement.During time interval measurement, in order to measure to obtain high-precision time interval, then need
The measurement method for taking bigness scale refinement to survey.
Bigness scale amount is carried out first, and thick measurement process is as shown in Figure 2.The 1PPS signal of receiver output is accessed into bigness scale mould
Block, adjacent two pulse is respectively as start and stop signal.
The clock cycle for counting pulse is T0, this bigness scale counts pulse system phase-locked loop pll by exporting atomic clock
10MHz frequency signal is obtained through frequency multiplication 200MHz, therefore, T herein0For 5ns.When start signal rising edge arrives, lock is opened
Door, when stop signal rising edge arrives, closed shutter, pulse counter calculates the pulse number N in gate spacer, obtains
To bigness scale time interval TNFor N*T0, T is spaced between bigness scale time interval and true pulse per second (PPS)dThere are a counting error, errors
It is worth size ± 1.As shown in Fig. 2, in fact, start rises edge and there are the phase difference of T1, stop between signal strobe rising edge
There are the phase differences of T2 between signal rising edge and signal strobe failing edge, between true start signal and stop signal when
Between between be divided into Td=TN+T1-T2, therefore accurately measure T1And T2, so that it may more really measure time interval, Ke Yiyou
The error of calibration ± 1 word of effect.Pulse counter is counted using gray encoding, its main feature is that gray code counter is every
Secondary only one can jump, and common binary counter is then at least one when counting and jumps, when more
Position is easy to generating metastable phenomenon when jumping simultaneously, and entanglement occurs so as to cause count results.And gray code counter is each
Only one jumps, therefore can reduce the probability of switch noise and the generation of metastable state phenomenon as much as possible.
To T1And T2Accurate measurement is carried out, with T1For, accurate measurement process is as shown in Figure 3.
Opening signal, that is, start signal rising edge is transmitted in tapped delay chain, when in door signal, that is, Fig. 3
When signal strobe rising edge arrives, each trigger samples the current state of each tap in delay chain, according to every
The number of a trigger output 1 judges passing time of the opening signal in delay chain, and by result be input to register into
Row deposit.T1It can be represented by the following formula: T1=m1* τ, m1 are the number of output 1 in trigger, thus be may be implemented in short-term
Between the precise measurement that is spaced, T1When the stability and measurement accuracy of measurement depend on the delay stability and delay of delay cell
Between.
With T1Accurate measurement process is similar, measures T2Measurement result be T2=m2* τ
The comprehensive bigness scale module of computing module and accurate measurement module measurement result are calculated, and final measurement T is obtainedd=TN+
T1-T2；Wherein, the bigness scale result T of the time intervalN=N*T0；The time interval carefully surveys result T1=m1* τ, T2=m2*
τ。
By using a kind of precision time interval measurement method and system based on FPGA of the present invention, realize
Measurement to the 1PPS signal of the GNSS receiver output of 1 second time interval, the precision of measurement reach tens picoseconds, solve
The problem of measurement to the 1PPS signal of the GNSS receiver output at long period interval, measurement accuracy not can guarantee.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of precision time interval measurement method based on FPGA, which is characterized in that including step is implemented as follows:
The bigness scale amount that the time interval between two pulses is carried out using pulse stuff counting method, obtains the bigness scale knot of time interval
Fruit；
The phase difference less than a clock cycle is carefully measured based on FPGA tap time delay chain, obtains the thin survey of time interval
As a result；
According to the bigness scale result and the thin final measurement surveyed result and determine the time interval.
2. a kind of precision time interval measurement method based on FPGA according to claim 1, which is characterized in that described
The bigness scale amount that the time interval between two pulses is carried out using pulse stuff counting method obtains the bigness scale of time interval as a result, packet
It includes:
The pulse number N in gate spacer is calculated by pulse counter, according to the pulse number N and clock week
Phase T0The bigness scale of time interval is obtained as a result, TN=N*T0。
3. a kind of precision time interval measurement method based on FPGA according to claim 2, which is characterized in that described
Pulse counter uses gray code counter.
4. a kind of precision time interval measurement method based on FPGA according to claim 1, which is characterized in that described
The counting pulse that pulse stuff counting method uses generates for phase-locked loop pll in FPGA according to the frequency signal frequency multiplication that atomic clock exports
's.
5. a kind of precision time interval measurement method based on FPGA according to claim 2, which is characterized in that described
The phase difference less than a clock cycle is carefully measured based on FPGA tap time delay chain, obtains the thin survey knot of time interval
Fruit, comprising:
One group of delay cell is cascaded into the tapped delay chain to be formed, the delay time of each delay cell is τ, and each delay is single
A tap is drawn in member and is latched with corresponding trigger；
Transmit the rising edge of measured signal in the tap time delay chain, when the rising edge of the signal strobe arrives, often
A trigger samples the current state of each tap in the tapped delay chain, according to each trigger output signal
The number m of Q=1 judges passing time of the rising edge of measured signal in the tapped delay chain, t=m* τ.
6. a kind of precision time interval measurement method based on FPGA according to claim 5, which is characterized in that according to
The bigness scale result and the thin final measurement surveyed result and determine the time interval, comprising:
Time interval T between described two pulsesd=TN+T1-T2；
The bigness scale result T of the time intervalN=N*T0；
The time interval carefully surveys result T1=m1* τ, T2=m2* τ.
7. a kind of precision time interval measurement method based on FPGA according to claim 5, which is characterized in that described
Delay cell is that configuration FPGA internal searching table obtains, and the internal searching table has DATAA, DATAB, DATAC, DATAD tetra-
Kind input port, in one group of delay cell, input port type is identical.
8. a kind of precision time interval measurement method based on FPGA according to claim 5, which is characterized in that described
Delay unit passes through logical locking.
9. a kind of high precision time interval measurement system based on FPGA, which is characterized in that including bigness scale module, accurate measurement module and
Computing module, in which:
The bigness scale module is obtained for being carried out the bigness scale amount of the time interval between two pulses using pulse stuff counting method
The bigness scale result of time interval；
The accurate measurement module, for carefully being measured based on FPGA tap time delay chain the phase difference less than a clock cycle,
Obtain the thin survey result of time interval；
The computing module, for according to the bigness scale result and the thin final measurement surveyed result and determine the time interval
As a result.
10. a kind of high precision time interval measurement system based on FPGA according to claim 9, which is characterized in that institute
It states thick side form block and uses gray code counter, for calculating the pulse number N in gate spacer by gray code counter,
According to the pulse number N and the clock cycle T0The bigness scale of time interval is obtained as a result, TN=N*T0；
The thin survey module is that one group of delay cell is cascaded the tapped delay chain to be formed, and the delay time of each delay cell is equal
A tap is drawn for τ, in each delay cell and is latched with corresponding trigger；
For transmitting the rising edge of measured signal in the tap time delay chain, when the rising edge of the signal strobe arrives
When, each trigger samples the current state of each tap in the tapped delay chain, defeated according to each trigger
The number m of signal Q=1 judges passing time of the rising edge of measured signal in the tapped delay chain, t=m* τ out；
The computing module, for calculating the time interval T between described two pulsesd=TN+T1-T2；
Wherein, the bigness scale result T of the time intervalN=N*T0；The time interval carefully surveys result T1=m1* τ, T2=m2* τ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910661291.1A CN110442012A (en) | 2019-07-22 | 2019-07-22 | A kind of precision time interval measurement method and system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910661291.1A CN110442012A (en) | 2019-07-22 | 2019-07-22 | A kind of precision time interval measurement method and system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110442012A true CN110442012A (en) | 2019-11-12 |
Family
ID=68431050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910661291.1A Pending CN110442012A (en) | 2019-07-22 | 2019-07-22 | A kind of precision time interval measurement method and system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110442012A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111007520A (en) * | 2019-12-30 | 2020-04-14 | 中国科学院微电子研究所 | Multi-channel time measuring system and method based on FPGA and laser scanner |
| CN111061145A (en) * | 2019-12-30 | 2020-04-24 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| CN111679569A (en) * | 2020-06-16 | 2020-09-18 | 中国科学院国家授时中心 | Time interval measuring system and method based on mismatched transmission lines |
| CN112506031A (en) * | 2020-11-30 | 2021-03-16 | 中国计量科学研究院 | High-precision time interval measuring system for laser interference fringe signals |
| CN113125944A (en) * | 2021-04-29 | 2021-07-16 | 上海科技大学 | Circuit delay detector for FPGA (field programmable Gate array) supporting full path and detection method |
| CN113271168A (en) * | 2021-04-26 | 2021-08-17 | 广西电网有限责任公司桂林供电局 | Power distribution network clock synchronization implementation method based on satellite common view |
| CN113328745A (en) * | 2021-05-24 | 2021-08-31 | 黑龙江省计量检定测试研究院 | Time interval measuring system and method |
| CN113625050A (en) * | 2021-08-13 | 2021-11-09 | 安徽中金码电子科技有限公司 | High-precision pulse repetition interval measuring device and method based on interpolation method |
| CN113655702A (en) * | 2021-10-20 | 2021-11-16 | 南京宏泰半导体科技有限公司 | Self-adaptive carry delay chain coefficient adjusting system and method based on FPGA (field programmable Gate array) test |
| CN113934132A (en) * | 2021-10-12 | 2022-01-14 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| CN114513196A (en) * | 2022-01-17 | 2022-05-17 | 烽火通信科技股份有限公司 | Time delay compensation value calculation method and device |
| CN114994637A (en) * | 2022-07-28 | 2022-09-02 | 北京一径科技有限公司 | Programmable logic device configuration and programmable logic device |
| WO2023061071A1 (en) * | 2021-10-15 | 2023-04-20 | 国开启科量子技术(北京)有限公司 | Method and apparatus for measuring time |
| CN117170210A (en) * | 2023-09-07 | 2023-12-05 | 中国科学院近代物理研究所 | FPGA-based tap delay chain type TDC |
| CN117170210B (en) * | 2023-09-07 | 2024-04-26 | 中国科学院近代物理研究所 | FPGA-based tap delay chain type TDC |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102621878A (en) * | 2012-01-04 | 2012-08-01 | 西安近代化学研究所 | High-precision time interval measurement device |
| CN102736511A (en) * | 2011-04-06 | 2012-10-17 | 中国科学院高能物理研究所 | Time measurement system and time measurement method |
| WO2014191782A1 (en) * | 2013-05-31 | 2014-12-04 | Cserey György Gábor | Device and method for determining timing of a measured signal |
| CN104216279A (en) * | 2014-09-23 | 2014-12-17 | 西安宏泰时频技术有限公司 | Time interval measuring device based on FPGA (Field Programmable Gate Array) |
| CN205080373U (en) * | 2015-08-06 | 2016-03-09 | 广西电网有限责任公司电力科学研究院 | Accurate time interval measuring circuit based on delay line interpolation method |
| CN107728460A (en) * | 2017-10-27 | 2018-02-23 | 西安电子科技大学 | A kind of high-resolution time interval measurement method |
| CN109286463A (en) * | 2018-12-05 | 2019-01-29 | 北京中创为南京量子通信技术有限公司 | A kind of high precision time measurement method based on FPGA |
-
2019
- 2019-07-22 CN CN201910661291.1A patent/CN110442012A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102736511A (en) * | 2011-04-06 | 2012-10-17 | 中国科学院高能物理研究所 | Time measurement system and time measurement method |
| CN102621878A (en) * | 2012-01-04 | 2012-08-01 | 西安近代化学研究所 | High-precision time interval measurement device |
| WO2014191782A1 (en) * | 2013-05-31 | 2014-12-04 | Cserey György Gábor | Device and method for determining timing of a measured signal |
| CN104216279A (en) * | 2014-09-23 | 2014-12-17 | 西安宏泰时频技术有限公司 | Time interval measuring device based on FPGA (Field Programmable Gate Array) |
| CN205080373U (en) * | 2015-08-06 | 2016-03-09 | 广西电网有限责任公司电力科学研究院 | Accurate time interval measuring circuit based on delay line interpolation method |
| CN107728460A (en) * | 2017-10-27 | 2018-02-23 | 西安电子科技大学 | A kind of high-resolution time interval measurement method |
| CN109286463A (en) * | 2018-12-05 | 2019-01-29 | 北京中创为南京量子通信技术有限公司 | A kind of high precision time measurement method based on FPGA |
Non-Patent Citations (2)
| Title |
|---|
| 刘东斌: "基于FPGA高精度时间间隔测量系统的设计与实现", 《弹箭与制导学报》 * |
| 范晓东: "精密时间间隔测量系统方案设计", 《无线电工程》 * |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111061145A (en) * | 2019-12-30 | 2020-04-24 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| CN111007520A (en) * | 2019-12-30 | 2020-04-14 | 中国科学院微电子研究所 | Multi-channel time measuring system and method based on FPGA and laser scanner |
| CN111061145B (en) * | 2019-12-30 | 2022-07-05 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| CN111679569A (en) * | 2020-06-16 | 2020-09-18 | 中国科学院国家授时中心 | Time interval measuring system and method based on mismatched transmission lines |
| CN112506031B (en) * | 2020-11-30 | 2021-09-21 | 中国计量科学研究院 | High-precision time interval measuring system for laser interference fringe signals |
| CN112506031A (en) * | 2020-11-30 | 2021-03-16 | 中国计量科学研究院 | High-precision time interval measuring system for laser interference fringe signals |
| CN113271168A (en) * | 2021-04-26 | 2021-08-17 | 广西电网有限责任公司桂林供电局 | Power distribution network clock synchronization implementation method based on satellite common view |
| WO2022227382A1 (en) * | 2021-04-29 | 2022-11-03 | 上海科技大学 | Full-path-supported circuit delay measurer for fpga, and measurement method |
| US11762015B2 (en) | 2021-04-29 | 2023-09-19 | Shanghaitech University | Full-path circuit delay measurement device for field-programmable gate array (FPGA) and measurement method |
| CN113125944A (en) * | 2021-04-29 | 2021-07-16 | 上海科技大学 | Circuit delay detector for FPGA (field programmable Gate array) supporting full path and detection method |
| CN113125944B (en) * | 2021-04-29 | 2023-06-02 | 上海科技大学 | Circuit delay detector and detection method for FPGA supporting full path |
| CN113328745A (en) * | 2021-05-24 | 2021-08-31 | 黑龙江省计量检定测试研究院 | Time interval measuring system and method |
| CN113625050A (en) * | 2021-08-13 | 2021-11-09 | 安徽中金码电子科技有限公司 | High-precision pulse repetition interval measuring device and method based on interpolation method |
| CN113934132A (en) * | 2021-10-12 | 2022-01-14 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| CN113934132B (en) * | 2021-10-12 | 2022-05-27 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| WO2023061071A1 (en) * | 2021-10-15 | 2023-04-20 | 国开启科量子技术(北京)有限公司 | Method and apparatus for measuring time |
| CN113655702A (en) * | 2021-10-20 | 2021-11-16 | 南京宏泰半导体科技有限公司 | Self-adaptive carry delay chain coefficient adjusting system and method based on FPGA (field programmable Gate array) test |
| CN114513196A (en) * | 2022-01-17 | 2022-05-17 | 烽火通信科技股份有限公司 | Time delay compensation value calculation method and device |
| CN114994637B (en) * | 2022-07-28 | 2022-11-15 | 北京一径科技有限公司 | Programmable logic device configuration and programmable logic device |
| CN114994637A (en) * | 2022-07-28 | 2022-09-02 | 北京一径科技有限公司 | Programmable logic device configuration and programmable logic device |
| CN117170210A (en) * | 2023-09-07 | 2023-12-05 | 中国科学院近代物理研究所 | FPGA-based tap delay chain type TDC |
| CN117170210B (en) * | 2023-09-07 | 2024-04-26 | 中国科学院近代物理研究所 | FPGA-based tap delay chain type TDC |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110442012A (en) | A kind of precision time interval measurement method and system based on FPGA | |
| CN101976037B (en) | Method and device for measuring time intervals of repeated synchronous interpolation simulation | |
| CN103197145B (en) | Method and system of ultrahigh resolution phase difference measurement | |
| CN107643674B (en) | Vernier type TDC circuit based on FPGA carry chain | |
| CN101871968B (en) | Reliable time scale pulse measurement method and measurement device thereof | |
| CN108599743A (en) | A kind of precision digital delay synchronous method based on phase compensation | |
| CN106301656B (en) | A kind of method and device for improving timestamp measurement accuracy | |
| CN105656456B (en) | Circuit and pulse generating method occur for a kind of high-speed, high precision digit pulse | |
| CN107436383B (en) | A kind of high-precision pulse signal time difference measuring device and measurement method | |
| CN102880071B (en) | Data acquisition system with high time stamp accuracy | |
| CN113092858B (en) | High-precision frequency scale comparison system and comparison method based on time-frequency information measurement | |
| CN110515292A (en) | TDC circuit and measurement method based on way traffic annular carry chain | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN110703583A (en) | Multi-channel high-precision wide-range time-to-digital converter based on SOC (system on chip) | |
| CN106597097A (en) | High-precision frequency measurement method | |
| CN102664701A (en) | System and method for dynamically adjusting multichannel and wide-range clock transmission delay | |
| CN102104384B (en) | Differential delay chain unit and time-to-digital converter comprising same | |
| CN108736885B (en) | Phase-locked loop clock edge triggered clock phase-splitting method | |
| CN109444856B (en) | Integer period measuring circuit applied to high-resolution time-to-digital converter | |
| CN108732912A (en) | The clock phase-splitting method of measured signal edging trigger | |
| CN113391333A (en) | Big dipper high accuracy time synchronization chip based on different frequency crowd quantization phase handles | |
| CN108768388A (en) | The clock phase-splitting method that phaselocked loop clock edge of connecting triggers | |
| CN108061885A (en) | The implementation method of multi-channel laser Fuze target feature recognition signal processing circuit | |
| CN101299609B (en) | Phase discriminator, phase demodulation method and phase-locked loop | |
| TW201303533A (en) | Method and system for measuring distance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191112 |