CN102104384B - Differential delay chain unit and time-to-digital converter comprising same - Google Patents
Differential delay chain unit and time-to-digital converter comprising same Download PDFInfo
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- CN102104384B CN102104384B CN2009103118466A CN200910311846A CN102104384B CN 102104384 B CN102104384 B CN 102104384B CN 2009103118466 A CN2009103118466 A CN 2009103118466A CN 200910311846 A CN200910311846 A CN 200910311846A CN 102104384 B CN102104384 B CN 102104384B
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Abstract
The invention discloses a differential delay chain unit and a time-to-digital converter comprising the same. The differential delay chain unit comprises a first NAND gate circuit, a trigger and a second NAND gate circuit, wherein the first input end of the first NAND gate circuit is connected with a high level; the second input end is connected to the first input end of the trigger and the output end of the first NAND gate circuit of a higher-level differential delay chain unit; the first input end of the trigger is connected to the second input end of the first NAND gate circuit; the second input end of the trigger is connected to the second input end of the second NAND gate circuit, wherein the first input end and the second input end of the trigger are differential input ends; the first input end of the second NAND gate circuit is connected to the high level; and the second input end of the second NAND gate circuit is connected to the second input end of the trigger and the output end of the second NAND gate circuit of the higher-level differential delay chain unit. The differential delay chain unit can realize accurate measurement on time intervals, and realize a high-precision time-digital converter.
Description
Technical field
The present invention relates generally to measurement and control area, relates to more specifically a kind of differential delay chain unit and comprises its time-to-digit converter.
Background technology
Time interval measurement is a focus of modern information technology research.Time interval measurement is widely used in the various fields such as the rotational speed detector, tensometer, magneto strictive sensor, time-of-flight spectrometer of the high-precision laser range-finding instrument that comprises ultrasonic flow instrument, high-energy physics and nuclear physics, various hand-held/airborne or steady job, laser radar, laser scanner, cdma wireless cellular system wireless location, ultrasonic densimeter, ultrasonic thickness instrument, turbocharger, and also all will use time interval measurement in high precision measurement fields such as the observation of astronomical time interval, frequency and phase signal analyses.Time measuring unit TDC (Time-to-digital converters) is the means of a kind of measuring intervals of TIME of adopting at present extensively, and it adopts is the pulse counting method of traditional ranging pulse width.But, when the time difference that rising is surveyed or decline is surveyed of two pulses is tens to hundreds of ns, traditional pulse counting method is no longer applicable, this is because the pulse that will measure is narrower, and needed clock frequency just heals high, also higher to the performance requirement of chip.For example, while requiring the measure error of 1ns, clock frequency just need to be brought up to 1GHz, and in this case, general counter chip is difficult to normal operation, and the while also can bring the problems such as wiring complexity, material selection difficulty and the difficulty of processing of circuit board is large.
For overcoming the problems referred to above, the TDC measuring unit utilizes signal to provide a kind of new time interval measurement method by the absolute transmission time of logic gates, the number of the time interval by gate decides, and can be easy to realize the method in integrated circuit technology.But for very little time interval measurement, for example, after quantizing, be the time interval measurement of mark, existing TDC measuring unit can not be measured exactly.Therefore, need a kind of solution of new measuring intervals of TIME, and then solve the problem in above-mentioned correlation technique.
Summary of the invention
The object of the present invention is to provide a kind of technical scheme of measuring intervals of TIME, solve in prior art and can not carry out the problem of accurately measuring to the time interval.
According to a first aspect of the invention, provide a kind of differential delay chain unit, having comprised:
The first NAND gate circuit, its first input end connects high level, the second input is connected to the output of the first NAND gate circuit of the first input end of trigger and upper level differential delay chain unit, and its output is connected to the second input of the first NAND gate circuit of next stage differential delay chain unit;
Trigger, its first input end is connected to the second input of the first NAND gate circuit, and its second input is connected to the second input of the second NAND gate circuit;
The second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of the second NAND gate circuit of the second input of trigger and upper level differential delay chain unit, and its output is connected to the second input of the second NAND gate circuit of next stage differential delay chain unit;
Wherein, this trigger is d type flip flop.
Wherein, the first NAND gate circuit and the second NAND gate circuit include a PMOS transistor and the 2nd PMOS transistor, and the first nmos pass transistor and the second nmos pass transistor.
Wherein, the grid of the transistorized grid of the one PMOS and the first nmos pass transistor is connected to the first input end of the first NAND gate, the transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are connected to high level, the transistorized drain electrode of the one PMOS and the transistorized drain electrode of the 2nd PMOS are connected to the source electrode of the first nmos pass transistor, the grid of the transistorized grid of the 2nd PMOS and the second nmos pass transistor is connected to the second input of the first NAND gate, the first nmos transistor drain is connected to the source electrode of the second nmos pass transistor, and the grounded drain of the second nmos pass transistor.
According to another aspect of the present invention, provide a kind of time-to-digit converter, comprised a plurality of differential delay chains unit, it is characterized in that, each differential delay chain unit includes:
The first NAND gate circuit, its first input end connects high level, the second input is connected to the output of the first NAND gate circuit of the first input end of trigger and upper level differential delay chain unit, and its output is connected to the second input of the first NAND gate circuit of next stage differential delay chain unit;
Trigger, its first input end is connected to the second input of the first NAND gate circuit, and its second input is connected to the second input of the second NAND gate circuit;
The second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of the second NAND gate circuit of the second input of trigger and upper level differential delay chain unit, its output is connected to the second input of the second NAND gate circuit of next stage differential delay chain unit
Wherein, trigger is d type flip flop.
The present invention can realize the accurate measurement to the time interval, and has realized high-precision time-to-digit converter.
The accompanying drawing explanation
Fig. 1 is the differential delay chain unit according to the embodiment of the present invention;
Fig. 2 is the NAND gate circuit of the standard cmos for the differential delay chain unit schematic diagram according to the embodiment of the present invention;
Fig. 3 a and Fig. 3 b are electric discharge equivalent model corresponding to the other end during according to one of them input termination high level of the standard cmos NAND gate of the embodiment of the present invention;
Fig. 4 a and Fig. 4 b are charging equivalent model corresponding to the other end during according to one of them input termination high level of the standard cmos NAND gate of the embodiment of the present invention
Embodiment
Describe embodiments of the invention in detail below in conjunction with accompanying drawing.
For all-digital phase-locked loop, reference clock signal phase place and oscillator output signal phase place all will be quantized, and the result after quantification is a real number, comprises integer part and fractional part.The quantification ratio of integer part is easier to realize, but that the quantification of fractional part just seems is more complex.The quantification of fractional phase adopts TDC time-to-digit converter of the present invention to realize.By introducing a less time base unit, reach the purpose at quantization time interval in this time-to-digit converter.Time-to-digit converter in the present invention is the differential configuration that the basic logic unit chain that do not wait by two unit time delays is realized, the unit gate delay that the time quantization precision that it can reach is this two one time delay chain poor.
In order better to set forth content of the present invention, employing as next preferred embodiment describe.
As shown in Figure 1, be a specific embodiment of differential delay chain of the present invention unit.This differential delay chain unit consists of trigger and two NAND gate of a difference input.Wherein the trigger 106 of difference input comprises a pair of differential input end, an input end of clock and an output.Two NAND gate, in size, are complete same on domain.Wherein the IN1 of the first NAND gate circuit 102 inputs the output of the corresponding NAND gate of termination previous stage, and the IN2 input termination of the first NAND gate circuit 102 is high level fixedly.And the output of the corresponding NAND gate of the IN2 ' input termination previous stage of the second NAND gate circuit 104, the IN1 ' input termination of the second NAND gate circuit 104 is high level fixedly.
Wherein, the IN1 input of the first NAND gate circuit 102 of the differential delay chain unit of the first order and the IN2 ' input of the second NAND gate circuit 104 are inputted respectively two paths of signals to be compared, and the clock signal of differential delay chains at different levels unit is identical, and wherein, according to the output of triggers at different levels, determine the time difference between two paths of signals to be compared.The cascade of a plurality of unit can form a differential delay chain time-digital converter.
Fig. 2 has provided the circuit diagram of standard NAND gate.Can find out, above two PMOS are environment facies with, each terminal connection of two PMOS is identical, but following two residing environment of NMOS are different, i.e. each terminal connection difference of two NMOS.When input IN1 by this NAND gate or IN2 fixedly connect high level, it all is equivalent to an inverter on function.But the transmission delay of these two connections is differentiated.Concrete, the grid of the transistorized grid of the one PMOS and the first nmos pass transistor is connected to the first input end of NAND gate, the transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are connected to high level, the transistorized drain electrode of the one PMOS and the transistorized drain electrode of the 2nd PMOS are connected to the source electrode of the first nmos pass transistor, the grid of the transistorized grid of the 2nd PMOS and the second nmos pass transistor is connected to the second input of NAND gate, the first nmos transistor drain is connected to the source electrode of the second nmos pass transistor, and the grounded drain of the second nmos pass transistor.Fig. 3 a, Fig. 3 b and Fig. 4 a, Fig. 4 b have provided respectively the digital equivalent circuit analysis model of two kinds of connections at charge and discharge process.Can find out under both of these case that it is differentiated discharging and recharging path, thereby cause the difference in time delay.The temporal resolution of gained differential delay chain is the poor of these two time delays.
Preferably, time-to-digit converter is the differential configuration that utilizes basic logic unit chain that two unit time delays do not wait to realize, the unit gate delay that the time quantization precision that it can reach is this two one time delay chain poor.
By the present invention, realized the precise time interval measurement and realized high-precision time-to-digit converter.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (2)
1. a differential delay chain unit, is characterized in that, comprising:
The first NAND gate circuit, its first input end connects high level, the second input is connected to the output of the first NAND gate circuit of the first input end of trigger and upper level differential delay chain unit, and its output is connected to the second input of the first NAND gate circuit of next stage differential delay chain unit;
Described trigger, its first input end is connected to the second input of described the first NAND gate circuit, and its second input is connected to the second input of the second NAND gate circuit;
The second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of the second NAND gate circuit of the second input of described trigger and upper level differential delay chain unit, its output is connected to the second input of the second NAND gate circuit of next stage differential delay chain unit
Wherein, described trigger is d type flip flop;
Described the first NAND gate circuit and described the second NAND gate circuit include a PMOS transistor and the 2nd PMOS transistor, and the first nmos pass transistor and the second nmos pass transistor;
The grid of the transistorized grid of a described PMOS and described the first nmos pass transistor is connected to the first input end of described the first NAND gate, the transistorized source electrode of a described PMOS and the transistorized source electrode of described the 2nd PMOS are connected to high level, the transistorized drain electrode of a described PMOS and the transistorized drain electrode of described the 2nd PMOS are connected to the source electrode of described the first nmos pass transistor, the grid of the transistorized grid of described the 2nd PMOS and described the second nmos pass transistor is connected to the second input of described the first NAND gate, described the first nmos transistor drain is connected to the source electrode of described the second nmos pass transistor, and the grounded drain of described the second nmos pass transistor.
2. a time-to-digit converter, comprise a plurality of differential delay chains unit, it is characterized in that, each described differential delay chain unit includes:
The first NAND gate circuit, its first input end connects high level, the second input is connected to the output of the first NAND gate circuit of the first input end of trigger and upper level differential delay chain unit, and its output is connected to the second input of the first NAND gate circuit of next stage differential delay chain unit;
Described trigger, its first input end is connected to the second input of described the first NAND gate circuit, and its second input is connected to the second input of the second NAND gate circuit;
The second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of the second NAND gate circuit of the second input of described trigger and upper level differential delay chain unit, its output is connected to the second input of the second NAND gate circuit of next stage differential delay chain unit
Wherein, described trigger is d type flip flop;
Described the first NAND gate circuit and described the second NAND gate circuit include a PMOS transistor and the 2nd PMOS transistor, and the first nmos pass transistor and the second nmos pass transistor;
The grid of the transistorized grid of a described PMOS and described the first nmos pass transistor is connected to the first input end of described the first NAND gate, the transistorized source electrode of a described PMOS and the transistorized source electrode of described the 2nd PMOS are connected to high level, the transistorized drain electrode of a described PMOS and the transistorized drain electrode of described the 2nd PMOS are connected to the source electrode of described the first nmos pass transistor, the grid of the transistorized grid of described the 2nd PMOS and described the second nmos pass transistor is connected to the second input of described the first NAND gate, described the first nmos transistor drain is connected to the source electrode of described the second nmos pass transistor, and the grounded drain of described the second nmos pass transistor.
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| CN103516367B (en) * | 2012-06-20 | 2016-09-28 | 中国科学院电子学研究所 | A kind of time-to-digit converter |
| CN103580696B (en) * | 2012-08-06 | 2016-11-16 | 复旦大学 | A kind of time deviation selection circuit |
| CN104154851A (en) * | 2014-08-14 | 2014-11-19 | 河海大学常州校区 | Method for measuring time difference proportional displacement of magnetostrictive sensor |
| CN108333910B (en) * | 2018-05-02 | 2019-12-31 | 晶晨半导体(上海)股份有限公司 | Novel time-to-digital converter |
| CN110086472B (en) * | 2019-04-23 | 2023-03-07 | 西安微电子技术研究所 | Digital timer topological structure and control method thereof |
| CN110865057B (en) * | 2019-11-06 | 2022-04-08 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101499790A (en) * | 2008-01-28 | 2009-08-05 | 财团法人工业技术研究院 | Signal delay circuit |
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| CN101499790A (en) * | 2008-01-28 | 2009-08-05 | 财团法人工业技术研究院 | Signal delay circuit |
Non-Patent Citations (3)
| Title |
|---|
| "基于FPGA高精度时间间隔测量系统的设计与实现";刘东斌等;《弹箭与制导学报》;20090430;第29卷(第2期);第299-302页 * |
| US 7,205,924 B2,2007.04.17,说明书分栏9第44-50行，图5. |
| 刘东斌等."基于FPGA高精度时间间隔测量系统的设计与实现".《弹箭与制导学报》.2009,第29卷(第2期),第299-302页. |
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Effective date of registration: 20220909 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Institute of Microelectronics Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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