CN102104384A - Differential delay chain unit and time-to-digital converter comprising same - Google Patents
Differential delay chain unit and time-to-digital converter comprising same Download PDFInfo
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- CN102104384A CN102104384A CN2009103118466A CN200910311846A CN102104384A CN 102104384 A CN102104384 A CN 102104384A CN 2009103118466 A CN2009103118466 A CN 2009103118466A CN 200910311846 A CN200910311846 A CN 200910311846A CN 102104384 A CN102104384 A CN 102104384A
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Abstract
The invention discloses a differential delay chain unit and a time-to-digital converter comprising the same. The differential delay chain unit comprises a first NAND gate circuit, a trigger and a second NAND gate circuit, wherein the first input end of the first NAND gate circuit is connected with a high level; the second input end is connected to the first input end of the trigger and the output end of the first NAND gate circuit of a higher-level differential delay chain unit; the first input end of the trigger is connected to the second input end of the first NAND gate circuit; the second input end of the trigger is connected to the second input end of the second NAND gate circuit, wherein the first input end and the second input end of the trigger are differential input ends; the first input end of the second NAND gate circuit is connected to the high level; and the second input end of the second NAND gate circuit is connected to the second input end of the trigger and the output end of the second NAND gate circuit of the higher-level differential delay chain unit. The differential delay chain unit can realize accurate measurement on time intervals, and realize a high-precision time-digital converter.
Description
Technical field
The present invention relates generally to measurement and control area, relates to a kind of difference time delay chain unit more specifically and comprises its time-to-digit converter.
Background technology
Time interval measurement is a focus of contemporary information technology research.Time interval measurement be widely used in comprise ultrasonic flow instrument, high-energy physics and nuclear physics, various hand-held/various fields such as the measurement of rotating speed instrument of the high-precision laser range-finding instrument of airborne or steady job, laser radar, laser scanner, cdma wireless cellular system wireless location, ultrasonic wave density instrument, ultrasonic thickness instrument, turbocharger, tensometer, magneto strictive sensor, time-of-flight spectrometer, and also all to use time interval measurement in high precision measurement fields such as astronomical time observation at interval, frequency and phase signal analyses.Time measuring unit TDC (Time-to-digital converters) is the means of a kind of measuring intervals of TIME of adopting at present extensively, and it adopts is the pulse counting method of traditional measurement pulse duration.But when the time difference that rising is surveyed or decline is surveyed of two pulses was tens to hundreds of ns, traditional pulse counting method was no longer suitable, and this is because the pulse that will measure is narrow more, and needed clock frequency just heals high, and is also high more to the performance requirement of chip.For example, when requiring the measure error of 1ns, clock frequency just need be brought up to 1GHz, and in this case, general counter chip is difficult to operate as normal, and the while also can bring problems such as wiring complexity, material selection difficulty and the difficulty of processing of circuit board is big.
For overcoming the problems referred to above, the TDC measuring unit utilizes signal to provide a kind of new time interval measurement method by the absolute transmission time of logic gates, the number of the time interval by gate decides, and can be easy to realize this method in integrated circuit technology.But for very little time interval measurement, for example quantizing the back is the time interval measurement of mark, and existing TDC measuring unit can not be measured exactly.Therefore, need a kind of solution of new measuring intervals of TIME, and then solve the problem in the above-mentioned correlation technique.
Summary of the invention
The object of the present invention is to provide a kind of technical scheme of measuring intervals of TIME, solve in the prior art problem that can not accurately measure the time interval.
According to a first aspect of the invention, provide a kind of difference time delay chain unit, having comprised:
First NAND gate circuit, its first input end connects high level, second input is connected to the output of first NAND gate circuit of the first input end of trigger and upper level difference time delay chain unit, and its output is connected to second input of first NAND gate circuit of next stage difference time delay chain unit;
Trigger, its first input end are connected to second input of first NAND gate circuit, and its second input is connected to second input of second NAND gate circuit;
Second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of second NAND gate circuit of second input of trigger and upper level difference time delay chain unit, and its output is connected to second input of second NAND gate circuit of next stage difference time delay chain unit;
Wherein, this trigger is a d type flip flop.
Wherein, first NAND gate circuit and second NAND gate circuit include a PMOS transistor and the 2nd PMOS transistor, and first nmos pass transistor and second nmos pass transistor.
Wherein, the grid of the transistorized grid of the one PMOS and first nmos pass transistor is connected to the first input end of first NAND gate, transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are connected to high level, the one PMOS transistor drain and the 2nd PMOS transistor drain are connected to the source electrode of first nmos pass transistor, the grid of the transistorized grid of the 2nd PMOS and second nmos pass transistor is connected to second input of first NAND gate, first nmos transistor drain is connected to the source electrode of second nmos pass transistor, and the grounded drain of second nmos pass transistor.
According to another aspect of the present invention, provide a kind of time-to-digit converter, comprised a plurality of difference time delay chains unit, it is characterized in that, each difference time delay chain unit includes:
First NAND gate circuit, its first input end connects high level, second input is connected to the output of first NAND gate circuit of the first input end of trigger and upper level difference time delay chain unit, and its output is connected to second input of first NAND gate circuit of next stage difference time delay chain unit;
Trigger, its first input end are connected to second input of first NAND gate circuit, and its second input is connected to second input of second NAND gate circuit;
Second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of second NAND gate circuit of second input of trigger and upper level difference time delay chain unit, its output is connected to second input of second NAND gate circuit of next stage difference time delay chain unit
Wherein, trigger is a d type flip flop.
The present invention can realize the accurate measurement to the time interval, and has realized the high precision time digital quantizer.
Description of drawings
Fig. 1 is the difference time delay chain unit according to the embodiment of the invention;
Fig. 2 is the standard cmos NAND gate circuit schematic diagram that is used for difference time delay chain unit according to the embodiment of the invention;
Fig. 3 a and Fig. 3 b are the discharge equivalent models of other end correspondence during according to one of them input termination high level of the standard cmos NAND gate of the embodiment of the invention;
Fig. 4 a and Fig. 4 b are the charging equivalent models of other end correspondence during according to one of them input termination high level of the standard cmos NAND gate of the embodiment of the invention
Embodiment
Describe embodiments of the invention in detail below in conjunction with accompanying drawing.
For all-digital phase-locked loop, reference clock signal phase place and oscillator output signal phase place all will quantize, and the result after the quantification is a real number, comprises integer part and fractional part.The quantification ratio of integer part is easier to realize, but the quantification of fractional part just seems complicated.The quantification of fractional phase adopts TDC time-to-digit converter of the present invention to realize.By introducing a littler time base unit, reach quantization time purpose at interval in this time-to-digit converter.Time-to-digit converter among the present invention is the differential configuration of realizing by the basic logic unit chain that the time-delay of two units does not wait, and the time quantization precision that it can reach is unit gate delay poor of this two one time delay chain.
Describe in order better to set forth content of the present invention, to adopt as next preferred embodiment.
As shown in Figure 1, be a specific embodiment of difference time delay chain of the present invention unit.This difference time delay chain unit is made of trigger and two NAND gate of a difference input.Wherein the trigger 106 of difference input comprises a pair of differential input end, an input end of clock and an output.Two NAND gate are complete same on the domain in size.Wherein the IN1 of first NAND gate circuit 102 imports the output of the corresponding NAND gate of termination previous stage, and the IN2 input termination of first NAND gate circuit 102 is high level fixedly.And the output of the corresponding NAND gate of the IN2 ' input termination previous stage of second NAND gate circuit 104, the IN1 ' input termination of second NAND gate circuit 104 is high level fixedly.
Wherein, the IN1 input of first NAND gate circuit 102 of the difference time delay chain unit of the first order and the IN2 ' input of second NAND gate circuit 104 are imported two paths of signals to be compared respectively, and the clock signal of difference time delay chains at different levels unit is identical, and wherein, determine time difference between the two paths of signals to be compared according to the output of triggers at different levels.The cascade of a plurality of unit can constitute a difference time delay chain time-to-digit converter.
Fig. 2 has provided the circuit diagram of standard NAND gate.As can be seen, above two PMOS are environment facies with, promptly each terminal connection of two PMOS is identical, but following two residing environment of NMOS are different, i.e. each terminal connection difference of two NMOS.When input IN1 of this NAND gate or IN2 were fixedly connect high level, it all was equivalent to an inverter on function.But the transmission delay of these two connections is differentiated.Concrete, the grid of the transistorized grid of the one PMOS and first nmos pass transistor is connected to the first input end of NAND gate, transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are connected to high level, the one PMOS transistor drain and the 2nd PMOS transistor drain are connected to the source electrode of first nmos pass transistor, the grid of the transistorized grid of the 2nd PMOS and second nmos pass transistor is connected to second input of NAND gate, first nmos transistor drain is connected to the source electrode of second nmos pass transistor, and the grounded drain of second nmos pass transistor.Fig. 3 a, Fig. 3 b and Fig. 4 a, Fig. 4 b have provided the digital equivalent circuit analysis model of two kinds of connections at charge and discharge process respectively.It is differentiated discharging and recharging the path as can be seen under the both of these case, thus the difference on causing delaying time.The temporal resolution of gained difference time delay chain is the poor of these two time-delays.
Preferably, time-to-digit converter is the differential configuration that the basic logic unit chain that utilizes the time-delay of two units not to wait is realized, the time quantization precision that it can reach is unit gate delay poor of this two one time delay chain.
By the present invention, realized the precise time interval measurement and realized the high precision time digital quantizer.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a difference time delay chain unit is characterized in that, comprising:
First NAND gate circuit, its first input end connects high level, second input is connected to the output of first NAND gate circuit of the first input end of trigger and upper level difference time delay chain unit, and its output is connected to second input of first NAND gate circuit of next stage difference time delay chain unit;
Described trigger, its first input end are connected to second input of described first NAND gate circuit, and its second input is connected to second input of second NAND gate circuit;
Second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of second NAND gate circuit of second input of described trigger and upper level difference time delay chain unit, its output is connected to second input of second NAND gate circuit of next stage difference time delay chain unit
Wherein, described trigger is a d type flip flop.
2. difference time delay chain according to claim 1 unit is characterized in that, described first NAND gate circuit and described second NAND gate circuit include a PMOS transistor and the 2nd PMOS transistor, and first nmos pass transistor and second nmos pass transistor.
3. difference time delay chain according to claim 2 unit, it is characterized in that, the grid of transistorized grid of a described PMOS and described first nmos pass transistor is connected to the first input end of described first NAND gate, transistorized source electrode of a described PMOS and the transistorized source electrode of described the 2nd PMOS are connected to high level, a described PMOS transistor drain and described the 2nd PMOS transistor drain are connected to the source electrode of described first nmos pass transistor, the grid of transistorized grid of described the 2nd PMOS and described second nmos pass transistor is connected to second input of described first NAND gate, described first nmos transistor drain is connected to the source electrode of described second nmos pass transistor, and the grounded drain of described second nmos pass transistor.
4. a time-to-digit converter comprises a plurality of difference time delay chains unit, it is characterized in that, each described difference time delay chain unit includes:
First NAND gate circuit, its first input end connects high level, second input is connected to the output of first NAND gate circuit of the first input end of trigger and upper level difference time delay chain unit, and its output is connected to second input of first NAND gate circuit of next stage difference time delay chain unit;
Described trigger, its first input end are connected to second input of described first NAND gate circuit, and its second input is connected to second input of second NAND gate circuit;
Second NAND gate circuit, its first input end is connected to high level, its second input is connected to the output of second NAND gate circuit of second input of described trigger and upper level difference time delay chain unit, its output is connected to second input of second NAND gate circuit of next stage difference time delay chain unit
Wherein, described trigger is a d type flip flop.
5. difference time delay chain according to claim 4 unit is characterized in that, described first NAND gate circuit and described second NAND gate circuit include a PMOS transistor and the 2nd PMOS transistor, and first nmos pass transistor and second nmos pass transistor.
6. difference time delay chain according to claim 5 unit, it is characterized in that, the grid of transistorized grid of a described PMOS and described first nmos pass transistor is connected to the first input end of described first NAND gate, transistorized source electrode of a described PMOS and the transistorized source electrode of described the 2nd PMOS are connected to high level, a described PMOS transistor drain and described the 2nd PMOS transistor drain are connected to the source electrode of described first nmos pass transistor, the grid of transistorized grid of described the 2nd PMOS and described second nmos pass transistor is connected to second input of described first NAND gate, described first nmos transistor drain is connected to the source electrode of described second nmos pass transistor, and the grounded drain of described second nmos pass transistor.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516367A (en) * | 2012-06-20 | 2014-01-15 | 中国科学院电子学研究所 | Time-to-digital converter |
| CN103580696A (en) * | 2012-08-06 | 2014-02-12 | 复旦大学 | Time deviation selection circuit |
| CN104154851A (en) * | 2014-08-14 | 2014-11-19 | 河海大学常州校区 | Method for measuring time difference proportional displacement of magnetostrictive sensor |
| CN110086472A (en) * | 2019-04-23 | 2019-08-02 | 西安微电子技术研究所 | A kind of digital clock topological structure and its control method |
| WO2019210642A1 (en) * | 2018-05-02 | 2019-11-07 | 晶晨半导体(上海)股份有限公司 | Novel time-to-digital converter |
| CN110865057A (en) * | 2019-11-06 | 2020-03-06 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101499790B (en) * | 2008-01-28 | 2012-06-27 | 财团法人工业技术研究院 | Signal delay circuit |
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2009
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516367A (en) * | 2012-06-20 | 2014-01-15 | 中国科学院电子学研究所 | Time-to-digital converter |
| CN103516367B (en) * | 2012-06-20 | 2016-09-28 | 中国科学院电子学研究所 | A kind of time-to-digit converter |
| CN103580696A (en) * | 2012-08-06 | 2014-02-12 | 复旦大学 | Time deviation selection circuit |
| CN103580696B (en) * | 2012-08-06 | 2016-11-16 | 复旦大学 | A kind of time deviation selection circuit |
| CN104154851A (en) * | 2014-08-14 | 2014-11-19 | 河海大学常州校区 | Method for measuring time difference proportional displacement of magnetostrictive sensor |
| WO2019210642A1 (en) * | 2018-05-02 | 2019-11-07 | 晶晨半导体(上海)股份有限公司 | Novel time-to-digital converter |
| US11275344B2 (en) | 2018-05-02 | 2022-03-15 | Amlogic (Shanghai) Co., Ltd. | Time to digital converter |
| CN110086472A (en) * | 2019-04-23 | 2019-08-02 | 西安微电子技术研究所 | A kind of digital clock topological structure and its control method |
| CN110086472B (en) * | 2019-04-23 | 2023-03-07 | 西安微电子技术研究所 | Digital timer topological structure and control method thereof |
| CN110865057A (en) * | 2019-11-06 | 2020-03-06 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
| CN110865057B (en) * | 2019-11-06 | 2022-04-08 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
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Effective date of registration: 20220909 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Institute of Microelectronics Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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