CN103516367B - A kind of time-to-digit converter - Google Patents
A kind of time-to-digit converter Download PDFInfo
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- CN103516367B CN103516367B CN201210211299.6A CN201210211299A CN103516367B CN 103516367 B CN103516367 B CN 103516367B CN 201210211299 A CN201210211299 A CN 201210211299A CN 103516367 B CN103516367 B CN 103516367B
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Abstract
The invention provides a kind of time-to-digit converter, described transducer comprises rough detection circuit, interface circuit and examining slowdown monitoring circuit, wherein: rough detection circuit is ring-type by being designed to by delay line, and ruling therein is unit multiplexed does delay cell, simultaneously by means of enumerator, finally achieve the time figure conversion of big input range；Interface circuit is for being delivered to examining slowdown monitoring circuit by the time margin that rough detection circuit produces；Examining slowdown monitoring circuit makes the difference on the frequency of two agitators in differential ring oscillator be to fix small value by the grid oxygen electric capacity of regulation field effect transistor, thus realizes the conversion of precision adjustable high-precision time figure.In a word, by above three module, the time-to-digit converter in the present invention can carry out the conversion of high-precision large-range with less area overhead to time interval.
Description
Technical field
The invention belongs to time measurement technology field, relate to a kind of high-precision large-range time figure conversion
Device.
Background technology
The measure of time of high-precision large-range as a kind of critical technology in numerous areas by extensively
General application, such as laser ranging (LRF), navigational communications, high-energy physics experiment, satellite monitoring,
The fields such as Scientific Measurement.Accurate measure of time either national defence still civil area all can not or
Lack, and along with the development of technology, the measurement of time is just sent out towards the direction of the big input range of high accuracy
Exhibition, to meet the requirement of numerous application.
Time-to-digit converter (Time-to-Digital Converter, TDC) is a kind of by the time
Interval is converted to the device of digital output, is similar to analog-digital converter to a certain extent
(Analog-to-Digital Converter, ADC), the voltage of only ADC quantization or electricity
Stream, and TDC quantization is time interval.Up to the present, the typical method of TDC can be summarized as with
Under several: counting method, i.e. with a high frequency clock to input time interval directly count, the party
Method certainty of measurement is relatively low, and needs outside high frequency clock, usual and other there is high-precision method
With the use of；Time to voltage and voltage to digital method, as the term suggests, the method is exactly first to be measured
Time interval (form of pulse) be converted to certain voltage by means of the charging of electric capacity, then pass through
Voltage is discharged by the electric discharge of electric capacity, and circuit design makes velocity of discharge charging rate to be much smaller than, so
Time interval to be measured has obtained broadening, has just obtained to be measured with enumerator to the step-by-step counting after broadening
Temporal information, comparative counting method, the method precision is high, but owing to being Digital Analog Hybrid Circuits, has all
The accuracy that multifactor impact is measured；Tapped delay line method (Tapped Delay Line, TDL),
Theme be exactly by the edge signal arrived first often through a certain amount of delay (be exactly generally a buffering
Device or the delay of phase inverter) with rear to signal carry out a ruling, to determine elder generation during both ruling
Rear order, ruling result is 11100 ... sequence, just can learn the temporal information of input from ruling result,
The method precision is higher, but chip-area overhead is big, especially when the time interval of input is the biggest；
Differential type postpones collimation method (Vernier Delay Line, VDL), by two signal often warps to be measured
Cross a certain amount of delay (both delays are different, but postponing difference is a definite value) ruling once, to cut out
Result certainly is exactly last output result, and ratio of precision TDL of the method is taller, is common method
In precision the highest, but also big than TDL of chip-area overhead.Therefore, a kind of high-precision,
Big input range, TDC that area overhead is little become a kind of development trend.
Summary of the invention
In order to solve the prior art chips area overhead the biggest technical problem than TDL, this
Improving eyesight be to provide a kind of high accuracy, big input range, time figure converter that chip area is little,
To solve the main bugbear run in current measure of time.
For reaching above-mentioned purpose, the time-to-digit converter of the present invention is provided with:
One rough detection circuit, has port one, port two and port three, wherein: port three receives defeated
The level signal entered, for selecting different measurement ranges to different level signals；Port one and end
Mouth two is for receiving two hopping edge signals with continuous time interval of input respectively, and utilizes Rough Inspection
Two are had between the hopping edge signal of continuous print time interval by the ring-type delay line in slowdown monitoring circuit
Time interval carries out bigness scale amount, and hopping edge signal the following in ring-type delay line to port one input
Ring number of times counts, and obtains the end-state value of all ruling delay cells of ring-type delay line, obtains
Take ring-type delay line middle port one input the cycle-index count value of hopping edge signal and be taken at port
The time margin signal of two input hopping edge signals；
One interface circuit, two input connects rough detection circuit output end, receives and by described sanction
Certainly the end-state value of delay cell generates the rising edge of commencing signal, and described time margin signal is raw
Become to stop the rising edge of signal, obtain the time interval between commencing signal and the rising edge stopping signal
Time margin as rough detection circuit；
One examining slowdown monitoring circuit, has two inputs and port four, and described port four is used for receiving input
Control signal, control the certainty of measurement of examining slowdown monitoring circuit for further regulation；Said two inputs
End connects the outfan of interface circuit, receives and utilizes the differential ring oscillator pair in examining slowdown monitoring circuit
Time interval between commencing signal and the rising edge stopping signal of interface circuit output is carefully surveyed
Amount, and the cycle of oscillation of agitator in differential ring oscillator is counted, generate and export difference
Count value cycle of oscillation of agitator in ring oscillator；
One computing unit, its input outfan with the enumerator of rough detection circuit respectively be connected and
Ruling postpones outfan connection and is connected with the outfan of the enumerator of examining slowdown monitoring circuit, receives and by institute
State port one input hopping edge signal cycle-index count value in ring-type delay line, described finally
In state value and described differential ring oscillator, count value cycle of oscillation of agitator generates and exports
Digital quantity containing time interval information to be measured.
Preferred embodiment, rough detection circuit includes:
Multiple ruling delay cells, each ruling delay cell have data input pin, input end of clock,
Clear input, selection input and an outfan, described port two connects all ruling and postpones single
The data terminal of unit, the clock end of first ruling delay cell connects the outfan of circulating controling circuit；
The clock end of each ruling delay cell afterwards connects the defeated of its previous ruling delay cell
Go out end；The outfan of last ruling delay cell is connected to circulation in the way of internal feedback signal
One input of control circuit；The outfan of later ruling delay cell is connected to previous ruling
The clear terminal of delay cell；It is connected to each ruling by the level signal of described port three input prolong
The selection end of unit late, for handover measurement range；It is end to end by multiple ruling delay cells,
Constitute a ring-type delay line；Ring-type delay line is used for the time interval of input is carried out bigness scale amount,
Produce and export thick measurement result；
One circulating controling circuit, it has two inputs and an outfan, and an input is connected to
Described port one, another input is connected to the outfan of last ruling delay cell；Follow
The outfan of loop control circuit is connected to the clock end of first ruling delay cell；Loop control electricity
The edge signal that the control signal on road inputs from described port one；Circulating controling circuit is used for port one
Switching between edge signal and the ring-type delay line internal feedback signal of input；
One enumerator, its input is connected to the outfan of first ruling delay cell, is used for producing
And the cycle-index that the hopping edge signal of output port one input is in ring-type delay line.
Preferred embodiment, examining slowdown monitoring circuit includes:
One oscillation control circuit, it has three inputs, two outfans, wherein first input end and
Second input is connected to the outfan of interface circuit, for two risings of receiving interface circuit input
Along signal；3rd input is connected to the outfan of phase detecting circuit；First input end and second defeated
The signal entering end reception is edge signal or pulse signal, and oscillation control circuit shakes for producing first
Swing the multiple oscillation control signal of device and the second agitator；
First agitator, it has an input and an outfan, and its input is connected to vibration control
First outfan of circuit processed, its outfan is connected to the first input end of phase detecting circuit；First
The frequency of oscillation of agitator realizes by changing the grid oxygen electric capacity of the first agitator internal fet
Fine setting, the first agitator is used for producing the adjustable oscillator signal of frequency of oscillation；
Second agitator, it has an input and an outfan, and its input is connected to vibration control
Second outfan of circuit processed, its outfan is connected to the second input of phase detecting circuit；Second
The frequency of oscillation of agitator realizes by changing the grid oxygen electric capacity of the second agitator internal fet
Fine setting, the second agitator is used for producing the adjustable oscillator signal of frequency of oscillation；
One phase detecting circuit, it has two inputs and an outfan, wherein first input end company
Receiving the outfan of the first agitator, the second input is connected to the outfan of the second agitator, its
Outfan is connected to the 3rd input of oscillation control circuit, and phase detecting circuit shakes for detection first
Swing the phase relation between device and the produced signal of the second agitator, when phase place is consistent, phase-detection electricity
Road outputs level signals, the first agitator and the second agitator all stop oscillation；
One enumerator, for the periodicity of record the second agitator.
Preferred embodiment, the ruling delay cell in rough detection circuit is ruling unit or postpones single
Unit.
Preferred embodiment, when port three input is for high level, the measurement range of rough detection circuit is relatively big,
When port three input is for low level, the measurement range of rough detection circuit is less.
Preferred embodiment, the time margin value of rough detection circuit is equal to the commencing signal of interface circuit output
And the time interval stopped between signal rising edge.
Preferred embodiment, when port four input is for high level, the certainty of measurement value of examining slowdown monitoring circuit is relatively big,
When port four input is for low level, the certainty of measurement value of examining slowdown monitoring circuit is less.
Beneficial effects of the present invention: the invention mainly comprises rough detection circuit, interface circuit, examining survey
Circuit three part, the conversion of the common finishing time information of three to digital information.The technology of the present invention is closed
Key is through being designed to delay line ring-type and does delay cell realize unit multiplexed for ruling greatly
The measurement of scope；And utilize the grid oxygen electric capacity of field effect transistor to regulate differential ring oscillator (VRO)
The difference on the frequency making two agitator reaches the least, it is achieved high-acruracy survey；Final with the least area
Expense realizes the time interval measurement of high-precision large-range.In rough detection circuit, the present invention passes through will
Delay line is designed to ring-type, and trigger (ruling delay cell) multiplexing of zero build-up time is done
A kind of special delay cell, records the signal of port one input ring-type by means of enumerator simultaneously
Cycle-index in delay line, in this case, the dynamic range that can input is greatly expanded, owing to being
Ring-type, even if so time interval to be measured is relatively big, circuit area still can be the least；At interface circuit
In, by designing the circuit similar with rough detection circuit, but during work, interface circuit is relative to slightly
Testing circuit wants entirety to be delayed by a period of time, and the output of such rough detection circuit just can be used for controlling to connect
The output of mouth circuit enables signal, and the time margin that final rough detection circuit produces is sent out accurately
Come, prepare for the thinnest survey；In examining slowdown monitoring circuit, by regulating the size of field effect transistor,
Thus change the capacitance of field effect transistor grid oxygen electric capacity, the frequency of two agitators in final change VRO
Difference, controls and regulates the precision of thin survey by such a mode, and at the end of measurement, agitator stops
Only vibration is to reduce circuit power consumption.By means of above-described three modules, the time number in the present invention
Word transducer just can obtain the highest certainty of measurement and the biggest input model with the least area overhead
Enclose.
The present invention has certainty of measurement height and inputs on a large scale, and the technology spy that chip area is little
Point, specific as follows:
1. input range extension is easily.The input range of this transducer is mainly determined by rough detection circuit,
To extension input range, simplest way is just to increase the figure place of rough detection circuit Counter,
Enumerator increases by one, and input range just expansion is twice, and do so can't cause big area
Expense.
2. the precision of examining slowdown monitoring circuit is adjustable.Because the precision of thin slowdown monitoring circuit is by changing field effect transistor
Grid oxygen electric capacity regulates, as long as so changing the size of field effect transistor, it is possible to the thin essence surveyed of regulation
Degree, has the biggest motility.
The most whole change-over circuit power consumption is relatively low.During the work of rough detection circuit, examining slowdown monitoring circuit is in dormancy
State, during the work of examining slowdown monitoring circuit, rough detection circuit in a dormant state, and either rough detection
Circuit or examining slowdown monitoring circuit, as long as its convert task one end undertaken, quit work at once, because of
The power consumption of this whole circuit is relatively low.
4. circuit stability is good.Embody the most all of buffer and have temperature-compensation circuit, and
The difference on the frequency caused by field effect transistor grid oxygen electric capacity is stable, and the input of examining slowdown monitoring circuit has trigger
Being filtered the time margin signal of input, so the good stability of whole circuit, measurement result can
Lean on.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the present invention；
The input/output signal waveform of Fig. 1 a rough detection circuit；
The input-output wave shape of Fig. 1 b interface circuit；
The input-output wave shape of Fig. 1 c examining slowdown monitoring circuit；
Fig. 2, Fig. 2 a and Fig. 2 b is the rough detection circuit block diagram in the present invention；
Fig. 3 is the rough detection circuit diagram in the present invention；
Fig. 4 is the interface circuit figure in the present invention；
Fig. 5, Fig. 5 a and Fig. 5 b is the examining slowdown monitoring circuit block diagram in the present invention；
Fig. 6, Fig. 6 a and Fig. 6 b is the examining slowdown monitoring circuit figure in the present invention；
Fig. 7 a and Fig. 7 b is zero build-up time trigger (SDFF) circuit diagram in the present invention；
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with concrete real
Execute example, and referring to the drawings, the present invention is described in more detail.
As it is shown in figure 1, heretofore described time-to-digit converter, including rough detection circuit 101,
Interface circuit 102, examining slowdown monitoring circuit 103 and computing unit 104.
One rough detection circuit 101, has port one, port two and port three, wherein: port three connects
Receive the level signal of input, for different level signals is selected different measurement ranges；Port one
With port two for receiving two hopping edge signals with continuous time interval of input respectively, and utilize
Ring-type delay line in rough detection circuit 101 has the hopping edge signal of continuous print time interval to two
Between time interval carry out bigness scale amount, and to the hopping edge signal of port one input at ring-type delay line
In cycle-index count, obtain the end-state of all ruling delay cells of ring-type delay line
Value Q [M:0], obtain ring-type delay line middle port one and input the cycle-index count value of hopping edge signal
N1 and be taken at port two and input the time margin signal STOP_D of hopping edge signal；
One interface circuit 102, two input connects the outfan of rough detection circuit 101, receives
And the end-state value of described ruling delay cell to be generated the rising edge of commencing signal, and by more than the time
Amount signal generates the rising edge stopping signal, obtains commencing signal start and stops signal stop's
Time interval between rising edge is as the time margin of rough detection circuit；
One examining slowdown monitoring circuit 103, has two inputs and port four, and described port four is used for receiving
The control signal of input, controls the certainty of measurement of examining slowdown monitoring circuit 103 for regulation further；Described
Two inputs connect the outfan of interface circuit, receive and utilize the difference in examining slowdown monitoring circuit 103
The commencing signal start of ring oscillator interface circuit output and the rising edge of stopping signal stop
Between time interval carefully measure, and the cycle of oscillation of agitator in differential ring oscillator is entered
Row counting, generates and exports count value N2 cycle of oscillation of agitator in differential ring oscillator；
One computing unit 104, its input respectively with the outfan of the enumerator of rough detection circuit 101
Connect the outfan being connected with the enumerator of examining slowdown monitoring circuit 103 with ruling delay outfan to be connected,
The hopping edge signal received and described port one is inputted cycle-index counting in ring-type delay line
The vibration of agitator in value N2, described end-state value Q [M:0] and described differential ring oscillator
Cycle count value N1 generates and exports the digital quantity containing time interval information to be measured.
Ruling delay cell in rough detection circuit 101 is ruling unit or delay cell.Port three
When input is for high level, the measurement range of rough detection circuit 101 is relatively big, and port three input is low level
Time, the measurement range of rough detection circuit 101 is less.The time margin value of rough detection circuit 101 output
Equal to the time interval between commencing signal and the stopping signal rising edge of interface circuit 102 output.End
When mouth four input is for high level, the certainty of measurement value of examining slowdown monitoring circuit 103 is relatively big, and port four input is
During low level, the certainty of measurement value of examining slowdown monitoring circuit 103 is less.Rough detection circuit 101, interface electricity
Road 102, examining slowdown monitoring circuit 103 and computing unit 104 are manufactured and designed by cmos circuit and form.
The operation principle of rough detection circuit 101 is as follows:
First, edge signal START and STOP to be measured is input to by port one and port two respectively
In rough detection circuit 101, the time interval between START and STOP hopping edge is exactly the time of input
Amount.The measurement measurement range selection signal SEL inputted by port three is for selecting rough detection circuit 101
Measure range.Rough detection terminates, and rough detection circuit 101 exports rough detection result: value N1 of enumerator,
End-state value Q [M:0] of (M+1) individual ruling delay cell in ring-type delay line.Rough detection simultaneously
Circuit 101 is by the time margin signal STOP_D produced and the end-state of all ruling delay cell
Signal Q [M:0] is input in interface circuit 102, for producing the two of correct time residual signal
Individual rising edge signal, i.e. commencing signal start and stopping signal stop.Interface circuit 102 is by bigness scale
During produce time margin signal be delivered in examining slowdown monitoring circuit 103, simultaneously by port four defeated
Enter control signal c, for the precision of regulation examining slowdown monitoring circuit 103 in real time.Control signal c is high electricity
Flat, the accuracy value of examining slowdown monitoring circuit becomes big, and control signal c is low level, examining slowdown monitoring circuit 103
Accuracy value diminishes.Examining is surveyed and is terminated, and examining slowdown monitoring circuit 103 exports carefully surveys result: the counting of enumerator
Value N2.Rough detection result N1, Q [M:0] and thin testing result N2 calculate according to following computing formula
I.e. can obtain the time interval size of input.
When level signal SEL of port three input is high level, and the control signal of port four input
When C is low level, computing formula is as follows:
T=tRough detection result+tThin testing result
=N1 × (M+1) × R1+P × R1+N2 × R3
tRough detection result=N1 × (M+1) × R1+P × R1
tThin testing result=N2 × R3
When level signal SEL of port three input is low level, and the control signal of port four input
When C is low level, computing formula is as follows:
T=tRough detection result+tThin testing result
=N1 × (M+1) × R2+P × R2+N2 × R3
tRough detection result=N1 × (M+1) × R2+P × R2
tThin testing result=N2 × R3
When level signal SEL of port three input is high level, and the control signal of port four input
When C is high level, computing formula is as follows:
T=tRough detection result+tThin testing result
=N1 × (M+1) × R1+P × R1+N2 × R4
tRough detection result=N1 × (M+1) × R1+P × R1
tThin testing result=N2 × R4
When level signal SEL of port three input is low level, and the control signal of port four input
When C is high level, computing formula is as follows:
T=tRough detection result+tThin testing result
=N1 × (M+1) × R2+P × R2+N2 × R4
tRough detection result=N1 × (M+1) × R2+P × R2
tThin testing result=N2 × R4
In above formula, t represents the time quantum of input, its result being equal to rough detection circuit 101 and examining
The result sum of slowdown monitoring circuit.Wherein, N1 is the output valve of rough detection circuit 101 Counter, (M+1)
Being the number of ruling delay cell in ring-type delay line in rough detection circuit 101, R1 is rough detection circuit
101 port three input level signal SEL be certainty of measurement during high level, R2 be rough detection electricity
Road 101 is certainty of measurement during low level in level signal SEL that port three inputs；P is from Q [0]
When occurring 1 in the sequence of Q [M] experience ruling delay cell number (be equal to from Q [0] to
The number of the 0 of experience when occurring 1 in the sequence of Q [M]), such as when Q [M:0]=... when 0001000,
From Q [0] to Q [M], when occurring 1 in sequence, the number of the ruling delay cell of experience is 3 (to occur
When 1, the number of the 0 of experience is 3), so P=3 in this case.N2 is examining slowdown monitoring circuit 103
The output valve of Counter, R3 be for examining slowdown monitoring circuit 103 when the C that port four inputs is low level
Certainty of measurement, R4 is to be measurement during high level for examining slowdown monitoring circuit 103 at the C that port four inputs
Precision.R1, R2, R3, R4 manufacture the constant determined that afterwards in circuit design.It can be seen that
The time quantum t of input may finally be come by digital quantity N1, Q [M:0] (can be scaled P value), N2
Represent.The most in such a way, it is achieved that the time is to the conversion of numeral.
Fig. 1 a gives the input-output wave shape of rough detection circuit 101.START is inputted from port one
Signal is a rising edge signal, is a trailing edge signal from the STOP signal of port two input,
Time interval between START rising edge and STOP trailing edge is time interval to be measured.Whole
During rough detection, the SEL signal of port three input is high, represents now 101, rough detection circuit
The input range held is bigger.Ruling delay cell is output as Q [0]-Q [M], adjacent two ruling
Time interval between the output waveform correspondence rising edge of delay cell represents the survey of rough detection circuit 101
Accuracy of measurement.The most in fig 1 a, first rising edge of first rising edge of Q [0] and Q [1] it
Between time interval be equal to the certainty of measurement of rough detection circuit.Output in same ruling delay cell
In waveform, the time interval between adjacent two rising edges is equal to the START signal edge of port one input
Ring-type delay line and propagate the time delay that a circle is experienced.STOP_D signal carrys out the end after self-dalay
Mouth input signal STOP, STOP_D remains a trailing edge.Count value N1 of enumerator represents
The number of times that the START signal of port one input circulates in ring-type delay line, i.e. START signal edge
The number of turns that ring-type delay line is propagated.The meter of the end-state value sum counter of all ruling delay cells
Numerical value of N 1 is the measurement result of rough detection circuit 101.
Fig. 1 b gives the input-output wave shape of interface circuit 102.Sanction in rough detection circuit 101
Certainly the output of delay cell is input to interface circuit 102 for producing commencing signal start, start
It it is a pulse signal.The time margin signal STOP_D of rough detection circuit 101 output is input to connect
It is a rising edge signal that mouth circuit is used for producing stopping signal stop, stop.Start pulse upper
The time interval rising edge and stop rising time is exactly the time margin of rough detection circuit.Produce
Time margin is passed to examining slowdown monitoring circuit 103 for further measuring.
Fig. 1 c gives the input-output wave shape of examining slowdown monitoring circuit 103.Examining slowdown monitoring circuit 103 defeated
Enter commencing signal start and stopping signal stop for interface circuit 102 output.At start and
Before stop rising edge arrives, control signal C of port four input becomes low level, represents the thinnest
The certainty of measurement of testing circuit 103 is higher.The vibration of agitator in counter records examining slowdown monitoring circuit
Periodicity N2 is as the measurement result of examining slowdown monitoring circuit 103.
Rough detection circuit 101 block diagram showing in the present invention such as Fig. 2, Fig. 2 a and Fig. 2 b, Rough Inspection
Slowdown monitoring circuit 101 comprises multiple ruling delay cell 302,303 ... 3n, each ruling delay cell 302,
303 ... 3n has data input pin, input end of clock, clear input, selection input and one defeated
Going out end, described port two connects the data terminal of all ruling delay cell, first ruling delay cell
Clock end connect circulating controling circuit 301 outfan；Each ruling delay cell afterwards
Clock end all connects the outfan of its previous ruling delay cell；Last ruling delay cell
Outfan is connected to an input of circulating controling circuit 301 in the way of internal feedback signal；After
The outfan of one ruling delay cell is connected to the clear terminal of previous ruling delay cell；By institute
The level signal stating port three input is connected to the selection end of each ruling delay cell, is used for switching
Measure range；End to end by multiple ruling delay cells, constitute a ring-type delay line；Ring
Shape delay line, for the time interval of input is carried out bigness scale amount, produces and exports thick measurement result；
One circulating controling circuit 301, it has two inputs and an outfan, an input to connect
Having received described port one, another input is connected to the output of last ruling delay cell
End；The outfan of circulating controling circuit is connected to the clock end of first ruling delay cell；Circulation
The edge signal that the control signal of control circuit inputs from described port one；Circulating controling circuit is used for
Switching between edge signal and the ring-type delay line internal feedback signal of port one input；
Also comprising an enumerator 275, its input is connected to the output of first ruling delay cell
End, the hopping edge signal that also output port one inputs for generation circulation time in ring-type delay line
Number.
The detailed operation principle of rough detection circuit 101 is as follows:
Input signal inputs from port one, port two and port three respectively, the edge that port one will arrive first
Signal START is input in circulating controling circuit 301, and port two is by the rear edge signal STOP arrived
Being input to all ruling delay cell 302, the data terminal of 303 ... 3n, port three will measure scope
Signal SEL is selected to be input to the selection end of all ruling delay cell 302,303 ... 3n.Follow
The outfan of loop control circuit 301 is connected to the clock end of first ruling delay cell 302,
The outfan of later ruling delay cell 3n is input to circulating controling circuit as internal feedback signal
301.So, all of ruling delay cell 302,303 ... 3n and circulating controling circuit 301 structure
Become a ring-type delay line, the time interval inputted from port one and port two has been carried out bigness scale amount.
All ruling delay cells 302,303 ... 3n the output valve of output valve sum counter 275 common
Constitute the measurement result of rough detection circuit 101.When circuit is started working, circulating controling circuit 301
Outfan be port one input signal, after the signal of port one is transfused to, loop control electricity
The outfan on road 301 switches to internal feedback signal.Circulating controling circuit 301 ensure that last
The output of ruling delay cell 3n can by correct be transmitted back to first ruling delay cell 302 time
Zhong Duan so that ring-type delay line can normally work.Enumerator 275 have recorded last ruling to postpone
The Times of Feedback of unit 3n outfan, the namely cycle-index of internal feedback signal, n is natural number.
Rough detection circuit 101, as it is shown on figure 3, input signal to be measured is called START and STOP, divides
Not inputting from port one and port two, START is a rising edge signal, and STOP is a decline
Along signal.Measuring measurement range selection signal SEL to input from port three, SEL can be that high level can also
It is low level, might as well assume that SEL signal is high level here.START signal is through MUX
280 and buffer 281 after be separately input to d type flip flop 201 (in Fig. 2, Fig. 2 a and Fig. 2 b
D type flip flop is zero build-up time trigger, is called for short SDFF) clock end, STOP signal is through too much
The data terminal of d type flip flop 201 it is input to after road selector 282 and buffer 283.D type flip flop
201 to carry out for the first time ruling suitable with the priority determining now clock end and two signal edges of data terminal
Sequence, START signal is again through CLK-Q delay, the MUX 290 of d type flip flop 201 afterwards
With the delay of buffer 291, d type flip flop 202 carry out second time ruling, and d type flip flop 202
Buffer output Q [1] anti-phase after as the reset signal R of d type flip flop 201, say, that D triggers
The high level state of device 201 is cleared after maintaining a period of time, and do so is in subsequent cycle
Ruling prepare.The rest may be inferred, and after (M+1) secondary ruling, START signal is from d type flip flop
The output of 272 comes back to the input of MUX 280, the now choosing of MUX 280
Selecting signal i.e. switching signal has switched to feedback signal to input, and can repeat the most again above-mentioned
Ruling process, the value of the enumerator 275 being simultaneously connected with buffer 291 increases by 1, represents and once follows
Ring.MUX 280 select signal START signal after i.e. switching signal carrys out self-dalay,
This is also one of the characteristic of the present invention.When d type flip flop occurs the situation that ruling result is zero first,
Rough detection terminates.End value N1 of enumerator 275 and end-state Q [M:0] of (M+1) individual d type flip flop
Together form rough detection result.It can be seen that during measuring, when SEL signal is high level
Time, d type flip flop is that ruling unit is re-used again and does delay cell, measures range ratio bigger；Work as SEL
When signal is low level, d type flip flop is intended only as ruling unit, therefore measures range less.Except this
Outside, the application of zero build-up time d type flip flop ensure that the accuracy of ruling.At traditional delay line
In, the length of delay line is proportional to time interval to be measured, and time interval is the biggest, and delay line is the longest,
The area of circuit is the biggest, and in the present invention, delay line is designed to ring-type, when time interval is the biggest
The area of circuit is the least.In a word, rough detection circuit 101, with the least area overhead, obtains
Big input range, is the main characteristics of the present invention.
The minimum interval can differentiated less than rough detection circuit 103, the i.e. CLK-Q of d type flip flop
Delay, a MUX 280 and the delay sum of a buffer 291, between this part-time
Will be spread out of by interface circuit 102 every being called time margin.Interface circuit 102 as shown in Figure 4, is controlled
Circuit 705 processed is output as three state buffer 701, the enable signal of 702,703 and tristate inverter
The enable signal of 704, the input of three state buffer is the output of ruling delay cell in rough detection circuit
Q [M:0], three state buffer is output as commencing signal start；The input of tristate inverter is Rough Inspection
The time margin signal STOP_D of slowdown monitoring circuit output, tristate inverter is output as stopping signal stop.
So, the ruling delay cell of rough detection circuit exports Q [M:0] and time margin signal STOP_D
It is converted into the commencing signal start of interface circuit and stops signal stop.Final rough detection circuit 101
The time margin produced is sent out accurately, ready for the thinnest survey.
The block diagram of examining slowdown monitoring circuit 103 is as shown in Fig. 5, Fig. 5 a and Fig. 5 b.Mainly include 5 moulds
Block, is oscillation control circuit 601 respectively, the first agitator 407, the second agitator 408, and phase place is examined
Slowdown monitoring circuit 604 sum counter 415, its feature includes:
Oscillation control circuit 601, it has three inputs, two outfans, wherein first input ends
With the outfan that the second input is connected to interface circuit, two inputted for receiving interface circuit
Rise along signal, i.e. commencing signal start and stopping signal stop；3rd input is connected to phase place inspection
The outfan of slowdown monitoring circuit；The signal that first input end and the second input receive is edge signal or arteries and veins
Rushing signal, oscillation control circuit 601 is for producing the first agitator 407 and the second agitator 408
Multiple oscillation control signal；
First agitator 407, it has an input and an outfan, and its input is connected to shake
Swinging the first outfan of control circuit, its outfan is connected to the first input end of phase detecting circuit；
The frequency of oscillation of the first agitator by changing the grid oxygen electric capacity of the first agitator internal fet and
Realizing fine setting, the first agitator is used for producing the adjustable oscillator signal of frequency of oscillation；
Second agitator 408, it has an input and an outfan, and its input is connected to shake
Swinging the second outfan of control circuit, its outfan is connected to the second input of phase detecting circuit；
The frequency of oscillation of the second agitator by changing the grid oxygen electric capacity of the second agitator internal fet and
Realizing fine setting, the second agitator is used for producing the adjustable oscillator signal of frequency of oscillation；
Phase detecting circuit 604, it has two inputs and outfan, wherein a first input end
Being connected to the outfan of the first agitator 407, the second input is connected to the second agitator 408
Outfan, its outfan is connected to the 3rd input of oscillation control circuit, and phase detecting circuit is used for
Detect the phase relation between the first agitator and the produced signal of the second agitator, when phase place is consistent,
Phase detecting circuit outputs level signals, the first agitator and the second agitator all stop oscillation；
Enumerator 415, for the periodicity of record the second agitator.
The specific works principle of examining slowdown monitoring circuit 103 is as follows:
Oscillation control circuit 601 is for receiving more than the time that first input end and the second input input
Amount signal, signal can be edge signal can also be pulse signal.It is additionally operable to accept from the 3rd input
The signal that stops oscillation of end input, for stopping shaking of the first agitator 407 and the second agitator 408
Swing.First outfan of oscillation control circuit 601 has been input to the first agitator 407, is used for starting
Or the vibration of stopping the first agitator 407, the second outfan of oscillation control circuit 601 is input to
Second agitator 408, for starting or stoping the vibration of the second agitator 2.When the first agitator 407
During with the phase alignment of the second agitator 408, phase detecting circuit 604 output low level is to vibration control
Single channel 601 processed, the first agitator 407 and the second agitator 408 all stop oscillation afterwards, and examining is surveyed
Circuit enters low-power consumption mode.Enumerator 415 have recorded 408 period of oscillation numbers of the second agitator,
The numerical value of enumerator 415 represents the measurement result of examining slowdown monitoring circuit 103.
The output signal of interface circuit 102 surveys electricity as the input signal of examining slowdown monitoring circuit 103, examining
Road 103 is as shown in Fig. 6, Fig. 6 a and Fig. 6 b.The time margin signal of output is called respectively and starts letter
Number and stop signal, commencing signal one arrives, the first agitator 407 starting of oscillation, stop signal arrive after,
The just starting of oscillation of second agitator 408, and ensure that the frequency of oscillation of the first agitator 407 is slightly less than during design
Second agitator 408 frequency of oscillation, when small difference on the frequency is specifically achieved in that beginning, the
One agitator 407 is identical with the frequency of oscillation of the second agitator 408, and agitator 407 and 408
Constituted by buffer 418, by loading inequality respectively in two oscillation rings 410 and 412
Field effect transistor grid oxygen electric capacity, the grid oxygen electric capacity 422 wherein controlled by switch c is mainly used to adversarial
The difference on the frequency change caused due to technique shake during making, it is also possible to be used for regulation first further
Agitator 407 and the difference on the frequency of the second agitator 408, difference on the frequency is the survey of examining slowdown monitoring circuit 103
Accuracy of measurement.Constantly regulation grid oxygen electric capacity 420 and grid oxygen electric capacity 421 make the thinnest precision of surveying of difference on the frequency reach
Till desired value, wherein the regulation of grid oxygen electric capacity 420 and grid oxygen electric capacity 421 is by changing grid oxygen electricity
The size of the field effect transistor corresponding to appearance 420 and grid oxygen electric capacity 421 realizes, and this is also the present invention
One of key technology.After some cycles, when the first agitator 407 and the second agitator 408
During phase alignment, by d type flip flop 402,403 and the phase detecting circuit 604 of NAND gate 404 composition
Output low level, the d type flip flop 400 and 401 being connected with input signal is all cleared, the first vibration
Device 407 and the second agitator 408 stop oscillation.Due to the D used in phase detecting circuit 604
Trigger is the d type flip flop of zero build-up time, so the accuracy of phase-detection is the highest, thin to improving
The certainty of measurement of testing circuit 103 has great role.The enumerator 415 being connected with the second agitator 408
Produced periodicity N2 before have recorded the second agitator 408 failure of oscillation.Because the time interval when input
During less than cycle of oscillation of the first agitator 407, the first agitator 407 and the second agitator 408
Before stopping oscillation, the periodicity of experience is identical, carries out one of them agitator with an enumerator 415
Count.Here, the effect of two d type flip flops 400 and 401 being connected with input signal is main
Having three: one is to be filtered input signal commencing signal start and stopping signal stop, really
When guarantor's input signal has bigger shake, the first agitator 407 and the second agitator 408 still can be normal
Work；Two is when the phase alignment of the first agitator 407 and the second agitator 408, the most carefully surveys knot
During bundle, the first agitator 407 and the second agitator 408 can quit work to reduce circuit merit timely
Consumption；Three are because introducing d type flip flop 400 and 401, so the commencing signal of input and stopping letter
Number both can be edge signal can also be pulse signal.End value N2 of enumerator 415 represents
The measurement result of examining slowdown monitoring circuit 103.
The zero build-up time d type flip flop used in rough detection circuit 101 and examining slowdown monitoring circuit 103
(SDFF) circuit structure is as shown in figs. 7 a and 7b.This trigger has 5 ports, respectively:
Data input pin D, clear input R, input end of clock clk_s, and outfan Q and anti-phase defeated
Go out to hold QB.Data input pin D is used for inputting data；Clear input is used for inputting reset signal；Time
Clock input be used for input clock signal, and by clk_s signal create the clk_m in Fig. 7 a,
Clk_sb, clk_mb signal；The output waveform of outfan Q and reversed-phase output QB is anti-phase pass
System.The time of setting up of master-slave flip flop is to be caused by the transmission delay of main latch, therefore will be main
The clock clk_m of latch postpones the regular hour relative to from the clock clk_s of latch, and D touches
The time of setting up sending out device just can set to zero.In the present invention, a kind of time delay is devised adjustable
Delay circuit, specifically: clk_m has prolonging of phase inverter 501 and phase inverter 503 relative to clk_s
Late, and add field effect transistor grid oxygen electric capacity 505 in the middle of phase inverter 501 and 503, by regulation
The size of field effect transistor regulates the value of grid oxygen electric capacity 505, further regulation clk_m and clk_s it
Between delay, the total delay of the delay circuit made is exactly equal to trigger when not introducing delay circuit
Set up the time.And inversion clock clk_sb and clk_mb connects the output of phase inverter 501.Pass through
Above measure makes the time of setting up of trigger the most all be approximately zero, i.e. works as d type flip flop
Rising edge clock and data rising edge when simultaneously arriving, d type flip flop still can normally work output
High level.Main latch and the delay circuit between latch clock in zero build-up time d type flip flop
Design is also one of characteristic of the present invention.
The above, the only detailed description of the invention in the present invention, but protection scope of the present invention is not
It is confined to this, any is familiar with the people of this technology in the technical scope that disclosed herein, it will be appreciated that think
The conversion arrived or replacement, all should contain within the scope of the comprising of the present invention.
Claims (7)
1. a time-to-digit converter, it is characterised in that be provided with:
One rough detection circuit, has port one, port two and port three, wherein: port three receives defeated
The level signal entered, for selecting different measurement ranges to different level signals；Port one and end
Mouth two is for receiving two edge signals with continuous time interval of input respectively, and utilizes rough detection
Ring-type delay line in circuit is to the time between two edge signals with continuous print time interval
Interval carries out bigness scale amount, and the cycle-index that the edge signal inputting port one is in ring-type delay line
Count, obtain all ruling delay cells of ring-type delay line end-state value, obtain ring-type
Delay line middle port one inputs the cycle-index count value of edge signal and is taken at port two and inputs limit
Time margin signal along signal；
One interface circuit, two input connects rough detection circuit output end, receives and by described sanction
Certainly the end-state value of delay cell generates the rising edge of commencing signal, and by described time margin signal
Generate the rising edge stopping signal, obtain between the time between commencing signal and the rising edge stopping signal
Every the time margin as rough detection circuit；
One examining slowdown monitoring circuit, has two inputs and port four, and described port four is used for receiving input
Control signal, control the certainty of measurement of examining slowdown monitoring circuit for further regulation；Said two inputs
End connects the outfan of interface circuit, receives and utilizes the differential ring oscillator pair in examining slowdown monitoring circuit
Time interval between commencing signal and the rising edge stopping signal of interface circuit output is carefully surveyed
Amount, and the cycle of oscillation of agitator in differential ring oscillator is counted, generate and export difference
Count value cycle of oscillation of agitator in ring oscillator；
One computing unit, its input outfan with the enumerator of rough detection circuit respectively be connected and
Ruling postpones outfan connection and is connected with the outfan of the enumerator of examining slowdown monitoring circuit, receives and by institute
State the edge signal cycle-index count value in ring-type delay line of port one input, described final shape
In state value and described differential ring oscillator, count value cycle of oscillation of agitator generates and exports and contains
There is the digital quantity of time interval information to be measured.
2. time-to-digit converter as claimed in claim 1, it is characterised in that rough detection circuit
Including:
Multiple ruling delay cells, each ruling delay cell have data terminal, clock end, clear terminal,
Selecting end and an outfan, described port two connects the data terminal of all ruling delay cell, and first
The clock end of individual ruling delay cell connects the outfan of circulating controling circuit；Each ruling afterwards
The clock end of delay cell all connects the outfan of its previous ruling delay cell；Last ruling
The outfan of delay cell be connected to circulating controling circuit in the way of internal feedback signal one is defeated
Enter end；The outfan of later ruling delay cell is connected to the clear terminal of previous ruling delay cell；
It is connected to the selection end of each ruling delay cell by the level signal of described port three input, uses
In handover measurement range；End to end by multiple ruling delay cells, constitute a ring-type delay
Line；Ring-type delay line, for the time interval of input is carried out bigness scale amount, produces and exports bigness scale amount knot
Really；
One circulating controling circuit, it has two inputs and an outfan, and an input is connected to
Described port one, another input is connected to the outfan of last ruling delay cell；Follow
The outfan of loop control circuit is connected to the clock end of first ruling delay cell；Loop control electricity
The edge signal that the control signal on road inputs from described port one；Circulating controling circuit is used for port one
Switching between edge signal and the ring-type delay line internal feedback signal of input；
One enumerator, its input is connected to the outfan of first ruling delay cell, is used for producing
And the cycle-index that the edge signal of output port one input is in ring-type delay line.
3. time-to-digit converter as claimed in claim 1, it is characterised in that examining slowdown monitoring circuit
Including:
One oscillation control circuit, it has three inputs, two outfans, wherein first input end and
Second input is connected to the outfan of interface circuit, for two risings of receiving interface circuit input
Along signal；3rd input is connected to the outfan of phase detecting circuit；First input end and second defeated
The signal entering end reception is edge signal or pulse signal, and oscillation control circuit shakes for producing first
Swing the multiple oscillation control signal of device and the second agitator；
First agitator, it has an input and an outfan, and its input is connected to vibration control
First outfan of circuit processed, its outfan is connected to the first input end of phase detecting circuit；First
The frequency of oscillation of agitator realizes by changing the grid oxygen electric capacity of the first agitator internal fet
Fine setting, the first agitator is used for producing the adjustable oscillator signal of frequency of oscillation；
Second agitator, it has an input and an outfan, and its input is connected to vibration control
Second outfan of circuit processed, its outfan is connected to the second input of phase detecting circuit；Second
The frequency of oscillation of agitator realizes by changing the grid oxygen electric capacity of the second agitator internal fet
Fine setting, the second agitator is used for producing the adjustable oscillator signal of frequency of oscillation；
One phase detecting circuit, it has two inputs and an outfan, wherein first input end company
Receiving the outfan of the first agitator, the second input is connected to the outfan of the second agitator, its
Outfan is connected to the 3rd input of oscillation control circuit, and phase detecting circuit shakes for detection first
Swing the phase relation between device and the produced signal of the second agitator, when phase place is consistent, phase-detection electricity
Road outputs level signals, the first agitator and the second agitator all stop oscillation；
One enumerator, for the periodicity of record the second agitator.
4. time-to-digit converter as claimed in claim 1, it is characterised in that rough detection circuit
In ruling delay cell be ruling unit or delay cell.
5. time-to-digit converter as claimed in claim 1, it is characterised in that port three inputs
During for high level, the measurement range of rough detection circuit is relatively big, when port three input is for low level, and Rough Inspection
The measurement range of slowdown monitoring circuit is less.
6. time-to-digit converter as claimed in claim 1, it is characterised in that rough detection circuit
Time margin value equal to the commencing signal of interface circuit output and stop between signal rising edge time
Between be spaced.
7. time-to-digit converter as claimed in claim 1, it is characterised in that port four inputs
During for high level, the certainty of measurement value of examining slowdown monitoring circuit is relatively big, when port four input is for low level, carefully
The certainty of measurement value of testing circuit is less.
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| CN201210211299.6A CN103516367B (en) | 2012-06-20 | 2012-06-20 | A kind of time-to-digit converter |
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| CN104614976B (en) * | 2015-02-12 | 2017-03-29 | 中国科学技术大学 | A kind of time-digital converter based on FPGA |
| CN106059540B (en) * | 2016-05-27 | 2019-03-15 | 湖南融创微电子有限公司 | D type flip flop |
| US9746832B1 (en) * | 2016-09-09 | 2017-08-29 | Samsung Electronics Co., Ltd | System and method for time-to-digital converter fine-conversion using analog-to-digital converter (ADC) |
| CN107272395B (en) * | 2017-08-03 | 2018-06-19 | 睿力集成电路有限公司 | Time-to-digit converter and its conversion method |
| CN107659308B (en) * | 2017-11-10 | 2023-10-20 | 长鑫存储技术有限公司 | Digitally controlled oscillator and time-to-digital converter |
| CN111433686B (en) * | 2017-12-14 | 2021-09-14 | 华为国际有限公司 | Time-to-digital converter |
| US10520901B2 (en) * | 2018-02-23 | 2019-12-31 | Qualcomm Incorporated | Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation |
| SG10201802514RA (en) * | 2018-03-27 | 2019-10-30 | Delta Electronics Int’L Singapore Pte Ltd | Time-to-digital converter |
| CN112557762B (en) * | 2019-09-25 | 2022-09-02 | 天津大学 | High-precision terahertz near field imaging array unit |
| US11885915B2 (en) * | 2020-03-30 | 2024-01-30 | Stmicroelectronics (Research & Development) Limited | Time to digital converter |
| CN111812410A (en) * | 2020-08-11 | 2020-10-23 | 明峰医疗系统股份有限公司 | Wave-unity type TDC device of PET (polyethylene terephthalate) and measuring method |
| CN112578661A (en) * | 2020-12-11 | 2021-03-30 | 天津大学 | Delay line calibration circuit for FPGA type time-to-digital converter |
| CN114337620B (en) * | 2022-03-15 | 2022-06-21 | 成都迅翼卫通科技有限公司 | Method, device and equipment for measuring relative delay of multi-channel pulse signals |
| CN114935886B (en) * | 2022-04-21 | 2023-04-28 | 中国科学院上海微系统与信息技术研究所 | Two-stage superconducting time-to-digital converter and superconducting detector imaging system |
| CN117439609B (en) * | 2023-12-21 | 2024-03-08 | 杭州万高科技股份有限公司 | Time-to-digital conversion circuit based on pulse stretching and chopping PLL |
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