CN102073268A - High-precision pulse time interval measurement circuit - Google Patents

Abstract

The invention relates to a high-precision pulse time interval measurement circuit which is formed by integrated circuits. The circuit comprises a voltage-controlled delay line circuit, an integer clock interval measurement circuit, a pulse offset measurement circuit and a data combination module, wherein the integer clock interval measurement circuit consists of a sampling circuit and a logical comparison and clock count state machine and mainly measures an integer number of clock periods of a signal space to be measured; a series of pulse signals output by the voltage-controlled delay line circuit serves as the input of the pulse offset measurement circuit; the pulse offset measurement circuit mainly measures the time offset between a pulse edge to be measured and a clock edge; and finally a clock interval measurement result is serially output by the data combination module. The high-precision pulse time interval measurement circuit has the advantages that: the precision of pulse signals can be measured to be the same level (1ns) as a time delay parameter by utilizing a delay line (1ns) with a small time delay parameter at a low clock (such as 50 MHz and the period of 20ns), the time measurement precision under the low lock is improved greatly; moreover, circuit resources are saved.

Description

A kind of high-accuracy pulse is towards time interval measuring circuit

Technical field:

The invention belongs to the SIC (semiconductor integrated circuit) technical field, is that a kind of high-accuracy pulse that is made of integrated circuit is towards time interval measuring circuit.

Background technology:

Pulse interval is measured and is extensively existed in the sensor signal process field.Require the mistiming in nanosecond order in communication, medical electronics, the pulse interval measuring accuracy used in the system such as control and instantaneous measurement automatically, adopt the mode of clock sampling pulse to measure this traditional circuit.This is not to be difficult in the design process of circuit, but the width of working as pulse is less, and when the accuracy requirement in the time interval is very high, not only need to measure the integer clock periodicity in interpulse period, also need to measure the side-play amount at pulse to be measured and clock edge.

If the employing traditional scheme according to the sampling principle of digital circuit, needs at least 2 times of clock sources to measuring accuracy and just can finish high-precision pulse interval measurement.And what improve that clock frequency will bring is a series of problems such as power consumption rising, clock reference shake.For addressing the above problem, can adopt outside lower clock input, the mode of carrying out clock multiplier in inside solves, and needs bigger hardware spending but also introduced inner frequency multiplier circuit, has also increased the circuit design difficulty simultaneously.Publication number be CN2672698's " new time interval measurement instrument " produce circuit by pseudo-random code and correlation detecting circuit, microprocessor, digital frequency synthesizer constitute, surveying instrument is quite complicated, system constructing also is difficult to guarantee the consistance of measuring error.Publication number is that the patent " based on the short time interval measurement device of programmable logic device (PLD) " of CN2736821 adopts a kind of intervalometer based on programmable logic device (PLD) (CPLD), the measuring appliance that is connected to form by programmable logic device (CPLD) and single-chip microcomputer, complex structure, and need write relevant software; Publication number is the patent " capacitive detection system, the timely interval measurement module of method, method " of the CN101369205 capacitive detection system that adopts Analog Circuit Design, and the time interval measurement module deadline interval measurement of capacitance detecting, is difficult to realize the high-speed pulse time interval measurement.

Summary of the invention:

Purpose of the present invention is exactly to pay wages big for the hardware that solves existing pulse interval metering circuit existence, circuit structure somewhat complex design difficulty is big simultaneously, and need write relevant software, be difficult to realize to shortcomings such as high-speed pulse time interval measurements, provide a kind of and have high-accuracy pulse towards time interval measuring circuit, this circuit has not only been realized high precision but also simplified related hardware, has reduced the clock resources costs; Owing to the high reliability of integrated circuit, measuring system consistance etc. has guaranteed high reliability and the high precision measured simultaneously.

For the purpose that realizes that this is above-mentioned, the present invention adopts following technical scheme:

A kind of high-accuracy pulse comprises towards time interval measuring circuit:

The voltage-controlled delay line circuit, it is made of the series connection of one group of time-delay impact damper, the voltage-controlled delay line circuit receives the pulse signal to be measured of input, and exports the input of delay pulse signal as pulse offset measurement circuit, and the voltage-controlled delay line circuit is made of 10 to 100 grades of time-delay impact dampers series connection;

Integer clock interval metering circuit, it is made up of secondary sample circuit, logic comparison circuit and clock counter state machine, the secondary sample circuit receives the pulse signal to be measured of input, transfer to the clock counter state machine after logic comparison processing of circuit, the number of cycles data of its output are as the input of data combination module;

Pulse offset measurement circuit, it is made up of one group of sampling logical circuit, logic comparison circuit and time-delay progression decoding output logic circuit, every grade of time-delay output signal of voltage controlled delay line is as the input of every grade of sampling logical circuit of correspondence, after corresponding logic comparison processing of circuit, transfer to time-delay progression decoding output logic circuit, the main time offset of measuring between porch to be measured and the clock edge, the offset data of its output is as the input of data combination module;

The data combination module, it is made up of 2 d type flip flops and one 32 bit register, under the control of clock signal be buffered in 32 bit registers by d type flip flop the number of cycles data of integer clock interval metering circuit output and the offset data of pulse offset measurement circuit output, number of cycles data high 16 as 32 bit registers wherein, offset data is as low 16 of 32 bit registers, by string and modular converter, under the driving of shift register, at last the serial of clock interval measurement result is exported.

Advantage of the present invention:

The present invention has realized low-frequency clock measurement high precision time interval, can be (such as 50MHz under lower clock, cycle 20ns), the precision of utilizing the less delay line of delay parameter (1ns) to measure pulse signal reach can be consistent with delay parameter rank (1ns), improved the time measurement precision under low clock greatly, compare existing scheme, not only realized high precision but also simplified related hardware, reduced the clock resources costs and saved circuit resource; Owing to the high reliability of integrated circuit, measuring system consistance etc. has guaranteed high reliability and the high precision measured simultaneously.

Description of drawings:

Fig. 1 high-accuracy pulse is towards the time interval measuring circuit The general frame;

The voltage-controlled delay line schematic block circuit diagram of Fig. 2;

Fig. 3 integer clock interval metering circuit theory diagram;

Fig. 4 integer clock count state machine transfer principle figure;

Fig. 5 pulse offset measurement schematic block circuit diagram;

Fig. 6 data combination module frame chart.

Embodiment:

Comprise voltage-controlled delay line circuit, integer clock interval metering circuit, pulse offset measurement circuit and output data composite module with reference to figure 1 circuit agent structure of the present invention.

The voltage-controlled delay line circuit can adopt time-delay buffering logic gates just can realize signal lag briefly; Integer clock interval metering circuit adopts repeatedly sampling pulse of clock, and carries out the mode of logical process, thus obtain the recurrent interval the integer clock period; Pulse offset measurement circuit can move to and clock synchronization through multistage delay line by detecting pulse to be measured, and then the progression of time-delay and average every grade of delay time can be multiplied each other obtains the side-play amount of pulse to be measured.

Further scheme is, with reference to figure 2, what delay circuit adopted is time-delay buffering logic gate, and the voltage-controlled delay line circuit constitutes the open loop form by the series connection of time-delay buffering logic gate, produces different delay values by the difference of voltage-controlled voltage.Simultaneously, also design band gap reference, a voltage reference that is not subjected to technology, voltage and temperature effect is provided for the delay locked loop circuit, further improved the degree of accuracy of chronotron.

With reference to figure 3, integer clock interval metering circuit compares circuit by secondary sample circuit and logic and the clock counter state machine is formed.Sampling obtains the input pulse state of adjacent 2 clocks, and keeps by at the edge of clock sampling input pulse; Logic comparison circuit is then made logical process to sampled result, to determine whether to sample the edge of input pulse, begins counting if sample the edge of pulse to be measured then begin the starting state machine; The clock counter state machine then begins counting after the edge of determining input pulse arrives, arrive up to the edge of finding next pulse, at this moment stops to count and obtaining the integer clock count partial data in the time interval of adjacent 2 pulses.

More concrete, with reference to figure 4, the clock counter state machine is in idle condition always, and after monitoring found that the edge arrival of pulse to be measured is arranged, state machine jumped to starting state and begin enabling counting after clock edge arrival next time; After count status found to have the edge of new pulse to be measured to arrive, state machine jumped to and stops 1 state and write down current count value, and changed over to and stop 2 states and wait for that the arrival at next pulse edge enters enabling counting.

With reference to figure 5, will be by the multistage delay pulse signal of voltage-controlled delay line circuit output as the input of pulse offset measurement circuit, pulse offset measurement circuit is made up of sample circuit, logic comparison circuit and time-delay progression decoding output logic circuit.The pulse signal of the outputs at different levels of delay line is sampled at the edge of clock, obtains the delay pulse state of adjacent 2 clocks and gives follow-up logic comparison circuit; Logic comparison circuit is then done the logic comparison to the pulse delay signal of sampling, and if the state that aligns with the edge of clock with the edge that determines whether to have monitored pulse is alignment then send a signal to the count decoding output logic circuit of delaying time; The time-delay counter-decoder circuit is write down current time-delay progression by decoding logic, and in conjunction with the offset data of average every grade of delay parameter output pulse signal of delay line.

With reference to figure 6, number of cycles data and offset data are buffered in by d type flip flop that (the integer multiples issue is high 16 in one 32 bit register, side-play amount is low 16), by string and modular converter, under the driving of shift register, with clock interval measurement result serial output, finish whole measuring process at last.

Claims (2)

1. a high-accuracy pulse is characterized in that comprising towards time interval measuring circuit:

The voltage-controlled delay line circuit, it is made of the series connection of one group of time-delay impact damper, and the voltage-controlled delay line circuit receives the pulse signal to be measured of input, and the output delay pulse signal is as the input of pulse offset measurement circuit;

Integer clock interval metering circuit, it is made up of secondary sample circuit, logic comparison circuit and clock counter state machine, the secondary sample circuit receives the pulse signal to be measured of input, transfer to the clock counter state machine after logic comparison processing of circuit, the number of cycles data of its output are as the input of data combination module;

Pulse offset measurement circuit, it is made up of one group of sampling logical circuit, logic comparison circuit and time-delay progression decoding output logic circuit, every grade of time-delay output signal of voltage controlled delay line is as the input of every grade of sampling logical circuit of correspondence, transfer to time-delay progression decoding output logic circuit after corresponding logic comparison processing of circuit, the offset data of its output is as the input of data combination module;

The data combination module, it is made up of 2 d type flip flops and one 32 bit register, under the control of clock signal be buffered in 32 bit registers by d type flip flop the number of cycles data of integer clock interval metering circuit output and the offset data of pulse offset measurement circuit output, number of cycles data high 16 as 32 bit registers wherein, offset data is as low 16 of 32 bit registers, by string and modular converter, under the driving of shift register, at last the serial of clock interval measurement result is exported.

According to a kind of high-accuracy pulse of claim 1 towards time interval measuring circuit, it is characterized in that: voltage controlled delay line is made of 10 to 100 grades of time-delay impact dampers series connection.

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