CN104133367A - Circuit and method for extracting time interval parameters of clock signals to be measured - Google Patents
Circuit and method for extracting time interval parameters of clock signals to be measured Download PDFInfo
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- CN104133367A CN104133367A CN201410320982.2A CN201410320982A CN104133367A CN 104133367 A CN104133367 A CN 104133367A CN 201410320982 A CN201410320982 A CN 201410320982A CN 104133367 A CN104133367 A CN 104133367A
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Abstract
The invention discloses a circuit and method for extracting time interval parameters of clock signals to be measured. The circuit comprises a comparator, a clock distribution unit, a start/stop control unit, three path units identical in circuit structure and an FPGA unit. By means of the FPGA unit, edges of the three clock signals to be measured of the three path units are locked, and the edges of the three clock signals to be measured are combined two by two so that the three time interval parameters or adjacent periodical values can be extracted once. By means of the circuit and method, the time interval parameters of a high-speed clock to be measured can be extracted, flexible control of types and polarity of the parameters can be achieved, the three time interval parameters or the adjacent periodical values can be extracted through single measurement, and random sampling can be achieved.
Description
Technical field
The present invention relates to clock test field, specifically a kind of circuit and method of extracting clock signal time interval parameter to be measured.
Background technology
Time interval measurement technology has a wide range of applications in fields such as Aeronautics and Astronautics, precise guidance and nuclear physics, is the indispensable gordian techniquies of application such as navigation, space technology, communication, commercial production, electric power.Time interval measurement is playing the important and pivotal role aspect the progress of industry, national defence and science and technology to observation and control technology.
To carry out signal integrity analysis and isolate deterministic jitter (DJ), Random jitter (RJ), periodic jitter (PJ) and high frequency modulated analysis etc. clock signal, need the time interval parameter of measurement a lot, as positive/negative cycle, positive/negative pulsewidth, a positive/negative N cycle and adjacent periods value etc.
The circuit of existing extraction clock signal time interval parameter to be measured, conventionally just extract single time interval parameter as positive/negative cycle or positive/negative pulsewidth etc., and can not to parameter type and positive/negative polarity, control arbitrarily, general clock signal frequency to be measured is no more than GHz simultaneously.With by oscillograph circuit measuring, compared, the shake being caused by trigger circuit itself can be reduced to minimum.The benefit of bringing is to measure rapidly accurately.Also can carry out the measurement to cycle etc. of dither cycle, cycle simultaneously.The cycle of input signal, pulsewidth, a N cycle etc. complete test by time interval measuring circuit.
Therefore, how obtaining the more time interval parameter of high speed clock to be measured available parameter type and positive/negative polarity, is those skilled in the art's technical issues that need to address.
summary of the inventionthe object of this invention is to provide a kind of circuit and method of extracting clock signal time interval parameter to be measured, the problem existing to solve prior art.
In order to achieve the above object, the technical solution adopted in the present invention is:
A circuit that extracts clock signal time interval parameter to be measured, is characterized in that: include comparer, clock distribution unit, start/stop control module, the identical San of circuit structure road path unit, FPGA unit, wherein:
The output of described comparer is connected with the input of clock distribution unit, and clock signal difference to be measured inputs to comparer, the point of crossing of inputting in difference relatively after, send into clock distribution unit;
Described clock distribution unit consists of the impact damper integrated circuit (IC) chip of differential comparator and a minute four, the output of clock distribution unit is connected with the input of start/stop control module, three road path unit inputs respectively, the clock signal to be measured that comparer is sent into is divided into four tunnel outputs after the impact damper of a minute four, and the clock signal to be measured of four tunnel outputs is sent into respectively start/stop control module, three road path units;
Described start/stop control module consists of single d type flip flop, start/stop control module output is connected to three road path units, described FPGA unit has part output to be connected to the input of startup/control module, the clock signal to be measured of clock distribution unit output is sent into the input end of clock of start/stop control module d type flip flop, FPGA unit produces start/stop measuring-signal and sends into the data input pin of start/stop control module d type flip flop, start/stop control module is usingd clock signal to be measured as the synchronous start/stop measuring-signal generation of reference signal start/stop control signal, start/stop control signal is exported by the output difference of start/stop control module, wherein part start/stop control signal is sent into three road path units,
In described path unit, every road path unit is respectively by the first positive/negative selection chip, two divided-frequency chip, the second positive/negative selection chip, programmable frequency divider, latch connects and composes successively, and described clock distribution unit is exported the first positive/negative selection chip input in the path unit of difference Yu Mei road and connected, and there is the first positive/negative selection chip in the path unit of part output difference Yu Mei road described FPGA unit, the second positive/negative selection chip, programmable frequency divider connects, and described start/stop control module is partly exported two divided-frequency chip in the path unit of difference Yu Mei road, programmable frequency divider, latch connects, and the clock signal to be measured of clock distribution unit output is sent into the first positive/negative selection chip in the path unit of every road, and clock signal to be measured is successively through the positive and negative selection of the first positive/negative selection chip, two divided-frequency chip frequency division, the positive and negative selection of the second positive/negative selection chip, programmable frequency divider frequency division, after latches, by latch, export the locking edge edge of clock signal to be measured, the start/stop control signal of described start/stop control module output is sent into respectively two divided-frequency chip, programmable frequency divider, latch, as several enable signals of putting of the reset signal of two divided-frequency chip and latch and programmable frequency divider, produces positive/negative polarity and selects signal in described FPGA unit, frequency division is put several control signals, and positive/negative polarity selects signal to send into respectively the first positive/negative selection chip by FPGA unit, the second positive/negative selection chip, frequency division is put several control signals and is sent into programmable frequency divider by FPGA unit.
Described a kind of circuit that extracts clock signal time interval parameter to be measured, is characterized in that: during the single-ended input of described comparer clock signal to be measured, comparer is not inputted the input end grounding of clock signal to be measured, or connects a fixedly comparative level.
A kind of clock signal time interval extracting method to be measured, it is characterized in that: the positive/negative polarity by positive/negative selection chip in the path unit of Dui San road, FPGA unit is selected, and the frequency division of programmable frequency divider is put several control, three road path units lock respectively the edge of three corresponding clock signals to be measured, by the edge of three clock signals to be measured each other combination of two can once extract three time interval parameters or adjacent periods value.
Beneficial effect of the present invention:
The invention provides a kind of circuit and the method for extracting clock signal time interval parameter to be measured for the time interval measurement of signal integrity analysis instrument, can realize high speed Clock Extraction time interval parameter to be measured, and can control flexibly the type of parameter and positive/negative polarity, single side amount can be extracted three time interval parameters or adjacent periods value, and can realize grab sample.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of circuit of the present invention.
Fig. 2 is the structured flowchart of path unit of the present invention.
Fig. 3 is the waveform schematic diagram of extraction of the present invention clock signal time interval parameter to be measured.
Embodiment
As shown in Figure 1 and Figure 2, a kind of circuit that extracts clock signal time interval parameter to be measured, include comparer, clock distribution unit 101, start/stop control module 102, the identical San of circuit structure road path unit 103,104,105, FPGA unit 106, wherein:
Comparer output and clock distribution list, 101 inputs connect, clock signal difference to be measured inputs to comparer, the point of crossing of difference input relatively after, send into clock distribution unit 101;
Clock distribution unit 101 consists of the impact damper integrated circuit (IC) chip of differential comparator and a minute four, the output of clock distribution unit 101 is connected with 102 inputs of start/stop control module, three road path unit 103,104,105 inputs respectively, the clock signal to be measured that comparer is sent into is divided into four tunnel outputs after the impact damper of a minute four, and the clock signal to be measured of four tunnel outputs is sent into respectively start/stop control module 102, three road path units 103,104,105;
Start/stop control module 102 consists of single d type flip flop, start/stop control module 102 outputs are connected to three road path units 103, 104, 105, FPGA unit 106 has part output to be connected to the input of startup/control module, the clock signal to be measured of clock distribution unit 101 outputs is sent into the input end of clock of start/stop control module 102D trigger, FPGA unit 106 produces start/stop measuring-signal and sends into the data input pin of start/stop control module 102D trigger, start/stop control module 102 is usingd clock signal to be measured as the synchronous start/stop measuring-signal generation of reference signal start/stop control signal, start/stop control signal is exported by the output difference of start/stop control module 102, wherein part start/stop control signal is sent into three road path units 103, 104, 105,
Path unit 103, 104, in 105, every road path unit is respectively by the first positive/negative selection chip 201, two divided-frequency chip 202, the second positive/negative selection chip 203, programmable frequency divider 204, latch 205 connects and composes successively, and clock distribution unit 101 is exported 201 inputs of the first positive/negative selection core in the path units of difference Yu Mei road and connected, and there is the first positive/negative selection chip 201 in the path unit of part output difference Yu Mei road FPGA unit 106, the second positive/negative selection chip 203, programmable frequency divider 204 connects, two divided-frequency chip 202 in start/stop control module 102 part output difference Yu Mei road path units, programmable frequency divider 204, latch 205 connects, and the clock signal to be measured of clock distribution unit 101 outputs is sent into the first positive/negative selection chip 201 in the path unit of every road, and clock signal to be measured is successively through the positive and negative selection of the first positive/negative selection chip 201, two divided-frequency chip 202 frequency divisions, the positive and negative selection of the second positive/negative selection chip 203, programmable frequency divider 204 frequency divisions, after latch 205 latchs, by the locking edge edge of latch 205 output clock signal to be measured, the start/stop control signal of start/stop control module 102 outputs is sent into respectively two divided-frequency chip 202, programmable frequency divider 204, latch 205, as several enable signals of putting of the reset signal of two divided-frequency chip 202 and latch 205 and programmable frequency divider 204, produces positive/negative polarity and selects signal in FPGA unit 106, frequency division is put several control signals, and positive/negative polarity selects signal to send into respectively the first positive/negative selection chip 201 by FPGA unit 106, the second positive/negative selection chip 203, frequency division is put several control signals and is sent into programmable frequency divider 204 by FPGA unit 106.
During the single-ended input of comparer clock signal to be measured, comparer is not inputted the input end grounding of clock signal to be measured, or connects a fixedly comparative level.
A kind of clock signal time interval extracting method to be measured, positive/negative polarity by positive/negative selection chip in the path unit of Dui San road, FPGA unit is selected, and the frequency division of programmable frequency divider is put several control, three road path units lock respectively the edge of three corresponding clock signals to be measured, by the edge of three clock signals to be measured each other combination of two can once extract three time interval parameters or adjacent periods value.
The present invention includes clock distribution unit, clock distribution unit is output as four tunnels by clock signal to be measured; The output terminal of clock distribution unit accesses respectively start/stop control module, identical three road path units, by FPGA unit, inputed to the start/stop measuring-signal of start/stop control module through d type flip flop and clock signal synchronization to be measured, produce start/stop control signal difference and export three road path units to; Three road path units carry out frequency division, the selection of positive/negative polarity, the edge of the clock signal to be measured that will extract by latches residence to clock signal to be measured.Wherein in three road path units programmable frequency divider frequency division put that several control signals, positive/negative polarity are selected and start/stop control module in start/stop measuring-signal by FPGA unit, produce.
In the present invention, clock signal difference to be measured inputs to high-speed comparator, in the point of crossing comparison of difference input, reduces the shake that sync comparator is introduced; In single-ended signal when input,, require the another terminal ground connection of difference, or connect a fixing comparative level; The clock distribution unit forming through one minute four impact damper integrated circuit (IC) chip of high speed low jitter is again output as four tunnels by clock signal to be measured.
In the present invention, start/stop control module is usingd clock signal to be measured as time-base signal, and start/stop measuring-signal is synchronizeed with it through d type flip flop, reduces and because start/stop measuring-signal is asynchronous with clock signal to be measured, causes measurement inaccurate.In addition, in three road path units fixedly two divided-frequency chip and the reset signal of latch, several enable signals of putting of programmable frequency divider by start/stop measuring-signal, provide, to reach before each startup is measured, automatically reset and put several objects, having improved testing efficiency.
In the present invention, the three identical path units in road, by drawing together two positive/negative selection chips, two divided-frequency chip, programmable frequency divider (2048>N >=2) and latch, form respectively, said integrated circuit chip all selects ON semi company frequency to be greater than the 100EP series ECL device design of 3GHz, and clock frequency to be measured can reach 2.5GHz; In PCB design, three path unit layout is consistent, cabling is strictly isometric, and differential signal line carries out 100 Ω impedance Control, as much as possible placement-and-routing is reduced to minimum to the impact of circuit performance.
In the present invention, FPGA unit produces positive/negative polarity in start/stop measuring-signal, three road path units and selects the frequency division of signal, programmable frequency divider to put several control signals, can adopt a slice FPGA design with rear end time interval measuring circuit, saved resources of chip, reduce the burden of CPU, improved the dirigibility of design.
In the present invention, by positive/negative polarity selection and frequency programmable dividing in the path unit of Dui San road, FPGA unit, put several control, three path units lock respectively the edge of three corresponding clock signals to be measured, combination of two can once extract three time interval parameters (as positive/negative cycle, positive/negative pulsewidth, a positive/negative N cycle etc.) or adjacent periods value each other, before measure starting, by circuit, automatically resetted and frequency division is put number, improve testing efficiency, by changing the opportunity of start/stop measurement, can realize grab sample.
Specific embodiment:
Of the present inventionly provide a kind of circuit that extracts clock signal time interval parameter to be measured, this main circuit will comprise clock distribution unit 101, start/stop control module 102, path unit 103, path unit 104, path unit 105 and FPGA unit 106.Clock distribution unit 101, clock signal difference to be measured inputs to high-speed comparator, in the point of crossing comparison of difference input, reduces the shake that sync comparator is introduced; In single-ended signal when input,, require the another terminal ground connection of difference, or connect a fixing comparative level; One minute four impact damper integrated circuit (IC) chip through high speed low jitter are output as four tunnels by clock signal to be measured again; The output terminal of clock distribution unit accesses respectively start/stop control module 102, path unit 103, path unit 104 and path unit 105; Start/stop control module 102, usings measured signal as time-base signal, and start/stop measuring-signal is synchronizeed with it through d type flip flop, reduces and because start/stop measuring-signal is asynchronous with clock signal to be measured, causes measurement inaccurate; In addition, in three road path units, the reset signal of two divided-frequency chip and latch, programmable frequency divider puts several enable signals by providing with start/stop control signal, to reach before each startup is measured, automatically reset and put several objects, having improved testing efficiency; Identical three road path units, comprise that respectively positive/negative polarity selects 201 and 203, fixedly two divided-frequency 202, frequency programmable dividing (2048>N >=2) 204 and latch 205 integrated circuit (IC) chip, said integrated circuit chip all selects ON semi company frequency to be greater than the 100EP series ECL device design of 3GHz, and clock frequency to be measured can reach 2.5GHz; In PCB design, three track layout is consistent, cabling is strictly isometric, and differential signal line carries out 100 Ω impedance Control, as much as possible placement-and-routing is reduced to minimum to the impact of circuit performance; Described FPGA unit 106 produces positive/negative polarity in start/stop measuring-signal, path Unit 1,2,3 and selects the frequency division of signal, programmable frequency divider to put the control signals such as number, can adopt a slice FPGA design with rear end time interval measuring circuit, saved resources of chip, reduce the burden of CPU, improved the dirigibility of design.
As shown in Figure 3, the invention provides a kind of method of extracting clock signal time interval parameter to be measured, the method is to put several control by positive/negative polarity selection and frequency programmable dividing in the path unit of Dui San road, three paths lock respectively the edge of three corresponding clock signals to be measured, combination of two can once extract three time interval parameters (as positive/negative cycle, positive/negative pulsewidth and a positive/negative N cycle etc.) or adjacent periods value each other, before measure starting, by circuit, automatically resetted and frequency division is put number, improve testing efficiency, and can realize grab sample.Concrete steps are (take path unit 103 as example):
(1), clock signal to be measured is output as four tunnels through clock distribution unit, wherein in an a access channel unit, road 103, positive/negative selection chip 201 carries out positive and negative selection, its output waveform is illustrated in figure 3 a+ or a-;
(2), positive/negative selection chip 201 output terminals access the fixedly input end of two divided-frequency chip 202, output after its two divided-frequency accesses positive/negative selection chip 203 and carries out positive and negative selection, at this moment its output waveform has four kinds of combinations, is illustrated in figure 3 ((a+ ÷ 2)+), ((a+ ÷ 2)-), ((a-÷ 2)+) or ((a-÷ 2)-);
(3), positive/negative selection chip 203 output access programmable frequency dividers 204, its divider ratio can be set to 2048>N >=2, here suppose that divider ratio is 2, its output waveform is illustrated in figure 3 ((a+ ÷ 2)+÷ 2), ((a+ ÷ 2)-÷ 2), ((a-÷ 2)+÷ 2) or ((a-÷ 2)-÷ 2);
(4), the input end of programmable frequency divider 204 output access latchs 205, the signal after latching along as in Fig. 3 1., 2., 3. or 4..
(5) time interval 1. and is 2. the positive period of measured signal as shown in the figure; In like manner the time interval 1. and is 3. the negative pulsewidth of measured signal; 1. the time interval and is 4. the positive pulsewidth of measured signal; 2. the time interval and is 3. the negative cycle of measured signal.Only need the frequency division that changes Fractional-N frequency in Fig. 2 to put the measurement (2048>N >=2) that number just can be realized the N cycle, by the programming of FPGA, be easy to realize the test of various parameters.
Claims (3)
1. extract a circuit for clock signal time interval parameter to be measured, it is characterized in that: include comparer, clock distribution unit, start/stop control module, the identical San of circuit structure road path unit, FPGA unit, wherein:
The output of described comparer is connected with the input of clock distribution unit, and clock signal difference to be measured inputs to comparer, the point of crossing of inputting in difference relatively after, send into clock distribution unit;
Described clock distribution unit consists of the impact damper integrated circuit (IC) chip of differential comparator and a minute four, the output of clock distribution unit is connected with the input of start/stop control module, three road path unit inputs respectively, the clock signal to be measured that comparer is sent into is divided into four tunnel outputs after the impact damper of a minute four, and the clock signal to be measured of four tunnel outputs is sent into respectively start/stop control module, three road path units;
Described start/stop control module consists of single d type flip flop, start/stop control module output is connected to three road path units, described FPGA unit has part output to be connected to the input of startup/control module, the clock signal to be measured of clock distribution unit output is sent into the input end of clock of start/stop control module d type flip flop, FPGA unit produces start/stop measuring-signal and sends into the data input pin of start/stop control module d type flip flop, start/stop control module is usingd clock signal to be measured as the synchronous start/stop measuring-signal generation of reference signal start/stop control signal, start/stop control signal is exported by the output difference of start/stop control module, wherein part start/stop control signal is sent into three road path units,
In described path unit, every road path unit is respectively by the first positive/negative selection chip, two divided-frequency chip, the second positive/negative selection chip, programmable frequency divider, latch connects and composes successively, and described clock distribution unit is exported the first positive/negative selection chip input in the path unit of difference Yu Mei road and connected, and there is the first positive/negative selection chip in the path unit of part output difference Yu Mei road described FPGA unit, the second positive/negative selection chip, programmable frequency divider connects, and described start/stop control module is partly exported two divided-frequency chip in the path unit of difference Yu Mei road, programmable frequency divider, latch connects, and the clock signal to be measured of clock distribution unit output is sent into the first positive/negative selection chip in the path unit of every road, and clock signal to be measured is successively through the positive and negative selection of the first positive/negative selection chip, two divided-frequency chip frequency division, the positive and negative selection of the second positive/negative selection chip, programmable frequency divider frequency division, after latches, by latch, export the locking edge edge of clock signal to be measured, the start/stop control signal of described start/stop control module output is sent into respectively two divided-frequency chip, programmable frequency divider, latch, as several enable signals of putting of the reset signal of two divided-frequency chip and latch and programmable frequency divider, produces positive/negative polarity and selects signal in described FPGA unit, frequency division is put several control signals, and positive/negative polarity selects signal to send into respectively the first positive/negative selection chip by FPGA unit, the second positive/negative selection chip, frequency division is put several control signals and is sent into programmable frequency divider by FPGA unit.
2. a kind of circuit that extracts clock signal time interval parameter to be measured according to claim 1, it is characterized in that: during the single-ended input of described comparer clock signal to be measured, comparer is not inputted the input end grounding of clock signal to be measured, or connects a fixedly comparative level.
3. the clock signal to be measured time interval extracting method based on circuit described in claim 1, it is characterized in that: the positive/negative polarity by positive/negative selection chip in the path unit of Dui San road, FPGA unit is selected, and the frequency division of programmable frequency divider is put several control, three road path units lock respectively the edge of three corresponding clock signals to be measured, by the edge of three clock signals to be measured each other combination of two can once extract three time interval parameters or adjacent periods value.
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| CN104133367B (en) | 2017-02-01 |
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