CN104133367B - Circuit and method for extracting time interval parameters of clock signals to be measured - Google Patents
Circuit and method for extracting time interval parameters of clock signals to be measured Download PDFInfo
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- CN104133367B CN104133367B CN201410320982.2A CN201410320982A CN104133367B CN 104133367 B CN104133367 B CN 104133367B CN 201410320982 A CN201410320982 A CN 201410320982A CN 104133367 B CN104133367 B CN 104133367B
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Abstract
The invention discloses a circuit and method for extracting time interval parameters of clock signals to be measured. The circuit comprises a comparator, a clock distribution unit, a start/stop control unit, three path units identical in circuit structure and an FPGA unit. By means of the FPGA unit, edges of the three clock signals to be measured of the three path units are locked, and the edges of the three clock signals to be measured are combined two by two so that the three time interval parameters or adjacent periodical values can be extracted once. By means of the circuit and method, the time interval parameters of a high-speed clock to be measured can be extracted, flexible control of types and polarity of the parameters can be achieved, the three time interval parameters or the adjacent periodical values can be extracted through single measurement, and random sampling can be achieved.
Description
Technical field
The present invention relates to clock test field, specifically a kind of electricity extracting clock signal time interval parameter to be measured
Road and method.
Background technology
Time interval measurement technology has a wide range of applications in fields such as Aeronautics and Astronautics, precise guidance and nuclear physics, is
The indispensable key technology of the applications such as navigation, space technology, communication, commercial production, electric power.Time interval measurement is to survey
Control technology plays the important and pivotal role at the progressive aspect of industry, national defence and science and technology.
Clock signal is carried out signal integrity analysis and isolate deterministic jitter (dj), Random jitter (rj),
Periodic jitter (pj) and high frequency modulated analysis etc., need the time interval parameter of measurement a lot, such as positive/negative cycle, positive/negative arteries and veins
Wide, positive/negative n cycle and adjacent periods value etc..
The existing circuit extracting clock signal time interval parameter to be measured, is generally only to extract single time interval ginseng
Number is as positive/negative cycles or positive/negative pulsewidth etc., and can not arbitrarily parameter type and positive/negative polarity be controlled, and simultaneously one
As clock signal frequency to be measured be less than ghz.Compared with by oscillograph circuit measuring, the shake being caused in itself by triggers circuit can
To be reduced to minimum.Have the advantage that, measurement is accurate rapidly.Dither cycle, cycle can also be carried out to the cycle etc. simultaneously
Measurement.The cycle of input signal, pulsewidth, n cycle etc. are completed to test by time interval measuring circuit.
Therefore, the more time interval parameter of high speed clock to be measured available parameter type and positive/negative how are obtained
Property, it is those skilled in the art's technical issues that need to address.
Content of the invention
It is an object of the invention to provide a kind of circuit extracting clock signal time interval parameter to be measured and method, to solve
The problem that prior art exists.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of extract clock signal time interval parameter to be measured circuit it is characterised in that: include clock distribution unit,
Startup/stop control unit, circuit structure identical three road path unit, fpga unit, wherein:
Described clock distribution unit is made up of the buffer integrated circuit chip of differential comparator and a point four, clock distribution
The output of unit is connected with the input of startup/stop control unit, three road path unit inputs respectively, and what differential comparator was sent into treats
Survey clock signal and be divided into four tunnel outputs after one point four of buffer, the clock signal to be measured of four tunnel outputs is respectively fed to open
Dynamic/stop control unit, three road path units；
Described startup/stop control unit is made up of single d trigger, and startup/stop control unit output par, c connects
To three road path units, described fpga unit has part output to connect to the input of startup/control unit, and clock distribution unit exports
Clock signal to be measured send into the input end of clock of startups/stop control unit d trigger, fpga unit produces and starts/stopping
Measurement signal simultaneously sends into the data input pin of startup/stop control unit d trigger, startup/stop control unit with to be measured when
Clock signal produces as reference signal synchronous averaging/stopping measurement signal and starts/stop control signal, startup/stop controlling letter
Number by the output of the output difference of startups/stop control unit, wherein part starts/stops control signal feeding three road path lists
Unit；
In described path unit, every road path unit respectively by first positive/negative select chip, two divided-frequency chip, second just/
Negative selection chip, programmable frequency divider, latch are sequentially connected composition, the output of described clock distribution unit respectively with every road path
In unit first positive/negative select chip input to connect, described fpga unit have part output respectively with every road path unit in the
One positive/negative selection chip, the second positive/negative selection chip, programmable frequency divider connect, described startup/stop control unit part
Output is connected with two divided-frequency chip, programmable frequency divider, latch in the path unit of every road respectively, clock distribution unit output
Clock signal to be measured sends into the first positive/negative selection chip in the path unit of every road, and it is positive/negative that clock signal to be measured sequentially passes through first
Select the positive negative selection of chip, two divided-frequency chip frequency dividing, the second positive/negative selection positive negative selection of chip, programmable frequency divider frequency dividing, lock
The locking edge edge of clock signal to be measured is exported by latch, what described startup/stop control unit exported opens after storage latch
Dynamic/stopping control signal being respectively fed to two divided-frequency chip, programmable frequency divider, latch, as two divided-frequency chip and latch
Reset signal and programmable frequency divider put number enable signals, produce in described fpga unit positive/negative polarity selection signal,
Frequency dividing puts several control signals, positive/negative polarity selection signal by fpga unit be respectively fed to first positive/negative select chip, second just/
Negative selection chip, frequency dividing is put several control signals and is sent into programmable frequency divider by fpga unit.
A kind of circuit of described extraction clock signal to be measured time interval parameter it is characterised in that: described differential comparison
During device single ended input clock signal to be measured, differential comparator does not input the input end grounding of clock signal to be measured, or connects one
Fixing comparative level.
A kind of clock signal time interval extracting method to be measured it is characterised in that: by fpga unit to three road path lists
The positive/negative positive/negative Sexual behavior mode selecting chip in unit, and the frequency dividing of programmable frequency divider puts several controls, three road path lists
The edge of unit's three corresponding clock signals to be measured of locking respectively, by the edge of three clock signals to be measured combination of two each other
Three time interval parameters or adjacent periods value can once be extracted.
Beneficial effects of the present invention:
The present invention is provided to when clock signal to be measured is extracted in one of signal integrity analysis instrument time interval measurement
Between the circuit of spacing parameter and method, can achieve to high speed Clock Extraction to be measured time interval parameter, and can be to the type of parameter
And positive/negative polarity is flexibly controlled, extractable three time interval parameters of single side amount or adjacent periods value, and can achieve
Randomization.
Brief description
Fig. 1 is the structured flowchart of circuit of the present invention.
Fig. 2 is the structured flowchart of the path unit of the present invention.
Fig. 3 is the waveform diagram of the extraction clock signal time interval parameter to be measured of the present invention.
Specific embodiment
As shown in Figure 1 and Figure 2, a kind of circuit extracting clock signal time interval parameter to be measured, includes clock distribution list
Unit 101, startup/stop control unit 102, circuit structure identical three road path unit 103,104,105, fpga unit 106,
Wherein:
Clock distribution unit 101 is made up of the buffer integrated circuit chip of differential comparator and a point four, clock distribution
The output of unit 101 is inputted with startup/stop control unit 102 respectively, three road path unit 103,104,105 input is connected,
Differential comparator send into clock signal to be measured be divided into after one point four of buffer four tunnels output, four tunnels output to be measured when
Clock signal is respectively fed to startup/stop control unit 102, three road path units 103,104,105；
Startup/stop control unit 102 is made up of single d trigger, and startup/stop control unit 102 output par, c is even
Be connected to three road path units 103,104,105, fpga unit 106 have part output to connect to input to startups/control unit, clock
The clock signal to be measured of allocation unit 101 output sends into the input end of clock of startup/stop control unit 102d trigger, fpga
Unit 106 produces the data input pin starting/stopping measurement signal and send into startup/stop control unit 102d trigger, opens
Dynamic/stop control unit 102 is produced as reference signal synchronous averaging/stopping measurement signal using clock signal to be measured and starts/stop
Only control signal, starts/stops the output difference output by startup/stop control unit 102 for the control signal, wherein partly open
Dynamic/to stop control signal feeding three road path units 103,104,105；
In path unit 103,104,105, every road path unit is respectively by the first positive/negative selection chip 201, two divided-frequency core
Piece 202, second is positive/negative to select chip 203, programmable frequency divider 204, latch 205 to be sequentially connected composition, clock distribution unit
Selection core 201 piece inputs positive/negative with the path unit of every road first are connected respectively for 101 outputs, and fpga unit 106 has part to export
First positive/negative select chip 201, second positive/negative select chip 203, programmable frequency divider 204 with the path unit of every road respectively
Connect, startups/stop control unit 102 part export respectively with two divided-frequency chip 202, frequency programmable dividing in the path unit of every road
Device 204, latch 205 connect, and the clock signal to be measured of clock distribution unit 101 output is sent into first in the path unit of every road
Positive/negative selection chip 201, clock signal to be measured sequentially passes through the first positive/negative selection positive negative selection of chip 201, two divided-frequency chip
202 frequency dividings, second positive/negative select the positive negative selection of chip 203, programmable frequency divider 204 to divide, latch 205 passes through after latching
Latch 205 exports the locking edge edge of clock signal to be measured, and the startup/stopping of startup/stop control unit 102 output controls letter
Number it is respectively fed to two divided-frequency chip 202, programmable frequency divider 204, latch 205, as two divided-frequency chip 202 and latch
The number of putting of 205 reset signal and programmable frequency divider 204 enables signal, produces positive/negative Sexual behavior mode in fpga unit 106
Signal, frequency dividing put several control signals, and positive/negative polarity selection signal is respectively fed to the first positive/negative selection chip by fpga unit 106
201st, the second positive/negative selection chip 203, frequency dividing is put several control signals and is sent into programmable frequency divider 204 by fpga unit 106.
During differential comparator single ended input clock signal to be measured, differential comparator does not input the input of clock signal to be measured
Ground connection, or connect a fixing comparative level.
A kind of clock signal time interval extracting method to be measured, by fpga unit to positive/negative choosing in three road path units
Select the positive/negative Sexual behavior mode of chip, and the frequency dividing of programmable frequency divider puts several controls, three road path units lock three respectively
The edge of individual clock signal accordingly to be measured, by the edge of three clock signals to be measured, combination of two can once extract each other
Three time interval parameters or adjacent periods value.
The present invention includes clock distribution unit, and clock signal to be measured is output as four tunnels by clock distribution unit；Clock distribution
The outfan of unit is respectively connected to startup/stop control unit, identical three road path units, by fpga unit input to
The startup of startup/stop control unit/stopping measurement signal, through d trigger and clock signal synchronization to be measured, produces and starts/stop
Only control signal difference output is to three road path units；Three road path units carry out to clock signal to be measured dividing, positive/negative polarity
Select, live the edge of to be fetched clock signal to be measured by latches.Programmable point in wherein three road path units
Frequency device frequency dividing put in several control signals, positive/negative Sexual behavior mode and startup/stop control unit start/stop measurement signal by
Fpga unit produces.
In the present invention, clock signal difference to be measured inputs to differential envelope detector, compares in the cross point of Differential Input,
Reduce the shake that synchronous difference comparator introduces；During single-ended signal input, then require the another terminal of difference to be grounded, or connect one
Fixing comparative level；The clock distribution unit that one point of four buffer integrated circuit chip through high speed low jitter is constituted again will be to be measured
Clock signal is output as four tunnels.
In the present invention, startup/stop control unit, using clock signal to be measured as time-base signal, will start/stop measurement
Signal is synchronous through d trigger, reduces and causes measurement not because startup/stopping measurement signal is asynchronous with clock signal to be measured
Accurately.Additionally, fixing the reset signal of two divided-frequency chip and latch in three road path units, the number of putting of programmable frequency divider makes
Signal can be provided by starting/stopping measurement signal, automatically reset before measurement and put several purposes to reach each startup, improve
Testing efficiency.
In the present invention, the identical path unit in three roads, respectively by include two positive/negative select chips, two divided-frequency chip,
Programmable frequency divider (2048 > n >=2) and latch are constituted, and said integrated circuit chip is all more than from semi company frequency
The 100ep series ecl device design of 3ghz, clock frequency to be measured is up to 2.5ghz；In pcb design, three path unit cloth
Office is consistent, cabling is strictly isometric, and differential signal line carries out 100 ω impedance control, as much as possible by placement-and-routing to circuit performance
Impact be reduced to minimum.
In the present invention, positive/negative Sexual behavior mode letter in fpga unit generation startup/stopping measurement signal, three road path units
Number, the frequency dividing of programmable frequency divider put several control signals, a piece of fpga design, section can be adopted with rear end time interval measuring circuit
About resources of chip, decreases the burden of cpu, improves the motility of design.
In the present invention, by fpga unit, positive/negative Sexual behavior mode in three road path units and frequency programmable dividing are put several
Control, three path units lock the edge of three corresponding clock signals to be measured respectively, combination of two can once carry each other
Take out three time interval parameters (as positive/negative cycle, positive/negative pulsewidth, positive/negative n cycle etc.) or adjacent periods value, measurement is opened
Automatically resetted and divided by circuit before dynamic and put number, improve testing efficiency, can by changing the opportunity starting/stop measurement
Realize randomization.
Specific embodiment:
The present invention provides a kind of circuit extracting clock signal time interval parameter to be measured, when this circuit mainly includes
Clock allocation unit 101, startup/stop control unit 102, path unit 103, path unit 104, path unit 105 and fpga
Unit 106.Clock distribution unit 101, clock signal difference to be measured inputs to differential comparator, in the cross point of Differential Input ratio
Relatively, reduce the shake that synchronous difference comparator introduces；During single-ended signal input, then the another terminal of difference is required to be grounded, or
Connect a fixing comparative level；Clock signal to be measured is output as by one point of four buffer integrated circuit chip through high speed low jitter again
Four tunnels；The outfan of clock distribution unit is respectively connected to startup/stop control unit 102, path unit 103, path unit 104
And path unit 105；Startup/stop control unit 102, using measured signal as time-base signal, starts/stops measurement signal warp
Cross d trigger synchronous, reduce because start/stop measurement signal asynchronous with clock signal to be measured cause to measure inaccurate；
Additionally, the number of putting of the reset signal of two divided-frequency chip and latch in three road path units, programmable frequency divider to enable signals equal
By with start/stop control signal and provide, automatically reset before measurement and put several purposes to reach each startup, improve test
Efficiency；Identical three road path units, include positive/negative Sexual behavior mode 201 and 203, fixing two divided-frequency 202 respectively, can compile
Journey frequency dividing (2048 > n >=2) 204 and latch 205 IC chip, said integrated circuit chip is all from semi company
Frequency is more than the 100ep series ecl device design of 3ghz, and clock frequency to be measured is up to 2.5ghz；In pcb design, three lead to
Road layout is consistent, cabling is strictly isometric, and differential signal line carries out 100 ω impedance control, as much as possible by placement-and-routing to circuit
The impact of performance is reduced to minimum；Described fpga unit 106 produces and starts/stop measurement signal, in path 1,2,3 unit
Positive/negative polarity selection signal, the frequency dividing of programmable frequency divider put the control signals such as number, can adopt with rear end time interval measuring circuit
With a piece of fpga design, save resources of chip, decreased the burden of cpu, improve the motility of design.
As shown in figure 3, the invention provides a kind of method extracting clock signal time interval parameter to be measured, the method is
By putting several controls to positive/negative Sexual behavior mode in three road path units and frequency programmable dividing, three paths lock three respectively
The accordingly edge of clock signal to be measured, each other combination of two can once extract three time interval parameters (as positive/negative week
Phase, positive/negative pulsewidth and positive/negative n cycle etc.) or adjacent periods value, automatically resetted by circuit before measurement startup and divided
Put number, improve testing efficiency, and can achieve randomization.Concretely comprise the following steps () taking path unit 103 as a example:
(1), clock signal to be measured is output as four tunnels through clock distribution unit, in wherein one road a access channel unit 103
Positive/negative selection chip 201 carries out positive negative selection, and its output waveform is illustrated in figure 3 a+ or a-；
(2), the positive/negative input selecting chip 201 outfan to access fixing two divided-frequency chip 202, after its two divided-frequency
Output accesses positive/negative selection chip 203 and carries out positive negative selection, and at this moment its output waveform has four kinds of combinations, is illustrated in figure 3 ((a+
÷ 2)+), ((a+ ÷ 2) -), ((a- ÷ 2)+) or ((a- ÷ 2) -)；
(3), positive/negative selection chip 203 output accesses programmable frequency divider 204, and its divider ratio may be configured as 2048 > n >=
2 it is assumed here that divider ratio is 2, and its output waveform is illustrated in figure 3 ((a+ ÷ 2)+÷ 2), ((a+ ÷ 2)-÷ 2), ((a- ÷ 2)
+ ÷ 2) or ((a- ÷ 2)-÷ 2)；
(4), programmable frequency divider 204 output accesses the input of latch 205, and the signal after latch is along as in Fig. 3
1., 2., 3. or 4..
(5) as shown in the figure 1. and 2. between time interval be the positive period of measured signal；In the same manner 1. and 3. between
Time interval is the negative pulsewidth of measured signal；1. the time interval between and 4. is the positive pulsewidth of measured signal；2. and 3.
Between time interval be measured signal negative cycle.The frequency dividing that n frequency dividing in Fig. 2 only need to be changed is put number just can to realize n all
The measurement (2048 > n >=2) of phase, is easily achieved the test of various parameters by the programming of fpga.
Claims (3)
1. a kind of extract clock signal time interval parameter to be measured circuit it is characterised in that: include clock distribution unit, open
Dynamic/stop control unit, circuit structure identical three road path unit, fpga unit, wherein:
Described clock distribution unit is made up of the buffer integrated circuit chip of differential comparator and a point four, clock distribution unit
Output is connected with the input of startup/stop control unit, three road path units inputs respectively, differential comparator feeding to be measured when
Clock signal is divided into four tunnel outputs after one point four of buffer, and the clock signal to be measured of four tunnel outputs is respectively fed to start/stop
Only control unit, three road path units；
Described startup/stop control unit is made up of single d trigger, and startup/stop control unit output par, c connects to three
Road path unit, described fpga unit has part output to connect to the input of startup/control unit, and what clock distribution unit exported treats
Survey the input end of clock that clock signal sends into startup/stop control unit d trigger, fpga unit produces and starts/stop measurement
Signal simultaneously sends into the data input pin of startup/stop control unit d trigger, and startup/stop control unit is believed with clock to be measured
Number produce as reference signal synchronous averaging/stopping measurement signal and to start/to stop control signal, start/stop control signal and lead to
Cross the output difference output of startup/stop control unit, wherein part starts/stop control signal feeding three road path units；
In described path unit, every road path unit is respectively by the first positive/negative selection chip, two divided-frequency chip, the second positive/negative choosing
Select chip, programmable frequency divider, latch are sequentially connected composition,
Selection chip input positive/negative with the path unit of every road first is connected respectively for described clock distribution unit output, described
Fpga unit have part output respectively with every road path unit in first positive/negative select chip, second positive/negative select chip, can
Programming frequency division device connects, described startup/stop control unit part output respectively with two divided-frequency chip in the path unit of every road, can
Programming frequency division device, latch connect, the clock signal to be measured of clock distribution unit output send in the path unit of every road first just/
Negative selection chip, clock signal to be measured sequentially pass through first positive/negative select the positive negative selection of chip, two divided-frequency chip frequency dividing, second
The positive/negative selection positive negative selection of chip, programmable frequency divider frequency dividing, clock signal to be measured is exported by latch after latches
Locking edge edge, the startup/stopping control signal of described startup/stop control unit output be respectively fed to two divided-frequency chip, can
The number of putting of programming frequency division device, latch, the reset signal as two divided-frequency chip and latch and programmable frequency divider enables
Signal, produce in described fpga unit positive/negative polarity selection signal, frequency dividing put several control signals, positive/negative polarity selection signal by
Fpga unit is respectively fed to the first positive/negative selection chip, the second positive/negative selection chip, and it is mono- by fpga that frequency dividing puts several control signals
Unit sends into programmable frequency divider.
2. according to claim 1 a kind of extract clock signal time interval parameter to be measured circuit it is characterised in that: institute
When stating differential comparator single ended input clock signal to be measured, differential comparator does not input the input end grounding of clock signal to be measured,
Or connect a fixing comparative level.
3. a kind of clock signal time interval extracting method to be measured based on circuit described in claim 1 it is characterised in that: pass through
Fpga unit is to the positive/negative Sexual behavior mode selecting chip positive/negative in three road path units, and the frequency dividing of programmable frequency divider is put
The control of number, three road path units lock the edge of three corresponding clock signals to be measured respectively, by three clock signals to be measured
Combination of two can once extract three time interval parameters or adjacent periods value each other at edge.
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Families Citing this family (3)
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| CN109471354B (en) * | 2018-12-13 | 2020-09-08 | 中国科学院国家授时中心 | Dead zone compensation device and method for precise time interval measurement |
| CN109738681B (en) * | 2018-12-26 | 2021-04-13 | 中电科思仪科技股份有限公司 | Dual-path acquisition path multiplexing circuit, sampling control method and data splicing method |
| US11422184B1 (en) | 2021-04-14 | 2022-08-23 | Apple Inc. | Multi-die debug stop clock trigger |
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