CN220626587U - Clock signal detection device for FPGA prototype verification board - Google Patents
Clock signal detection device for FPGA prototype verification board Download PDFInfo
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- CN220626587U CN220626587U CN202322198419.XU CN202322198419U CN220626587U CN 220626587 U CN220626587 U CN 220626587U CN 202322198419 U CN202322198419 U CN 202322198419U CN 220626587 U CN220626587 U CN 220626587U
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- 238000012795 verification Methods 0.000 title claims abstract description 32
- 238000001514 detection method Methods 0.000 title claims abstract description 24
- 238000005070 sampling Methods 0.000 claims abstract description 35
- 238000004891 communication Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The utility model provides a clock signal detection device of an FPGA prototype verification board, which comprises: an internal clock generation circuit of the field programmable gate array FPGA prototype verification board; and the sampling clock circuit is electrically connected with the output end of the internal clock generation circuit, the clock frequency of the sampling clock circuit is higher than that of the internal clock generation circuit, and the sampling clock circuit samples the clock signal generated by the internal clock generation circuit and outputs the sampling signal to the upper computer for display. The method and the device can realize sampling detection of the clock signal of the FPGA prototype verification board so as to check the missing clock signal in time, ensure the normal operation of the system and improve the accuracy and efficiency of the FPGA prototype verification.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a clock signal detection device of an FPGA prototype verification board.
Background
An FPGA (field programmable gate array) is a programmable logic device, a circuit can be customized at will, the FPGA greatly promotes the development of digital design, plays an important role in rapid prototyping, and a clock plays an important role in the FPGA.
Disclosure of Invention
The technical problem to be solved by the utility model is to provide the clock signal detection device for the FPGA prototype verification board, so that the clock signal detection for the FPGA prototype verification board is realized, the missing clock signal can be checked in time, the normal operation of the system is ensured, and the accuracy and the efficiency of the FPGA prototype verification are improved.
In order to solve the technical problems, the technical scheme of the utility model is as follows:
an FPGA prototype verification board clock signal detection apparatus, comprising:
an internal clock generation circuit of the field programmable gate array FPGA prototype verification board;
and the sampling clock circuit is electrically connected with the output end of the internal clock generation circuit, the clock frequency of the sampling clock circuit is higher than that of the internal clock generation circuit, and the sampling clock circuit samples the clock signal generated by the internal clock generation circuit and outputs the sampling signal to the upper computer for display.
Optionally, the internal clock generating circuit includes:
a global clock differential input buffer receiving a dedicated clock signal;
a global buffer electrically connected to the global clock differential input buffer;
a mixed mode clock manager electrically connected to the global buffer;
a global output buffer electrically connected to the mixed mode clock manager;
the global buffer inputs the differential clock signal to the mixed mode clock manager, and the mixed mode clock manager inputs the differential clock signal to the global output buffer and outputs the differential clock signal to the global output buffer.
Optionally, the sampling clock circuit includes:
and the clock input end of the trigger is electrically connected with the clock output end of the mixed mode clock manager, and the differential clock signal output by the mixed mode clock manager enters the trigger to sample the clock signal and detects whether the differential clock signal is missing.
Optionally, the latch end of the trigger is electrically connected with the clock locking end of the mixed mode clock manager, and when no external clock signal is input, the clock signal with the frequency higher than a preset value output by the clock locking end of the mixed mode clock manager is adopted by the trigger to sample the differential clock signal output by the mixed mode clock manager.
Optionally, the data input end of the trigger is used for inputting a data signal, and the output end of the trigger is connected with the upper computer in a communication manner through a serial port, and is used for outputting a sampling signal of the differential clock signal and outputting the sampling signal to the upper computer for displaying.
Optionally, the mixed mode clock manager includes:
an input clock signal selector;
a frequency divider electrically connected to the clock signal selector;
a phase frequency selector electrically connected to the frequency divider;
a voltage converter electrically connected to the phase frequency selector;
a ring filter electrically connected to the voltage converter;
an oscillator electrically connected to the loop filter;
a plurality of output clock signal selectors electrically connected to the oscillator;
the input clock signal selector selects one of at least two input differential clock signals, sequentially inputs the selected differential clock signal into the frequency divider, the phase frequency selector, the voltage converter, the ring filter and the oscillator to be output to the output clock signal selectors, and the output clock signal selector outputs corresponding differential clock signals.
Optionally, the plurality of output clock signal selectors includes: an 8-way output clock signal selector, wherein the eighth clock signal selector outputs a feedback clock signal to the feedback selector; the first to fourth output clock signal selectors supply differential clock signals 180 degrees inverted and output.
Optionally, the mixed mode clock manager further includes: the latch detection circuit is electrically connected with the output end of the frequency divider and the output end of the feedback selector; the output end of the feedback selector is also electrically connected with the input end of the phase frequency selector.
Optionally, the output end of the oscillator generating frequency is further electrically connected with the input end of the phase frequency selector, the oscillator generating frequency is divided by M times and fed back to the phase frequency selector, and M is a positive integer.
The scheme of the utility model at least comprises the following beneficial effects:
in the scheme, the internal clock generation circuit of the FPGA prototype verification board is arranged through the field programmable gate array; and the sampling clock circuit is electrically connected with the output end of the internal clock generation circuit, the clock frequency of the sampling clock circuit is higher than that of the internal clock generation circuit, and the sampling clock circuit samples the clock signal generated by the internal clock generation circuit and outputs the sampling signal to the upper computer for display. The clock signal detection of the FPGA prototype verification board is realized, so that missing clock signals can be checked in time, the normal operation of the system is ensured, and the accuracy and the efficiency of the FPGA prototype verification are improved.
Drawings
FIG. 1 is a schematic diagram of an FPGA prototype verification board clock signal detection apparatus of the present utility model;
FIG. 2 is a schematic diagram of a sampling clock circuit of the present utility model;
fig. 3 is a schematic circuit configuration diagram of the mixed mode clock manager of the present utility model.
Detailed Description
Exemplary embodiments of the present utility model will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present utility model are shown in the drawings, it should be understood that the present utility model may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art.
As shown in fig. 1, an embodiment of the present utility model provides a clock signal detection device for an FPGA prototype verification board, including:
an internal clock generation circuit of the field programmable gate array FPGA prototype verification board;
and the sampling clock circuit is electrically connected with the output end of the internal clock generation circuit, the clock frequency of the sampling clock circuit is higher than that of the internal clock generation circuit, and the sampling clock circuit samples the clock signal generated by the internal clock generation circuit and outputs the sampling signal to the upper computer for display.
In this embodiment, the clock signal generated by the internal clock generating circuit is sampled by the sampling clock circuit having a higher clock frequency than the internal clock generating circuit, and the sampled signal is outputted to the upper computer for display. The clock signal detection of the FPGA prototype verification board is realized, so that missing clock signals can be checked in time, the normal operation of the system is ensured, and the accuracy and the efficiency of the FPGA prototype verification are improved.
In an alternative embodiment of the present utility model, the internal clock generation circuit includes:
a global clock differential input buffer 11 receiving a dedicated clock signal;
a global buffer 12 electrically connected to the global clock differential input buffer;
a mixed mode clock manager 13 electrically connected to the global buffer;
a global output buffer 14 electrically connected to the mixed mode clock manager;
wherein, the differential clock signal output by the global clock differential input buffer 11 is input to the global buffer 12, the global buffer 12 inputs the differential clock signal to the mixed mode clock manager 13, and the differential clock signal is input to the global output buffer 14 by the mixed mode clock manager 13 and output by the global output buffer 14.
In the embodiment, the special clock signal is adopted, so that the method is applicable to general wiring resources, has smaller delay, can reduce clock offset and meets time sequence requirements; under the condition that the frequency is higher than 100MHz, the common mode noise can be restrained by using the differential clock, and the noise resistance is good; the input global buffer is a first-stage global buffer connected with a special clock signal input pin; the global clock differential input buffer 11 is a differential form of input global buffer, when signals are input from a pair of differential global clock pins, the signals enter the global clock differential input buffer 11 and then enter the global buffer 12, and the outputs of the global buffer 12 reach IOBs (input output blocks), CLBs (cell logic blocks) and the like inside the FPGA, so that delay and jitter of clock signals inside the FPGA are minimized.
In an alternative embodiment of the present utility model, as shown in fig. 2, the sampling clock circuit includes:
and the clock input end of the trigger is electrically connected with the clock output end of the mixed mode clock manager 13, and the differential clock signal CLK_OUT output by the mixed mode clock manager 13 enters the trigger to perform clock signal sampling and detects whether the differential clock signal is missing.
Specifically, the latch terminal R of the flip-flop is electrically connected to the clock locking terminal of the mixed mode clock manager 13, and when no external clock signal is input, the flip-flop samples the differential clock signal clk_out output by the mixed mode clock manager 13 by using the clock signal Locked output by the clock locking terminal of the mixed mode clock manager 13 with a frequency higher than a preset value.
Further, the data input end D of the trigger is used for inputting a data signal, and the output end Q of the trigger is connected with the upper computer in a communication manner through a serial port, and is used for outputting a sampling signal of the differential clock signal and outputting the sampling signal to the upper computer for displaying.
In this embodiment, the clock signal of the mixed mode clock manager 13 is sampled by using a sampling clock circuit with a higher frequency, so that the missing of the clock signal, for example, the jitter and missing of the rising edge and the falling edge of the clock signal can be detected effectively, and the clock signal can be further displayed on the upper computer, so that the real-time situation of the clock signal can be observed conveniently, and the clock signal can be adjusted in time.
As shown in fig. 3, in an alternative embodiment of the present utility model, the mixed mode clock manager 13 includes: an input clock signal selector 31; a frequency divider electrically connected to the clock signal selector 31; a phase frequency selector electrically connected to the frequency divider; a voltage converter electrically connected to the phase frequency selector; a ring filter electrically connected to the voltage converter; an oscillator electrically connected to the loop filter; a plurality of output clock signal selectors electrically connected to the oscillator;
the input clock signal selector 31 selects one of the at least two input differential clock signals, sequentially inputs the selected differential clock signal to the frequency divider, the phase frequency selector, the voltage converter, the ring filter, and the oscillator, outputs the selected differential clock signal to the plurality of output clock signal selectors, and outputs the corresponding differential clock signal from the output clock signal selectors.
Further, the plurality of output clock signal selectors includes: the 8-way output clock signal selector specifically comprises: a first output clock signal selector 32, a second output clock signal selector 33, a third output clock signal selector 34, a fourth output clock signal selector 35, a fifth output clock signal selector 36, a sixth output clock signal selector 37, a seventh output clock signal selector 38, an eighth output clock signal selector 39; wherein the eighth output clock signal selector 39 outputs the feedback clock signal to the feedback selector 40; the 1 st to 4 th output clock signal selectors supply differential clock signals 180 degrees inverted and output.
Further, the mixed mode clock manager 13 further includes: a latch detection circuit, one end of which is electrically connected with the output end of the frequency divider and with the output end of the feedback selector 40; the output of the feedback selector 40 is also electrically connected to the input of the phase frequency selector.
Further, the output end of the oscillator generating frequency is also electrically connected with the input end of the phase frequency selector, the oscillator generating frequency is divided by M times and fed back to the phase frequency selector, and M is a positive integer.
In this embodiment, the mixed mode clock manager 13 has 2 clock inputs, optionally 1 way, and the input clock passes through the frequency divider (D), the phase-frequency selector (PFD, phase-frequency detector), the voltage converter, the Loop Filter (LF) and then generates a voltage with a certain amplitude, and inputs the voltage to the oscillator, the oscillator generates a high-frequency clock with a frequency proportional to the amplitude of the input voltage, and divides the high-frequency clock by M times and feeds back the high-frequency clock to the phase-frequency selector, so that the output frequency of the oscillator is a stable high-frequency clock with M times of the input frequency, and the clock is divided by different multiples (user-adjustable) to output the clock signal to the multiple output clock signal selector, wherein the 1 st way output and the feedback output can be divided by a decimal number (counter M), and the 1 st to 4 th ways provide an output with 180 degrees of opposite phase, and the output of the oscillator can also accurately adjust the phase.
In the above embodiment of the present utility model, the clock signal generated by the internal clock generating circuit is sampled by the sampling clock circuit having a clock frequency higher than that of the internal clock generating circuit of the FPGA, and the sampled signal is outputted to the upper computer for display. The clock signal detection of the FPGA prototype verification board is realized, so that missing clock signals can be checked in time, the normal operation of the system is ensured, and the accuracy and the efficiency of the FPGA prototype verification are improved.
While the foregoing is directed to the preferred embodiments of the present utility model, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present utility model, and such modifications and adaptations are intended to be comprehended within the scope of the present utility model.
Claims (9)
1. The utility model provides a FPGA prototype verification board clock signal detection device which characterized in that includes:
an internal clock generation circuit of the field programmable gate array FPGA prototype verification board;
and the sampling clock circuit is electrically connected with the output end of the internal clock generation circuit, the clock frequency of the sampling clock circuit is higher than that of the internal clock generation circuit, and the sampling clock circuit samples the clock signal generated by the internal clock generation circuit and outputs the sampling signal to the upper computer for display.
2. The FPGA prototype verification board clock signal detection apparatus according to claim 1, wherein said internal clock generation circuit comprises:
a global clock differential input buffer receiving a dedicated clock signal;
a global buffer electrically connected to the global clock differential input buffer;
a mixed mode clock manager electrically connected to the global buffer;
a global output buffer electrically connected to the mixed mode clock manager;
the global buffer inputs the differential clock signal to the mixed mode clock manager, and the mixed mode clock manager inputs the differential clock signal to the global output buffer and outputs the differential clock signal to the global output buffer.
3. The FPGA prototype verification board clock signal detection apparatus according to claim 2, wherein said sampling clock circuit comprises:
and the clock input end of the trigger is electrically connected with the clock output end of the mixed mode clock manager, and the differential clock signal output by the mixed mode clock manager enters the trigger to sample the clock signal and detects whether the differential clock signal is missing.
4. The FPGA prototype verification board clock signal detection apparatus according to claim 3, wherein the latch terminal of the flip-flop is electrically connected to the clock lock terminal of the mixed mode clock manager, and the flip-flop samples the differential clock signal output by the mixed mode clock manager with a clock signal output by the clock lock terminal of the mixed mode clock manager having a frequency higher than a preset value when no external clock signal is input.
5. The device for detecting clock signals of the FPGA prototype verification board according to claim 4, wherein the data input end of the trigger is used for inputting data signals, and the output end of the trigger is connected with the upper computer in a communication manner through a serial port and is used for outputting sampling signals of the differential clock signals and outputting the sampling signals to the upper computer for displaying.
6. The FPGA prototype verification board clock signal detection apparatus according to claim 2, wherein said mixed mode clock manager comprises:
an input clock signal selector;
a frequency divider electrically connected to the clock signal selector;
a phase frequency selector electrically connected to the frequency divider;
a voltage converter electrically connected to the phase frequency selector;
a ring filter electrically connected to the voltage converter;
an oscillator electrically connected to the loop filter;
a plurality of output clock signal selectors electrically connected to the oscillator;
the input clock signal selector selects one of at least two input differential clock signals, sequentially inputs the selected differential clock signal into the frequency divider, the phase frequency selector, the voltage converter, the ring filter and the oscillator to be output to the output clock signal selectors, and the output clock signal selector outputs corresponding differential clock signals.
7. The FPGA prototype verification board clock signal detection apparatus according to claim 6, wherein said plurality of output clock signal selectors comprises: an 8-way output clock signal selector, wherein the eighth clock signal selector outputs a feedback clock signal to the feedback selector; the first to fourth output clock signal selectors supply differential clock signals 180 degrees inverted and output.
8. The FPGA prototype verification board clock signal detection apparatus according to claim 7, wherein said mixed mode clock manager further comprises: the latch detection circuit is electrically connected with the output end of the frequency divider and the output end of the feedback selector; the output end of the feedback selector is also electrically connected with the input end of the phase frequency selector.
9. The FPGA prototype-verification board clock signal detection apparatus of claim 6, wherein the output of the oscillator that generates frequency is further electrically connected to the input of the phase frequency selector, and the oscillator generates a high frequency clock with a frequency that is in a preset ratio to the input voltage amplitude, divided by M times, and fed back to the phase frequency selector, where M is a positive integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322198419.XU CN220626587U (en) | 2023-08-16 | 2023-08-16 | Clock signal detection device for FPGA prototype verification board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322198419.XU CN220626587U (en) | 2023-08-16 | 2023-08-16 | Clock signal detection device for FPGA prototype verification board |
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| Publication Number | Publication Date |
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| CN220626587U true CN220626587U (en) | 2024-03-19 |
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| CN202322198419.XU Active CN220626587U (en) | 2023-08-16 | 2023-08-16 | Clock signal detection device for FPGA prototype verification board |
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- 2023-08-16 CN CN202322198419.XU patent/CN220626587U/en active Active
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