CN101359014B - Built-in dithering measuring circuit - Google Patents
Built-in dithering measuring circuit Download PDFInfo
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- CN101359014B CN101359014B CN2007101382107A CN200710138210A CN101359014B CN 101359014 B CN101359014 B CN 101359014B CN 2007101382107 A CN2007101382107 A CN 2007101382107A CN 200710138210 A CN200710138210 A CN 200710138210A CN 101359014 B CN101359014 B CN 101359014B
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Abstract
The present invention discloses a time jitter measuring circuit and a correcting method which is used for correcting the time jitter measurement circuit. The measuring circuit comprises a synchronous two-phase detection circuit and a decision circuit. When the invention is in the test mode, the probability distribution map of the clock signals to be detected can be acquired. When the invention is in the correction mode, a random clock signal can be used for correcting the synchronous two-phase detection circuit. The random clock signal can be transmitted from the outside or be generated by the freely oscillating oscillator in the circuit to be detected. The decision circuit is used for the logic operation, data latching and counting of the phase relation detected by the synchronous two-phase detection circuit, so as to acquire the counting value distribution and the probability distribution of the jitter.
Description
Technical field
The present invention relates to a kind of dithering measuring circuit, and particularly relate to a kind of built-in clock jitter measuring circuit.
Background technology
Data pulse (Data Pulse) is when transmitting on transmission line, if signal is shaken, (Clock Recovery Circuit, CDR) or phaselocked loop (PLL) generation problem, even data may be lost may to make the clock reflex circuit.Shake can be defined as: the rising edge of signal (or falling edge) with respect to the time offset of its position ideal time.Fig. 1 demonstrates the definition of shake.Shake can make that (Bit Error Rate BER) improves, and reduces the service quality (Qualityof Service) of total system for the bit error rate of receiving end.
Time error (TIE, Time Interval Error) parameter is one of parameter of shake, and its meaning is a time point in office, the phase differential between signal bits that receives (or pulse) and reference clock.
Generally speaking, shake can classify as the shake of quantitative property (Deterministic Jitter, DJ) with randomness shake (Random Jitter, RJ).Randomness is dithered as the sequential noise level shake that produces at random.Its distribution situation is generally Gaussian distribution (Gaussian Distribution), also can be described as regular distribution (Normal Distribution).
With present, can utilize external ATE (automatic test equipment) (ATE, automatic testequipment) to measure shake.But, because will export signal to ATE (automatic test equipment), so signal must be by exporting/go into pin.Thus, measured shake may be original shake.In addition, ATE (automatic test equipment) incurs a considerable or great expense, and also can additionally increase testing cost.
So, a kind of BIST circuit that can accurately measure shake better can be arranged, can reduce the use of testing cost, test duration and minimizing surveying instrument.
Summary of the invention
In view of this, the invention provides a kind of built-in dithering measuring circuit, it can accurately measure shake, can reduce the use of testing cost, test duration and minimizing surveying instrument again.
The invention provides a kind of built-in dithering measuring circuit, the delay buffer in the synchronous two-phase detecting device of its recoverable is to accurately measure shake.
The invention provides a kind of built-in dithering measuring circuit, it can be after each sampling, and the synchronous two-phase detecting device of resetting is to reduce hysteresis effect.
One of example of the present invention proposes a kind of built-in dithering measuring circuit, the shake that is used to measure clock signal to be measured.This dithering measuring circuit comprises: a synchronous two-phase testing circuit, carry out different delays to this clock signal to be measured with a reference clock signal, and detect the phase relation between this delay back clock signal to be measured and this delay back reference clock signal; And a decision-making circuit, the phase relation that this synchronous two-phase testing circuit is detected is carried out logical operation, data bolt-lock and counting, to obtain a count value and probability distribution relevant for this shake of this clock signal to be measured.
Another example of the present invention provides a kind of time difference measurements circuit, be used to measure the mistiming between the clock signal to be measured that a reference clock signal and a circuit under test export, this circuit under test comprises an oscillation source at least, this time difference measurements circuit comprises: a synchronous two-phase testing circuit, be coupled to this circuit under test, this synchronous two-phase testing circuit comprises that one first postpones the buffer cell and the second delay buffer cell, when this oscillation source is in a normal operation, obtain a probability distribution figure of a phase place of this clock signal to be measured, proofread and correct this with this probability distribution figure and first postpone buffer cell and the second delay buffer cell a delay-time difference that this reference clock signal was caused according to this phase place of this clock signal to be measured; And a decision-making circuit, be coupled to this synchronous two-phase testing circuit, the phase relation that this synchronous two-phase testing circuit is detected is carried out logical operation, data bolt-lock and counting, to obtain a count value relevant for this mistiming.
Another example of the present invention provides a kind of time difference measurements circuit, be used to measure the mistiming between the clock signal to be measured that a reference clock signal and a circuit under test export, this circuit under test comprises an oscillation source at least, this time difference measurements circuit comprises: a synchronous two-phase testing circuit, be coupled to this circuit under test, this synchronous two-phase testing circuit comprises that one first postpones the buffer cell and the second delay buffer cell, when this oscillation source is in a free oscillation, obtain a probability distribution figure of a phase place of this clock signal to be measured, proofread and correct this with this probability distribution figure and first postpone buffer cell and the second delay buffer cell a delay-time difference that this reference clock signal was caused according to this phase place of this clock signal to be measured; And a decision-making circuit, be coupled to this synchronous two-phase testing circuit, the phase relation that this synchronous two-phase testing circuit is detected is carried out logical operation, data bolt-lock and counting, to obtain a count value relevant for this mistiming.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 demonstrates the definition of shake.
Fig. 2 shows the block schematic diagram according to the built-in dithering measuring circuit of first embodiment of the invention.
The synchronous two-phase detecting device of Fig. 3 displayed map 2 and the circuit block diagram of decision-making circuit.
Fig. 4 is presented under the test pattern, the probability distribution functional arrangement of the phase place of clock signal to be measured.
Fig. 5 is presented under the correction mode, the probability distribution functional arrangement of the phase place of clock signal to be measured.
Fig. 6 shows the probability distribution functional arrangement that adds up of the phase place of clock signal to be measured.
Fig. 7 shows the analog result of first embodiment.
Fig. 8 shows the circuit diagram of the built-in dithering measuring circuit of second embodiment of the invention.
The reference numeral explanation
21: circuit under test
23: synchronous two-phase detecting device
25,25 ｀: decision-making circuit
301-303: delay buffer
304-305: phase detection unit
311-312,315-316: logical circuit
313-314: bolt lock device
317: multiplexer
318,318a, 318b: counter
Embodiment
In order to make content of the present invention more clear, below the example that can implement according to this really as the present invention especially exemplified by several embodiment.
Fig. 2 shows the block schematic diagram according to the built-in dithering measuring circuit of first embodiment of the invention.This dithering measuring circuit mainly comprises: synchronous two-phase detecting device 23 and decision-making circuit 25.This dithering measuring circuit is used to detect the shake of the clock signal clk test to be measured of circuit under test 21, and just clock signal clk test is with respect to the error of reference clock signal CLKref.This circuit under test 21 can be PLL, CDR, DLL (delay phase-locked loop), or other can produce the similar circuit of another clock signal according to reference clock signal.
Two-phase detecting device 23 is used to detect the phase relation between this clock signal clk test to be measured and reference clock signal CLKref synchronously, and exports two signal S1/S2 to decision-making circuit 25.Decision-making circuit 25 count signal S1/S2 to be obtaining count value R1/R2, and deliver to the computing unit/software for calculation (not shown) of rear end, to obtain jitter value and its RMS value.
Fig. 3 demonstrates the circuit block diagram of synchronous two-phase detecting device 23 and decision-making circuit 25.Two-phase detecting device 23 comprises synchronously: delay buffer 301-303 and phase detection unit 304-305.Decision-making circuit 25 comprises logical circuit 311-312, bolt lock device 313-314, logical circuit 315-316, multiplexer 317 and counter 318.
Phase detection unit 304-305 is such as being D type flip-flop (DFF).Phase detection unit 304-305 has: data input pin D, and input end of clock C, end RST and data output end Q reset.The data input pin D of phase detection unit 304-305 accepts to postpone back reference clock signal D1 and D2 respectively.The input end of clock C of phase detection unit 304-305 accepts to postpone back clock signal D 3.The replacement end RST of phase detection unit 304-305 accepts reset signal RST.The data output end Q of phase detection unit 304-305 is output signal S1 and S2 respectively.
Signal S1 (its value may be 1 or 0) representative postpones the phase relation between back reference clock signal D1 and delay back clock signal D3.Signal S2 (its value may be 1 or 0) representative postpones the phase relation between back reference clock signal D2 and delay back clock signal D3.
In addition, for solving hysteresis effect, in first embodiment, when taking a sample one (just producing a signal S1/S2), reset signal RST just can reset phase detection unit 304 and 305.
The output signal S1 and the S2 of logical circuit 311 and 312 receiving phase detecting units 304 and 305. Bolt lock device 313 and 314 is the output signal of bolt-lock logical circuit 311 and 312 according to postponing back clock signal D3. Logical circuit 315 and 316 receives output signal, delay back clock signal D3 and the enable signal EN of bolt lock device 313 and 314, and wherein, enable signal EN is produced by the external testing instrument. Bolt lock device 313 and 314 and the combination of logical circuit 315 and 316 can produce pulse signal. Logical circuit 311 and 312 output signal are 1, then logical circuit 315 and 316 output pulse signals; Output signal as logical circuit 311 and 312 is 0, then logical circuit 315 and 316 output pulse signal not.
The BIST circuit of first embodiment has two kinds of operator schemes: test pattern and correction mode.Under test pattern, the oscillation source of circuit under test (as voltage-controlled oscillator VCO) meeting normal running; And under correction mode, this oscillation source then is under the free oscillation (free-run).But in another embodiment of the present invention, also can import needed clock signal clk test to be measured from the outside and do correction mode.That is to say that when being in correction mode, needed random clock signal may be imported by the outside; Perhaps, needed random clock signal can be produced by the free-running oscillator that is in of circuit under test inside.
Please refer to Fig. 4, it is presented under the test pattern, the probability distribution functional arrangement of the phase place ψ d of clock signal clk test to be measured (PDF, probability distribution function).Under test pattern, suppose that amount of jitter is regular distribution.According to the value of signal S1/S2, the phase place ψ d of clock signal clk test to be measured can be divided into three blocks: less than ψ
-(work as S1=0, S2=0); Between ψ
-With ψ
+Between (work as S1=1, S2=0); And greater than ψ
+(work as S1=1, S2=1).
In Fig. 4, P1-P3 represents the area (P1+P2+P3=1) of these three blocks respectively, and just, phase place ψ d is positioned at the probability of which block.Such as, P1=R1/ (number of samples), P2=R2/ (number of samples).Symbol T representative, when S1=1 and S2=0, the scope of phase place ψ d.
Please refer to Fig. 5, it is presented under the correction mode, the probability distribution functional arrangement of the phase place ψ d of clock signal clk test to be measured.Because the oscillation source of circuit under test is under the free oscillation, so clock signal clk test to be measured can produce at random.That is to say that between clock signal clk test to be measured and reference clock signal CLKref and onrelevant, and the probability distribution functional arrangement of the phase place ψ d of clock signal clk test to be measured can present even distribution.Symbol T0 represents the reference clock signal CLKref cycle of (just postponing back reference clock signal D1).Symbol T represents the delay-time difference of delay buffer 301 and 302.CLKrefd1 and CLKrefd2 be reference clock signal D1 and D2 after the delay buffer 301 of representative graph 3 and 302 delays that produced respectively.The equally distributed statistical property that is produced when being in free oscillation according to the oscillation source of circuit under test can obtain: T=P2 ' * T0.According to T0 and P2 ', can obtain the delay-time difference of delay buffer 301 and 302.
Fig. 6 shows the probability distribution functional arrangement that adds up (CDF, cumulative distributionfunction) of phase place ψ d.Transverse axis then is the phase place ψ d of clock signal clk test to be measured, and is unit with root mean square (RMS) value (σ).According to P1, P2 utilizes Fig. 6 can check in phase error x
-With x
+(is unit with σ).More calculate the value of T according to P2 '.Again by T and x
-, x
+Relation, can obtain the pairing phase place size of a σ.If be formulated, then be:
σ＝T/(x
+-x
-)
Such as, work as P1=0.1100, during P2=0.5414, the corresponding x that goes out
-Be-1.23 x
+Then be+0.39.So, σ=0.04/ (0.39-(1.23))=0.025.
Fig. 7 display simulation result.Reference clock signal CLKref is 2.5GHz, and the σ of the shake of clock signal clk test to be measured is 10ps (being 0.025UI).
2 jitter value error comparison sheets under please refer to have or not the difference of feed-in reset signal RST to phase detectors to understand more.
Following table 1 shows that not feed-in reset signal RST is to the resulting jitter value error of phase detectors comparison sheet.
Table 1
| P1 | P2 | T | Error | |
| Desirable correcting state | 0.0809 | 0.5686 | 0.0409 | 8.1％ |
| P1 | P2 | T | | |
| Correcting state | ||||
| 1 | 0.0809 | 0.5686 | 0.0375 | 15.9％ |
| Correcting state 2 | 0.0809 | 0.5686 | 0.0380 | 14.8％ |
| |
0.0809 | 0.5686 | 0.0369 | 17.2％ |
In last table 1, desirable correcting state refers to, and under correction mode, the clock signal clk test to be measured of Fig. 2 is replaced with may command clock signal (being produced by signal generator).The probability distribution functional arrangement of the phase place ψ d of this may command clock signal can present even distribution, and the phase differential between this may command clock signal and reference clock is evenly to distribute.So can proofread and correct accurately.3 representatives of correcting state 1-correcting state are used the different measured results of free oscillation frequency in correction mode.
Following table 2 shows that feed-in reset signal RST is to the resulting jitter error comparison sheet of phase detectors.
Table 2
| P1 | P2 | T | Error | |
| Desirable correcting state | 0.1100 | 0.5414 | 0.0400 | 1％ |
| |
0.1100 | 0.5414 | 0.0389 | 3.8％ |
| Correcting state 2 | 0.1100 | 0.5414 | 0.0392 | 3.0％ |
| |
0.1100 | 0.5414 | 0.0379 | 6.1％ |
Can find out that by table 1 and table 2 as feed-in reset signal RST during to phase detectors, resulting jitter error is smaller really.
Fig. 8 shows the circuit diagram of the BIST circuit of second embodiment of the invention.Basically, the framework of the BIST circuit of second embodiment duplicates in the BIST of first embodiment circuit, and just the multiplexer 317 with Fig. 2 replaces to counter 318a and 318b with counter 318.Function mode as for second embodiment can be learnt by the description content of first embodiment basically, so no longer repeat in this.
In sum, the above embodiment of the present invention has following advantage: circuit area is little, high operating speed and high accuracy.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (14)
1. built-in dithering measuring circuit is used to measure the shake with respect to a reference clock signal of a clock signal to be measured that a circuit under test exports, and this dithering measuring circuit comprises:
One synchronous two-phase testing circuit, be coupled to this circuit under test, this synchronous two-phase testing circuit carries out different delays to this clock signal to be measured with this reference clock signal, and detects the phase relation between this delay back clock signal to be measured and this delay back reference clock signal; And
One decision-making circuit is coupled to this synchronous two-phase testing circuit, and the phase relation that this synchronous two-phase testing circuit is detected is carried out logical operation, data bolt-lock and counting, obtaining a count value relevant for this shake of this clock signal to be measured,
Wherein, this synchronous two-phase testing circuit comprises:
One first postpones buffer cell, postpones this reference clock signal and postpones the back reference clock to produce one first;
One second postpones buffer cell, postpones this reference clock signal and postpones the back reference clock to produce one second; With
One the 3rd postpones buffer cell, postpones this clock signal to be measured to produce this delay back clock to be measured;
Wherein, the 3rd retardation that postpones buffer cell between this first with the retardation of this second delay buffer cell between.
2. dithering measuring circuit as claimed in claim 1, wherein, this synchronous two-phase testing circuit comprises:
One first phase detectors are coupled in this first delay buffer cell and the 3rd and postpone buffer cell, to detect this first phase relation that postpones between back reference clock and this delay back clock signal to be measured; And
One second phase detectors are coupled in this second delay buffer cell and the 3rd and postpone buffer cell, to detect this second phase relation that postpones between back reference clock and this delay back clock signal to be measured;
Wherein, every sampling once, these first and second phase detectors can be reset.
3. dithering measuring circuit as claimed in claim 2, wherein, this decision-making circuit comprises:
One first logical circuit carries out logical operation to an output signal of these first phase detectors and an output signal of these second phase detectors; And
One second logical circuit carries out logical operation to this output signal of these first phase detectors and this output signal of these second phase detectors.
4. dithering measuring circuit as claimed in claim 3, wherein, this decision-making circuit comprises:
One first data bolt lock device postpones back clock signal to be measured and an output signal of this first logical circuit of bolt-lock according to this; And
One second data bolt lock device postpones back clock signal to be measured and an output signal of this second logical circuit of bolt-lock according to this.
5. dithering measuring circuit as claimed in claim 4, wherein, this decision-making circuit comprises:
One the 3rd logical circuit carries out logical operation to an output signal of this first data bolt lock device, this delay back clock signal to be measured and an enable signal; And
One the 4th logical circuit carries out logical operation to an output signal of this second data bolt lock device, this delay back clock signal to be measured and this enable signal.
6. dithering measuring circuit as claimed in claim 5, wherein, this decision-making circuit comprises:
One multiplexer selects one from an output signal of the 3rd logical circuit and an output signal of the 4th logical circuit; And
One first counter is counted an output signal of this multiplexer.
7. dithering measuring circuit as claimed in claim 5, wherein, this decision-making circuit comprises:
One second counter is counted an output signal of the 3rd logical circuit; And
One the 3rd counter is counted an output signal of the 4th logical circuit.
8. time difference measurements circuit is used to measure the mistiming between the clock signal to be measured that a reference clock signal and a circuit under test export, and this circuit under test comprises an oscillation source at least, and this time difference measurements circuit comprises:
One synchronous two-phase testing circuit, be coupled to this circuit under test, this synchronous two-phase testing circuit comprises that one first postpones the buffer cell and the second delay buffer cell, when this oscillation source is in a free oscillation, obtain a probability distribution figure of a phase place of this clock signal to be measured, proofread and correct this with this probability distribution figure and first postpone buffer cell and the second delay buffer cell a delay-time difference that this reference clock signal was caused according to this phase place of this clock signal to be measured; And
One decision-making circuit is coupled to this synchronous two-phase testing circuit, and the phase relation that this synchronous two-phase testing circuit is detected is carried out logical operation, data bolt-lock and counting, obtaining a count value relevant for this mistiming,
Wherein, this first delay buffer cell postpones this reference clock signal and postpones the back reference clock to produce one first; This second delay buffer cell postpones this reference clock signal and postpones the back reference clock to produce one second; And this synchronous two-phase testing circuit more comprises: one the 3rd postpones buffer cell, postpones this clock signal to be measured to produce this delay back clock to be measured;
Wherein, the 3rd retardation that postpones buffer cell between this first with the retardation of this second delay buffer cell between.
9. time difference measurements circuit as claimed in claim 8, wherein, this synchronous two-phase testing circuit comprises:
One first phase detectors are coupled in this first delay buffer cell and the 3rd and postpone buffer cell, to detect this first phase relation that postpones between back reference clock and this delay back clock signal to be measured; And
One second phase detectors are coupled in this second delay buffer cell and the 3rd and postpone buffer cell, to detect this second phase relation that postpones between back reference clock and this delay back clock signal to be measured;
Wherein, every sampling once, these first and second phase detectors can be reset.
10. time difference measurements circuit as claimed in claim 9, wherein, this decision-making circuit comprises:
One first logical circuit carries out logical operation to an output signal of these first phase detectors and an output signal of these second phase detectors; And
One second logical circuit carries out logical operation to this output signal of these first phase detectors and this output signal of these second phase detectors.
11. time difference measurements circuit as claimed in claim 10, wherein, this decision-making circuit comprises:
One first data bolt lock device postpones back clock signal to be measured and an output signal of this first logical circuit of bolt-lock according to this; And
One second data bolt lock device postpones back clock signal to be measured and an output signal of this second logical circuit of bolt-lock according to this.
12. time difference measurements circuit as claimed in claim 11, wherein, this decision-making circuit comprises:
One the 3rd logical circuit carries out logical operation to an output signal of this first data bolt lock device, this delay back clock signal to be measured and an enable signal; And
One the 4th logical circuit carries out logical operation to an output signal of this second data bolt lock device, this delay back clock signal to be measured and this enable signal.
13. time difference measurements circuit as claimed in claim 12, wherein, this decision-making circuit comprises:
One multiplexer selects one from an output signal of the 3rd logical circuit and an output signal of the 4th logical circuit; And
One first counter is counted an output signal of this multiplexer.
14. time difference measurements circuit as claimed in claim 12, wherein, this decision-making circuit comprises:
One second counter is counted an output signal of the 3rd logical circuit; And
One the 3rd counter is counted an output signal of the 4th logical circuit.
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|---|---|---|---|
| CN2007101382107A CN101359014B (en) | 2007-07-31 | 2007-07-31 | Built-in dithering measuring circuit |
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|---|---|---|---|
| CN2007101382107A CN101359014B (en) | 2007-07-31 | 2007-07-31 | Built-in dithering measuring circuit |
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| CN101359014B true CN101359014B (en) | 2010-11-17 |
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| CN108318809B (en) * | 2017-01-16 | 2020-09-01 | 奇景光电股份有限公司 | Built-in self-test circuit for frequency jitter |
| KR102410014B1 (en) * | 2017-08-03 | 2022-06-21 | 삼성전자주식회사 | Clock jitter measurement circuit and semiconductor device including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1493883A (en) * | 2002-10-31 | 2004-05-05 | 联发科技股份有限公司 | Agitating measuring device and measuring method |
| CN1323337C (en) * | 2003-06-23 | 2007-06-27 | 华为技术有限公司 | Method and circuit for conducting real time test for single chip clock shaking |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1493883A (en) * | 2002-10-31 | 2004-05-05 | 联发科技股份有限公司 | Agitating measuring device and measuring method |
| CN1323337C (en) * | 2003-06-23 | 2007-06-27 | 华为技术有限公司 | Method and circuit for conducting real time test for single chip clock shaking |
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