CN110515292B - TDC circuit based on bidirectional running annular carry chain and measuring method - Google Patents
TDC circuit based on bidirectional running annular carry chain and measuring method Download PDFInfo
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Abstract
The invention discloses a TDC circuit based on a bidirectional running annular carry chain and a measuring method. The circuit comprises a standard delay line channel, a non-standard delay line channel and a time analysis module, wherein the two delay line channels respectively comprise four submodules of time extraction, coarse timing, fine timing and timestamp combination. The method comprises the following steps: in a standard delay line channel, a measured signal propagates along a slow delay line, a coarse timing clock signal propagates along a fast delay line, and a fine timing module calculates the time interval between the two signals and transmits the time interval to a timestamp combination module; in a non-standard delay line channel, a measured signal propagates along a fast delay line, a coarse timing clock signal propagates along a slow delay line, and a fine timing module calculates the time interval between the two signals and transmits the time interval to a timestamp combination module; and the time analysis module receives the results of the two channels, and takes the time stamp corresponding to the delay line with the small fine count value as an output result. The invention reduces the root mean square error, improves the TDC resolution and saves the resource cost.
Description
Technical Field
The invention belongs to the technical field of digital measurement of time quantum, and particularly relates to a TDC circuit based on a bidirectional running annular carry chain and a measurement method.
Background
In many high-energy nuclear experiments, a high-resolution time-to-digital converter (TDC) is required to help determine the particle type. TDC can also be used in many applications involving precise timing, such as medical flight Positron Emission Tomography (PET), lidar, Automatic Test Equipment (ATE), and all-digital phase-locked loop (PLL) circuitry. Compared with an Application Specific Integrated Circuit (ASIC), the TDC based on the FPG has the advantages of low cost, strong reconfigurability, strong flexibility and short development period.
A TDC typically comprises two time measurement steps: a coarse timing module is used to extend the entire measurement range and a fine timing module is used to increase the resolution. The fine timing module is used for measuring the time range of the whole period of the coarse timing module. The combination of the coarse timing counter (given by the coarse timing module) and the fine timing counter (given by the fine timing module) generates a time stamp representing the time of occurrence of the event, and a precise time interval is measured by establishing two such TDC channels.
For the FPGA platform, the main technique to build the fine timing module is to tap the delay line. However, in order to construct a high resolution TDC, the length of the carry chain must be quite long, at least exceeding 100 delay units in modern designs, which costs a lot of resources and has a relatively large differential non-linearity (DNL) error and integral non-linearity (INL) error. In the past, there has been proposed a TDC circuit that is organized into a ring-shaped carry chain to form a Ring Oscillator (ROs), and the DNL and INL of such a TDC are much smaller, mostly smaller than 1LSB, and require relatively few delay lines, and cost resources are less, and this method can achieve a resolution lower than 10ps by adjusting the oscillation period, but the accumulated oscillation jitter number ultimately limits the achievable resolution. Since the delay of the ROs is not compensated, its rms error increases proportionally with the square root of the number of oscillations, but too small a resolution cannot be chosen to avoid large rms errors.
Disclosure of Invention
The invention aims to provide a TDC circuit and a measuring method based on a bidirectional running annular carry chain, which have high resolution and low root mean square error.
The technical solution for realizing the purpose of the invention is as follows: a TDC circuit based on a bidirectional running annular carry chain comprises a standard delay line channel, a non-standard delay line channel and a time analysis module, wherein the standard delay line channel and the non-standard delay line channel have the same structure and comprise a time extraction module, a coarse timing module, a fine timing module and a timestamp combination module; the time extraction module, the fine timing module, the timestamp combination module and the time analysis module are sequentially connected, and the coarse timing module is connected with the timestamp combination module;
the time extraction module is used for searching and searching a coarse clock signal which is nearest to the measured signal and appears behind the measured signal, and transmitting the measured signal and the coarse timing clock signal which respectively undergo different delays to the fine timing module;
the fine timing module is used for measuring the time interval between the measured signal and the coarse timing clock signal and generating a fine timing part in a time stamp result;
the coarse timing module is used for generating a coarse timing part in a timestamp result;
the timestamp combination module is used for outputting a complete timestamp result;
and the time analysis module is used for analyzing the time stamp results generated by the two delay line channels, and selecting the time stamp corresponding to the delay line with the relatively small fine count value as the final output result.
Furthermore, the standard delay line channel transmits a measured signal to a slow delay line, and transmits a coarse timing clock signal to a fast delay line; the nonstandard delay line channel transmits the detected signal to the fast delay line, and transmits the coarse timing clock signal to the slow delay line.
Furthermore, the fine timing module comprises a first delay line, a second delay line, a phase discriminator, a fine counter and first to fourth pulse shaping modules;
the input end of the first delay line is connected with a first pulse shaping module; the output end of the first delay line is connected with the data port of the phase discriminator, and is connected with the clock port of the fine counter and the 1-from-2 Mux through the second pulse shaping module, and the 1-from-2 Mux is connected with the input end of the first delay line through an OR gate so as to form a first oscillation ring-shaped carry chain;
the input end of the second delay line is connected with a third pulse shaping module; the output end of the second delay line is connected with the clock port of the phase discriminator and is connected with the input end of the second delay line through a fourth pulse shaping module, a 2-to-1 Mux or an OR gate to form a second oscillation annular carry chain;
the output port of the phase discriminator is connected with the enable port of the fine counter and is used for judging the relative time relationship between the leading signal and the lagging signal and controlling the enable port of the fine counter;
the fine counter is used for outputting a fine timing part in the timestamp result;
and the first pulse shaping module, the second pulse shaping module, the third pulse shaping module and the fourth pulse shaping module are used for controlling the high level duration of a propagation signal in an oscillation loop, so that the fine counting measurement range can cover the coarse counting clock period.
Further, the first delay line comprises n1A delay unit and a delay circuit having n1A first multiplexer of input ports, where n1According to the value of sel delivered by PC terminal1Determining a value; the output end of the ith delay unit is connected with the ith input end of the first multiplexer and is connected with the input end of the (i + 1) th delay unit, wherein i is more than or equal to 1 and is less than or equal to n1-1；
The second delay line comprises n2A delay unit and n2A second multiplexer of inputs, where n2According to the value of sel delivered by PC terminal2Determining a value; the output end of the jth delay unit is connected with the jth input end of the second multiplexer and is connected with the input end of the jth +1 delay unit, wherein j is more than or equal to 1 and is less than or equal to n2-1；
The N input multiplexers respectively correspond to the N delay units of the carry chain, the p output end of each delay unit is connected to the p input end of the multiplexer, and only one connection is effective according to the channel selection value of the SEL set by the PC end, so that the circuit has N different carry chain loops and is dynamically switched and controlled through a PC program; in two lengths each n1、n2In the carry chain of (2), possible combination elements (sel)1,sel2) Is n1×n2Corresponding to each (sel)1,sel2) And calculating the resolution ratio: t iscyc1-Tcyc2Wherein T iscyc1Indicating the period of oscillation, T, during which the first delay line constitutes the carry chaincyc2Representing the oscillation period of the second delay line carry chain; by enumerating sel from 1 to n independently1And sel2And recording the corresponding Tcyc1And Tcyc2The entire combined set can be covered and only n is needed1+n2Performing secondary operation; t is obtained by receiving the oscillation signal at the output terminal of the multiplexer and observing the signal with an external oscilloscopecyc1And Tcyc2Finally by selection (sel)1,sel2) The combination to achieve the target resolution of the TDC.
Furthermore, a cascade inverter longitudinal adjustable chain is respectively inserted between the time extraction module and the fine timing module of the standard delay line channel and the non-standard delay line channel, and is respectively used for tauupAnd τnullAdjusting by modifying the number of inverters to τupAnd τnullAre both positive and approach 0; wherein tau isupFor additional delay of the front-end signals of the signal under test and the clock signal, τnullAn extra delay for the signal under test and the back-end signal of the clock signal.
A TDC (time delay/position converter) measuring method based on a bidirectional running annular carry chain comprises the following steps:
and 3, receiving the results transmitted by the timestamp combination module in the steps 1 and 2 by the time analysis module, analyzing the fine count values of the two channels, and taking the timestamp corresponding to the delay line with the relatively small fine count value as an output result.
Compared with the prior art, the invention has the remarkable advantages that: (1) the maximum oscillation period number or the fine count value can be reduced by half, the resolution is improved, and the RMS error is reduced; (2) the method has better integral nonlinearity and differential nonlinearity; (3) by using the Vernier measurement principle, the length of a delay line is shortened, and the consumption of required resources is reduced.
Drawings
FIG. 1 is a schematic diagram of a TDC circuit based on a two-way operation circular carry chain according to the present invention.
Fig. 2 is a schematic diagram of a single channel structure of the TDC circuit of the present invention.
FIG. 3 is a schematic diagram of a fine timing module in the TDC circuit of the present invention.
Fig. 4 is a schematic structural diagram of a dynamic delay variable ring oscillator RO in the fine timing module according to the present invention.
Fig. 5 is a schematic diagram of the working principle of the present invention using the bi-directional delay line.
Fig. 6 is a schematic diagram of a length-adjustable chain of cascaded inverters according to the present invention.
FIG. 7 is a graph of differential nonlinear DNL of a standard delay line channel in an embodiment of the present invention.
FIG. 8 is a graph of the integrated non-linearity INL of the standard delay line channel in an embodiment of the present invention.
FIG. 9 is a graph of differential nonlinear DNL of a non-standard delay line channel in an embodiment of the present invention.
FIG. 10 is a graph of the integral non-linearity INL of the non-standard delay line channel in an embodiment of the present invention.
Fig. 11 is a histogram of the measured time distribution with time delay not improved at 3444ps in the embodiment of the present invention.
Fig. 12 is a measured time distribution histogram after the time delay is improved at 3444ps in the embodiment of the present invention.
Fig. 13 is a histogram of the measured time distribution with time delays unmodified at 23371ps in an embodiment of the present invention.
Fig. 14 is a histogram of measured time distribution with time delay improved at 23371ps in an embodiment of the present invention.
Detailed Description
The TDC circuit based on the bidirectional running annular carry chain comprises a standard delay line channel, a non-standard delay line channel and a time analysis module, wherein the standard delay line channel and the non-standard delay line channel have the same structure and comprise a time extraction module, a coarse timing module, a fine timing module and a timestamp combination module; the time extraction module, the fine timing module, the timestamp combination module and the time analysis module are sequentially connected, and the coarse timing module is connected with the timestamp combination module;
the time extraction module is used for searching and searching a coarse clock signal which is nearest to the measured signal and appears behind the measured signal, and transmitting the measured signal and the coarse timing clock signal which respectively undergo different delays to the fine timing module;
the fine timing module is used for measuring the time interval between the measured signal and the coarse timing clock signal and generating a fine timing part in a time stamp result;
the coarse timing module is used for generating a coarse timing part in a timestamp result;
the timestamp combination module is used for outputting a complete timestamp result;
and the time analysis module is used for analyzing the time stamp results generated by the two delay line channels, and selecting the time stamp corresponding to the delay line with the relatively small fine count value as the final output result.
Furthermore, the standard delay line channel transmits a measured signal to a slow delay line, and transmits a coarse timing clock signal to a fast delay line; the nonstandard delay line channel transmits the detected signal to the fast delay line, and transmits the coarse timing clock signal to the slow delay line.
Furthermore, the fine timing module comprises a first delay line, a second delay line, a phase discriminator, a fine counter and first to fourth pulse shaping modules;
the input end of the first delay line is connected with a first pulse shaping module; the output end of the first delay line is connected with the data port of the phase discriminator, and is connected with the clock port of the fine counter and the 1-from-2 Mux through the second pulse shaping module, and the 1-from-2 Mux is connected with the input end of the first delay line through an OR gate so as to form a first oscillation ring-shaped carry chain;
the input end of the second delay line is connected with a third pulse shaping module; the output end of the second delay line is connected with the clock port of the phase discriminator and is connected with the input end of the second delay line through a fourth pulse shaping module, a 2-to-1 Mux or an OR gate to form a second oscillation annular carry chain;
the output port of the phase discriminator is connected with the enable port of the fine counter and is used for judging the relative time relationship between the leading signal and the lagging signal and controlling the enable port of the fine counter;
the fine counter is used for outputting a fine timing part in the timestamp result;
and the first pulse shaping module, the second pulse shaping module, the third pulse shaping module and the fourth pulse shaping module are used for controlling the high level duration of a propagation signal in an oscillation loop, so that the fine counting measurement range can cover the coarse counting clock period.
Further, the first delay line comprises n1A delay unit and a delay circuit having n1A first multiplexer of input ports, where n1According to the value of sel delivered by PC terminal1Determining a value; the output end of the ith delay unit is connected with the ith input end of the first multiplexer and is connected with the input end of the (i + 1) th delay unit, wherein i is more than or equal to 1 and is less than or equal to n1-1；
The second delay line comprises n2A delay unit and n2A second multiplexer of inputs, where n2According to the value of sel delivered by PC terminal2Determining a value; the output end of the jth delay unit is connected with the jth input end of the second multiplexer and is connected with the input end of the jth +1 delay unit, wherein j is more than or equal to 1 and is less than or equal to n2-1；
The N input multiplexers respectively correspond to the N delay units of the carry chain, the p output end of each delay unit is connected to the p input end of the multiplexer, and only one connection is effective according to the channel selection value of the SEL set by the PC end, so that the circuit has N different carry chain loops and is dynamically switched and controlled through a PC program; in two lengths each n1、n2In the carry chain of (2), possible combination elements (sel)1,sel2) Is n1×n2Corresponding to each (sel)1,sel2) And calculating the resolution ratio: t iscyc1-Tcyc2Wherein T iscyc1Indicating the period of oscillation, T, during which the first delay line constitutes the carry chaincyc2Representing the oscillation period of the second delay line carry chain; by enumerating sel from 1 to n independently1And sel2And recording the corresponding Tcyc1And Tcyc2The entire combined set can be covered and only n is needed1+n2Performing secondary operation; t is obtained by receiving the oscillation signal at the output terminal of the multiplexer and observing the signal with an external oscilloscopecyc1And Tcyc2Finally by selection (sel)1,sel2) The combination to achieve the target resolution of the TDC.
Furthermore, a cascade inverter longitudinal adjustable chain is respectively inserted between the time extraction module and the fine timing module of the standard delay line channel and the non-standard delay line channel, and is respectively used for tauupAnd τnullAdjusting by modifying the number of inverters to τupAnd τnullAre both positive and approach 0; wherein tau isupFor additional delay of the front-end signals of the signal under test and the clock signal, τnullAn extra delay for the signal under test and the back-end signal of the clock signal.
A TDC (time delay/position converter) measuring method based on a bidirectional running annular carry chain comprises the following steps:
and 3, receiving the results transmitted by the timestamp combination module in the steps 1 and 2 by the time analysis module, analyzing the fine count values of the two channels, and taking the timestamp corresponding to the delay line with the relatively small fine count value as an output result.
The invention is described in further detail below with reference to the figures and specific examples.
With reference to fig. 1 and fig. 2, the TDC circuit based on the bidirectional running circular carry chain of the present invention includes a standard delay line channel, a non-standard delay line channel, and a time analysis module, wherein the standard delay line channel and the non-standard delay line channel have the same structure, and include a time extraction module, a coarse timing module, a fine timing module, and a timestamp combination module; the time extraction module, the fine timing module, the timestamp combination module and the time analysis module are sequentially connected, and the coarse timing module is connected with the timestamp combination module;
the time extraction module is used for searching and searching a coarse clock signal which is present behind the measured signal and is closest to the measured signal, and transmitting the measured signal and the coarse timing clock signal which are respectively delayed to the fine timing module;
the fine timing module is used for measuring the time interval between the measured signal and the coarse timing clock signal and generating a fine timing part in a time stamp result; the fine timing module consists of a ring oscillator formed by two ring-shaped carry chains, and the ring-shaped carry chains are formed by connecting the last delay unit to the first delay unit. By distributing different numbers of delay units, the difference of the oscillation periods of the two ring oscillators is very small, and the oscillation period of the ring oscillator determines the resolution; the working principle of the fine timing module is based on a Vernier mode, in a standard delay line structure, an advanced measured signal is fed to a slow ring oscillator and a delay clock signal to a fast ring oscillator, a D-type trigger is used for identifying the time when a lagging signal exceeds the advanced signal, a counter is used for recording the oscillation number of the overtaking time, and finally, a high-resolution timestamp result is obtained according to the value of the counter;
the coarse timing module is used for generating a coarse timing part in a timestamp result and recording the number of clock cycles T by using a coarse counter;
the timestamp combination module is used for outputting a complete timestamp result;
and the time analysis module is used for analyzing the time stamp results generated by the two delay line channels, and selecting the time stamp corresponding to the delay line with the relatively small fine count value as the final output result.
Further, with reference to fig. 3, the fine timing module includes a first delay line, a second delay line, a phase discriminator, a fine counter, and first to fourth pulse shaping modules;
the input end of the first delay line is connected with a first pulse shaping module; the output end of the first delay line is connected with the data port of the phase discriminator, and is connected with the clock port of the fine counter and the 1-from-2 Mux through the second pulse shaping module, and the 1-from-2 Mux is connected with the input end of the first delay line through an OR gate so as to form a first oscillation ring-shaped carry chain;
the input end of the second delay line is connected with a third pulse shaping module; the output end of the second delay line is connected with the clock port of the phase discriminator and is connected with the input end of the second delay line through a fourth pulse shaping module, a 2-to-1 Mux or an OR gate to form a second oscillation annular carry chain;
the output port of the phase discriminator is connected with the enable port of the fine counter and is used for judging the relative time relationship between the leading signal and the lagging signal and controlling the enable port of the fine counter;
the fine counter is used for outputting a fine timing part in the timestamp result;
and the first pulse shaping module, the second pulse shaping module, the third pulse shaping module and the fourth pulse shaping module are used for controlling the high level duration of a propagation signal in an oscillation loop, so that the fine counting measurement range can cover the coarse counting clock period.
Further, in conjunction with fig. 4, the first delay line includes n1A delay unit and a delay circuit having n1A first multiplexer of input ports, where n1According to the value of sel delivered by PC terminal1Determining a value; the output end of the ith delay unit is connected with the ith input end of the first multiplexer and is connected with the input end of the (i + 1) th delay unit, wherein i is more than or equal to 1 and is less than or equal to n1-1；
The second delay line comprises n2A delay unit and n2A second multiplexer of inputs, where n2According to the value of sel delivered by PC terminal2Determining a value; the output end of the jth delay unit is connected with the jth input end of the second multiplexer and is connected with the input end of the jth +1 delay unit, wherein j is more than or equal to 1 and is less than or equal to n2-1；
The n input multiplexers respectively correspond to the n delay units of the carry chain, and the p-th output of each delay unit is connected to the p-th input end of each multiplexer; at the same time, only one connection is effective according to the channel selection value of SEL set by the PC end of the information analysis module, so that the circuit has N different carry chain loops and can be dynamically switched and controlled by a PC program; in two lengths each n1、n2In the carry chain of (2), possible combination elements (sel)1,sel2) Is n1×n2Corresponding to each (sel)1,sel2) The resolution can be calculated: t iscyc1-Tcyc2Wherein T iscyc1Indicating the period of oscillation, T, during which the first delay line constitutes the carry chaincyc2Representing the oscillation period of the second delay line carry chain; by enumerating sel from 1 to n independently1And sel2And recording the corresponding Tcyc1And Tcyc2The entire combined set can be covered and only n is needed1+n2Performing secondary operation; t is obtained by receiving the oscillation signal at the output terminal of the multiplexer and observing the signal with an external oscilloscopecyc1And Tcyc2And finally by selecting (sel)1,sel2) The combination to achieve the target resolution of the TDC.
Further, with reference to fig. 5, the timestamp result obtained by the timestamp combination module of the standard delay line channel is the time when the leading measured signal catches up with the lagging clock signal in the positive direction, the timestamp result obtained by the timestamp combination module of the non-standard delay line channel is the time when the lagging clock signal catches up with the leading measured signal in the negative direction, the timestamp results of the last two types of delay line channels are transmitted to the time analysis module, the fine count values of the two channels are analyzed, and the timestamp corresponding to the delay line with the relatively small fine count value is used as the final output result.
Further, with reference to fig. 6, a cascaded inverter vertical adjustable chain is inserted between the time extraction module and the fine timing module of the standard delay line channel and the non-standard delay line channel, respectively, for τupAnd τnullAdjusting by modifying the number of inverters to τupAnd τnullAre all positive and as close to 0 as possible; wherein tau isupFor additional delay of the front-end signals of the signal under test and the clock signal, τnullAn extra delay for the signal under test and the back-end signal of the clock signal.
A TDC (time-to-digital converter) conversion method based on a bidirectional running annular carry chain comprises the following steps:
and 3, receiving the results transmitted by the timestamp combination module in the steps 1 and 2 by the time analysis module, analyzing the fine count values of the two channels, and taking the timestamp corresponding to the delay line with the relatively small fine count value as a final output result.
Further, the reason why the TDC resolution can be improved by using the two-way operation circular carry chain is as follows:
where σ represents the root mean square error RMS, k is a circuit-dependent constant factor, mainly influenced by the overall noise of the circuit, TcycIs the oscillation period of a Ring Oscillator (ROs), n is the oscillation frequency, r is the resolution of the fine timing module, and Δ T is the fine time interval to be measured;
it can be seen from the formula that the root mean square error σ is proportional to the square root of the total number of oscillations n. The circuit enables an event to trigger two different types of delay line structures simultaneously, generates two fine timing value results with different numerical values, selects a timestamp corresponding to the delay line with a small fine counting value as a final output result, so that the oscillation frequency n can be reduced by a half, the root mean square error sigma is effectively reduced, and the TDC resolution is improved.
Examples
In this embodiment, the coarse timing counter is set to be 9 bits wide and operates at a clock rate of 600 Mhz; the fine timing counter is 7 bits wide, which can support higher resolution (1667/2 can be reached)713 ps); the measured signal is generated by a function generator (AFG 3251 of Tektronix Co., with a repetition frequency of 200.1 KHz; considering that the tested signal is asynchronous with the clock signal of the TDC, firstly, the resolution, DNL and INL performance are determined through a code density test; the experiment was carried out at a standard voltage of 1100mv and at an ambient temperature of 20 ℃.
As can be seen from fig. 7 and 8, DNL ranges from-0.17 LSB to 0.10LSB and INL ranges from-0.04 LSB to 0.19LSB according to the timestamp results measured by the standard delay line channel; referring to fig. 9 and 10, it can be seen that DNL is in the range of-0.20 LSB to 0.25LSB and INL is in the range of 0.03LSB to 0.82LSB for the timestamp results measured by the non-standard delay line channel, and therefore it can be seen that DNL and INL are relatively low for the fine timing results obtained by using the present invention.
The root mean square error is then evaluated using a fine timing interval check. As shown in the time distribution histograms shown in fig. 11 and 12, the final measurement result of the time delay at around 3444ps has an unmodified RMS error result of 38ps, and the result obtained by the bidirectional delay method is 27ps, so that the improvement effect is significant; as shown in the time distribution histograms shown in fig. 13 and fig. 14, the final measurement result of the time delay at about 23371ps has an unmodified RMS error result of 39ps, and the result obtained by the method is 28ps, so that the improvement effect is remarkable, and therefore, the method can improve the TDC resolution from 30-40 ps magnitude to 20-30 ps magnitude.
The TDC circuit and the measuring method based on the bidirectional running annular carry chain can effectively reduce the oscillation times in the process of fine timing measurement, thereby obviously reducing RMS errors and improving the resolution. According to experimental results, the method can reduce the maximum oscillation period number or the fine count value by half, so that the resolution is improved from 30-40 ps magnitude to 20-30 ps magnitude; the method has better integral nonlinearity and differential nonlinearity; by using the Vernier measurement principle, the length of a delay line is shortened, and the consumption of required resources is reduced.
Claims (4)
1. A TDC circuit based on a bidirectional running annular carry chain is characterized by comprising a standard delay line channel, a non-standard delay line channel and a time analysis module, wherein the standard delay line channel and the non-standard delay line channel have the same structure and comprise a time extraction module, a coarse timing module, a fine timing module and a timestamp combination module; the time extraction module, the fine timing module, the timestamp combination module and the time analysis module are sequentially connected, and the coarse timing module is connected with the timestamp combination module;
the time extraction module is used for searching and searching a coarse clock signal which is nearest to the measured signal and appears behind the measured signal, and transmitting the measured signal and the coarse timing clock signal which respectively undergo different delays to the fine timing module;
the fine timing module is used for measuring the time interval between the measured signal and the coarse timing clock signal and generating a fine timing part in a time stamp result;
the coarse timing module is used for generating a coarse timing part in a timestamp result;
the timestamp combination module is used for outputting a complete timestamp result;
the time analysis module is used for analyzing the time stamp results generated by the two delay line channels, and selecting the time stamp corresponding to the delay line with the relatively small fine count value as the final output result;
the fine timing module comprises a first delay line, a second delay line, a phase discriminator, a fine counter and first to fourth pulse shaping modules;
the input end of the first delay line is connected with a first pulse shaping module; the output end of the first delay line is connected with the data port of the phase discriminator, and is connected with the clock port of the fine counter and the 1-from-2 Mux through the second pulse shaping module, and the 1-from-2 Mux is connected with the input end of the first delay line through an OR gate so as to form a first oscillation ring-shaped carry chain;
the input end of the second delay line is connected with a third pulse shaping module; the output end of the second delay line is connected with the clock port of the phase discriminator and is connected with the input end of the second delay line through a fourth pulse shaping module, a 2-to-1 Mux or an OR gate to form a second oscillation annular carry chain;
the output port of the phase discriminator is connected with the enable port of the fine counter and is used for judging the relative time relationship between the leading signal and the lagging signal and controlling the enable port of the fine counter;
the fine counter is used for outputting a fine timing part in the timestamp result;
the first pulse shaping module, the second pulse shaping module, the third pulse shaping module, the fourth pulse shaping module and the fourth pulse shaping module are respectively used for controlling the high level duration time of a propagation signal in an oscillation loop, so that a fine counting measurement range can cover a coarse counting clock period;
the first delay line comprises n1A delay unit and a delay circuit having n1A first multiplexer of input ports, where n1According to the value of sel delivered by PC terminal1Determining a value; the output end of the ith delay unit is connected with the ith input end of the first multiplexer and is connected with the input end of the (i + 1) th delay unit, wherein i is more than or equal to 1 and is less than or equal to n1-1；
The second delay line comprises n2A delay unit and n2A second multiplexer of inputs, where n2According to the value of sel delivered by PC terminal2Determining a value; the output end of the jth delay unit and the second multiplexThe jth input end of the user device is connected with the jth input end of the (j + 1) th delay unit, wherein j is more than or equal to 1 and is less than or equal to n2-1；
The N input multiplexers respectively correspond to the N delay units of the carry chain, the p output end of each delay unit is connected to the p input end of the multiplexer, and only one connection is effective according to the channel selection value of the SEL set by the PC end, so that the circuit has N different carry chain loops and is dynamically switched and controlled through a PC program; in two lengths each n1、n2In the carry chain of (2), the combination element (sel)1,sel2) Is n1×n2Corresponding to each (sel)1,sel2) And calculating the resolution ratio: t iscyc1-Tcyc2Wherein T iscyc1Indicating the period of oscillation, T, during which the first delay line constitutes the carry chaincyc2Representing the oscillation period of the second delay line carry chain; by enumerating sel from 1 to n independently1And sel2And recording the corresponding Tcyc1And Tcyc2The entire combined set can be covered and only n is needed1+n2Performing secondary operation; t is obtained by receiving the oscillation signal at the output terminal of the multiplexer and observing the signal with an external oscilloscopecyc1And Tcyc2Finally by selection (sel)1,sel2) The combination to achieve the target resolution of the TDC.
2. The TDC circuit according to claim 1, wherein the standard delay line channel passes the signal under test to the slow delay line and the coarse timing clock signal to the fast delay line; the nonstandard delay line channel transmits the detected signal to the fast delay line, and transmits the coarse timing clock signal to the slow delay line.
3. The TDC circuit based on a bi-directional operation circular carry chain as claimed in claim 1, wherein a cascaded inverter longitudinally adjustable chain is inserted between the time extraction module and the fine timing module of the standard delay line channel and the non-standard delay line channel, respectively, and each chain is connected to the fine timing moduleFor tauupAnd τnullAdjusting by modifying the number of inverters to τupAnd τnullAre both positive and approach 0; wherein tau isupFor additional delay of the front-end signals of the signal under test and the clock signal, τnullAn extra delay for the signal under test and the back-end signal of the clock signal.
4. A TDC measurement method based on a bidirectional running annular carry chain, which is characterized in that the method is based on the TDC circuit of the bidirectional running annular carry chain as claimed in any one of claims 1 to 3, and comprises the following steps:
step 1, in a standard delay line channel, a measured signal is used as a leading signal and is propagated along a slow delay line through a time extraction module, a coarse timing clock signal is used as a lagging signal and is propagated along a fast delay line through the time extraction module, and a fine timing module calculates the time interval between the measured signal and the coarse timing clock signal and transmits the time interval to a timestamp combination module;
step 2, in a non-standard delay line channel, a measured signal is used as a leading signal and is propagated along a fast delay line through a time extraction module, a coarse timing clock signal is used as a lagging signal and is propagated along a slow delay line through the time extraction module, and a fine timing module calculates the time interval between the measured signal and the coarse timing clock signal and transmits the time interval to a timestamp combination module;
and 3, receiving the results transmitted by the timestamp combination module in the steps 1 and 2 by the time analysis module, analyzing the fine count values of the two channels, and taking the timestamp corresponding to the delay line with the relatively small fine count value as an output result.
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| CN113346879A (en) * | 2021-06-04 | 2021-09-03 | 南京理工大学 | Annular carry chain TDC circuit based on fine delay phase shift and measurement method thereof |
| CN113835333B (en) * | 2021-09-29 | 2022-08-12 | 武汉市聚芯微电子有限责任公司 | Time-to-digital conversion device and time-to-digital conversion method |
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