CN112650044B - High-precision time measuring device and method based on delay ring redundant state information - Google Patents
High-precision time measuring device and method based on delay ring redundant state information Download PDFInfo
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Abstract
The invention belongs to the field of high-precision time frequency measurement, and particularly discloses a high-precision time measuring device and method based on delay loop redundancy state information. The device comprises a delay loop interpolator, a delay loop logic gate state information latching module, a redundant state information time sequence storage module and a measurement data statistical analysis module. The delay loop interpolator is composed of logic gates with special carry chains, and realizes first-order interpolation subdivision. The delay loop logic gate state information latching module and the redundant state information time sequence storage module realize a redundant state information subdivision circuit, synchronously latch the output state information of the delay loop logic gate, perform second-order equivalent subdivision on the delay loop interpolator, and the measurement data statistical analysis module analyzes and calculates the measurement result. The invention utilizes the inherent inconsistent transmission delay characteristic of the FPGA logic gate to realize the second-order subdivision of the delay loop interpolator through the redundant state information subdivision circuit so as to improve the time measurement resolution and the measurement precision.
Description
Technical Field
The invention belongs to the field of high-precision time and frequency measurement, and particularly relates to a high-precision time measuring device and method based on delay loop redundant state information.
Background
Time measurement is an important measurement technology in modern metrology, the technology can accurately measure the time interval between two physical events, and the current high-precision time interval measurement equipment is widely applied to basic research and engineering application, such as the fields of quantum communication, time resolution spectral analysis, laser ranging, biomedical imaging and the like. The time-to-digital converter realized based on the FPGA is one of the most popular time interval measuring methods with high precision in the prior art, and has the characteristics of short realization period, low cost, strong adaptability and the like.
However, the resolution of time measurement in the conventional delay-loop subtraction method based on the FPGA is low, and meanwhile, in the conventional second-order time measurement method, the first-order measurement circuit and the second-order measurement circuit are sequentially executed, and the time measurement speed is reduced every time one measurement circuit is added. Meanwhile, each additional measuring circuit affects the time measuring speed and the dead time.
Based on the above defects, there is a need in the art to further improve and design the existing second-order delay loop time measurement device, construct a high-precision time measurement device and method, and solve the problems of the existing second-order delay loop time measurement device.
Disclosure of Invention
In view of the above drawbacks or needs for improvement in the prior art, the present invention provides a high-precision time measurement device and method based on delay loop redundant state information, in which the features of an FPGA delay loop and the technical features of time measurement thereof are combined, and the structures and specific setting modes of key components thereof, such as a delay loop interpolator, a delay loop logic gate state information latch module, a redundant state information time sequence storage module, and a measurement data statistical analysis module, are studied and designed accordingly, so that the problem of low time measurement resolution of delay loop subtraction method based on FPGA in the prior art can be solved, the measurement resolution and measurement precision of the delay loop subtraction method interpolator can be improved significantly, the measurement speed of the delay loop interpolator is not affected, and high-precision time measurement can be realized on a low-end FPGA platform.
To achieve the above object, according to one aspect of the present invention, there is provided a high-precision time measuring device based on redundant state information of a delay loop, comprising a delay loop interpolator, a delay loop logic gate state information latch module, a redundant state information time series storage module, and a measurement data statistical analysis module, wherein,
the time delay loop interpolator is used for measuring the interval of the measured time, and comprises a first time delay loop and a second time delay loop which are parallel and identical, wherein the first time delay loop and the second time delay loop are both composed of FPGA logic gate units, the first time delay loop is used for inputting a pulse signal of the measured time, and the second time delay loop is used for inputting a reference clock;
the delay ring logic gate state information latching module consists of a delay ring state information synchronous locking circuit which is synchronously driven by a reference clock and is used for synchronously latching redundant state information at corresponding delay units in the first delay ring and the second delay ring and coding the redundant state information to acquire a redundant state information time sequence;
the redundancy state information time sequence storage module comprises a measurement data coding circuit and a storage unit, wherein the measurement data coding circuit is used for carrying out natural binary coding and coding calibration on a redundancy state information time sequence according to the measurement data of the delay loop interpolator and the redundancy state information time sequence so as to obtain a characteristic time sequence and store the characteristic time sequence in the storage unit;
and the measurement data statistical analysis module calculates a time measurement result according to the measurement data and the characteristic time sequence of the delay loop interpolator, the resolution of the delay loop interpolator and the equivalent time width of the redundant state information subdivision code element.
Preferably, the FPGA logic gate in the FPGA logic gate unit is a logic gate with a carry chain, the delay unit in the FPGA logic gate unit is a multi-bit adder, and each bit adder has a set carry chain resource.
Preferably, the time measuring device further includes a high-precision clock for a high-precision reference clock, and the reference clock is used to trigger the delay loop state information synchronization locking circuit to latch the redundant state information at the corresponding delay units in the first delay loop and the second delay loop.
Preferably, the measurement data encoding circuit includes an address encoder, a natural binary encoder, and an encoding calibration unit, the address encoder performs bidirectional data interaction with the storage unit, the address encoder reads the measurement data and the redundant state information time series stored in the delay loop interpolator in the storage unit, performs hybrid encoding on the measurement data and the redundant state information time series of the delay loop interpolator, and determines a storage address, the natural binary encoder is configured to perform binary encoding on the redundant state information time series, and sends the redundant state information time series subjected to binary encoding to the encoding calibration unit for calibration, so as to generate a characteristic time series, and the encoding calibration unit stores the characteristic time series in the storage unit.
Preferably, the address encoder is a hybrid encoder, which obtains the high bits of the storage address according to the measurement data of the delay loop interpolator, and obtains the low bits of the storage address according to the natural binary coding of the redundant state information time sequence.
Preferably, the measurement data statistical analysis module analyzes a statistical rule between the measured time interval and the redundant state information time sequence according to the redundant state information time sequence by using the kernel controller, then generates a characteristic time sequence and a symbol equivalent time width corresponding to the characteristic time sequence according to the statistical rule, and finally realizes second-order equivalent time measurement according to the delay loop interpolator measurement resolution and the symbol equivalent time width.
Preferably, a Cortex-M3 kernel is used as a core controller of the measurement data statistical analysis module, and an APB (advanced peripheral bus) inside an FPGA (field programmable gate array) is used for realizing data interaction between the Cortex-M3 kernel and the delay ring interpolator, the delay ring logic gate state information latch module and the redundant state information time sequence storage module.
According to another aspect of the present invention, there is also provided a method for measuring a time interval using the above-mentioned high-precision time measuring device, comprising the steps of:
1) inputting measured time and a reference clock, measuring a measured time interval by a delay loop interpolator by adopting a cycle reduction method, and circularly transmitting a starting signal and an ending signal of the measured time interval in a first delay loop and a second delay loop respectively;
2) when the delay ring interpolator is used for measurement, the delay ring logic gate state information latching module synchronously latches the state information output by each logic gate by adopting a reference clock, and second-order equivalent subdivision of a measured time interval is realized according to a redundant state information time sequence in the state information and the measurement data of the delay ring interpolator;
3) when the measurement of the delay loop interpolator is finished, the redundant state information time sequence storage module carries out natural binary coding and coding calibration on the redundant state information time sequence so as to obtain a characteristic time sequence and a storage low-order address, and the characteristic time sequence and the storage low-order address are stored in the storage unit;
4) and the measurement data statistical analysis module calculates the measured time interval according to the measurement data and the characteristic time sequence of the delay loop interpolator, the resolution of the delay loop interpolator and the equivalent time width of the redundant state information subdivision code element.
Preferably, during the measurement time interval, the delay loop state information synchronous locking circuit of the delay loop logic gate state information latch module and the delay loop interpolator operate synchronously.
Preferably, the redundancy state information subdivision code element equivalent time width is obtained by a code statistical test method;
and the resolution of the delay ring interpolator is the integral delay difference value of the two delay rings of the first delay ring and the second delay ring.
Generally, compared with the prior art, the above technical solution conceived by the present invention mainly has the following technical advantages:
1. compared with other sequentially executed second-order measurement methods, the high-precision time measuring device provided by the invention has the advantages that the measurement time and the measurement dead time are not increased, the measurement resolution is high, the measurement precision is high, and the measurement speed is high.
2. Based on the inconsistent characteristic of the inherent transmission delay of the FPGA logic gate, the invention fully utilizes the latched output state information of the delay loop logic gate, subdivides the measurement resolution of the delay loop interpolator and improves the time measurement resolution and the measurement precision of the delay loop interpolator.
3. The redundant state information subdivision circuit consists of the logic gate of the delay loop and the latch, and occupies less logic gate resources by increasing the output state of the latch latching the logic gate of the delay loop, thereby being beneficial to the realization of a multi-channel time measurement circuit.
4. The invention adopts mixed address coding and natural binary coding of the measured data, thereby reducing the storage space of the measured data.
5. The invention can realize high-precision time measurement on a low-end FPGA platform, thereby reducing the realization cost of the invention.
Drawings
FIG. 1 is a schematic block diagram of a high-precision time measurement device based on redundant state information of a delay loop according to a preferred embodiment of the present invention;
FIG. 2 is a schematic block diagram of a redundant state information time-series storage module in a high-precision time measurement device based on the redundant state information of the delay loop according to a preferred embodiment of the present invention;
FIG. 3 is a schematic block diagram of a subdivision circuit based on redundant state information of a delay loop according to a preferred embodiment of the present invention;
fig. 4 is a schematic diagram of the time-series change of the redundant state of the sub-circuit according to the preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, a high-precision time measuring apparatus based on delay loop redundant state information according to an embodiment of the present invention includes a delay loop interpolator, a delay loop logic gate state information latch module, a redundant state information time sequence storage module, a measurement data statistical analysis module, and a high-precision clock.
The delay loop interpolator is realized by two delay loop loops formed by logic gates with special carry chains in the FPGA, and realizes first-order interpolation subdivision of the measured time interval. Specifically, the delay loop interpolator is realized by adopting a delay loop formed by logic gates with special carry chains in an FPGA (field programmable gate array), so that the difference of inherent transmission delay among the delay loop logic gates is reduced, and the second-order equivalent subdivision resolution is improved. The delay loop interpolator measures the measured time interval by adopting a cycle reduction method, a starting signal and an ending signal of the measured time interval are circularly transmitted in a delay loop formed by FPGA logic gates, and meanwhile, a delay loop logic gate state information latch module latches output state information of each logic gate of the delay loop. Wherein the cycle reduction method utilizes two identical delay loopsAnd continuously reducing the time interval of the two cyclic pulses through cyclic transmission until the time interval of the two cyclic pulses is smaller than the integral time delay difference of the two delay rings, namely the measurement resolution of the delay ring interpolator, wherein the measurement resolution is the resolution of the delay ring interpolator and is the integral time delay difference of the two delay rings of the first delay ring and the second delay ring. The design conditions of the two delay loops are completely the same, and the design reduces the influence of external factors such as external temperature and power supply voltage on the two delay loops. As shown in fig. 3, in the present invention, the delay loop interpolator includes a first delay loop and a second delay loop that are parallel and identical, where the first delay loop and the second delay loop are both composed of FPGA logic gate units, the first delay loop is used to input a pulse signal of a measured time, and the second delay loop is used to input a reference clock. Namely, a first delay loop and a second delay loop which are composed of logic gates of a special carry chain are arranged in the FPGA, a delay loop interpolator is realized, first-order subdivision of a measured time interval is realized, and the measurement resolution is equal to the difference of the whole time delay of the first delay loop and the second delay loop. At the same time, the reference clock of the second delay loop drives the latch to latch the output state information of the first delay loop, analyzing the output state information time sequence (D)1To DM) And the change rule between the measured time and the measured time, namely the change rule between the redundant state information time sequence and the measurement data of the delay loop interpolator, realizes the second-order subdivision of the measured time interval. The delay loop adopts a logic gate with a special carry link to realize the delay loop, the transmission delay consistency of the logic gate is better, the transmission delay difference of a single logic gate is smaller, high subdivision resolution can be realized, and the subdivision resolution can be generally tested by adopting code density statistics to obtain the equivalent time width of a code element.
In the invention, the number of the corresponding delay units is selected according to the measurement range of the designed high-precision time measuring device. And in the two delay rings, a latch is arranged at the corresponding delay unit.
The delay ring logic gate state information latch module is composed of a delay ring state information synchronous locking circuit, and a reference clock synchronously drives a latch circuit, namely a reference clock of a delay ring interpolator is adopted to drive a delay ring state information latch register, each logic gate of a delay ring is synchronously latched to output state information, and high-precision measurement of a measured time interval is realized according to a latch state information time sequence and delay ring interpolator measurement data. The state information latching module of the delay loop logic gate synchronously latches redundant state information of the delay loop by adopting a reference clock, and realizes second-order equivalent subdivision of a measured time interval according to a state information redundant state information time sequence and delay loop interpolator measurement data. When the delay ring interpolator is used for measurement, the delay ring logic gate state information latch module synchronously latches output state information of each logic gate of a delay ring, and utilizes the inconsistent characteristic of inherent transmission delay of the logic gates to realize second-order subdivision of the measurement resolution of the delay ring interpolator, so that second-order time measurement is realized, and the time measurement resolution and the measurement precision are improved. In the present invention, a synchronous latch circuit that latches delay loop redundant state information operates in synchronization with a delay loop interpolator. Compared with other second-order measurement methods, the method has the advantages that the measurement time and the measurement dead time are not increased, and the measurement speed is high.
As shown in fig. 2, the redundant state information time-series storage module includes a measurement data encoding circuit and a storage unit, which determines a storage address according to a mixed encoding of the delay ring interpolated measurement data and the redundant state information latch time series, and the redundant state information latch time series adopts a natural binary encoding to reduce a data storage space and store the redundant state information into the storage unit. And the redundant state information time sequence storage module generates a characteristic time sequence according to the latched delay ring redundant state time sequence when the measurement of the delay ring interpolator is finished, and stores the characteristic time sequence in the storage unit. The redundant state information time sequence storage module comprises an address encoder, a natural binary encoder, an encoding calibration module and a storage unit. The address encoder adopts a mixed coding mode, the high-order address is obtained according to the data measured by the delay loop interpolator, namely the high-order address of the storage address, and the low-order address is obtained according to the natural binary coding data of the redundant state information, namely the low-order address of the storage address. Firstly, when the time measurement is finished, obtaining a high-order address of a storage unit according to the data of the delay ring interpolator; then, natural binary coding is carried out according to the redundant state time sequence output by the delay loop logic gate state information latch module so as to reduce the storage space of the measured data, meanwhile, due to the inconsistency of logic gate transmission delay and wiring delay, the equivalent time widths of the redundant state time sequence code elements which are measured in a subdivision mode are inconsistent, and the phenomenon that a small code element equivalent time width or partial code element equivalent time width disappears occurs and needs to be calibrated; and finally, utilizing the code calibration module to calibrate and rearrange the natural binary codes of the redundant state information, generating a characteristic redundant state information time sequence, and storing the characteristic time sequence into a storage unit.
In the invention, the measurement data statistical analysis module analyzes the change rule between the measured time interval and the redundancy state according to the redundancy state information of the delay loop to obtain the time sequence of the characteristic redundancy state information and realize second-order equivalent subdivision. The measurement data statistical analysis module analyzes a statistical rule between a measured time interval and a redundancy state time sequence by using the FPGA kernel controller according to the latched time sequence of the redundancy state information of the delay ring, then generates a code element equivalent time width corresponding to the characteristic time sequence and the time sequence of the redundancy state information, and finally calculates a time measurement result according to the measurement resolution and the code element equivalent time width of the delay ring interpolator to realize second-order time interval measurement.
In the invention, a delay ring interpolator is connected with a delay ring logic gate state information latch module, a redundant state information time sequence storage module and a high-precision clock, the delay ring logic gate state information latch module is connected with the delay ring interpolator, the redundant state information time sequence storage module and the high-precision clock, the redundant state information time sequence storage module is connected with the delay ring interpolator, the delay ring logic gate state information latch module, a measurement data statistical analysis module and the high-precision clock, and the measurement data statistical analysis module is connected with the redundant state information time sequence storage module and the high-precision clock.
As shown in fig. 4, in the present invention, the delay-loop interpolator uses a round-robin reduction measurement, once interpolator measurement per round,the state information latch module of the delay ring logic gate latches the output state information of each logic gate of the delay ring once, and the time sequence (D) of the state of the redundant information is transmitted in each cycle1、D2、······、DM-1、DM) The variation is shown in fig. 4. The time interval between two cyclic pulses is reduced by one measurement resolution ratio once each cycle of measurement of the delay loop interpolator, however, transmission delay of logic gates in the FPGA is inconsistent, so that a state time sequence latched by a state information latch module of the delay loop logic gate changes in each cycle, and a redundant information subdivision model and a subdivision algorithm can be established according to a change relation between the position of the ring redundant state information time sequence in fig. 4 and input delay, so as to realize equivalent subdivision measurement.
Firstly, the time pulse trigger shown in figure 1 generates a start signal of cycle reduction measurement, the reference clock trigger generates an end signal, and the cycle reduction measurement is performed in the delay loop interpolator shown in figure 1; secondly, the time interval width between the start signal and the end signal is reduced once per cycle, the reduced resolution is the measurement resolution of the delay loop interpolator, and meanwhile, the latch shown in the figure 3 latches the output state of the delay loop logic gate under the driving of the reference clock in the process of each cycle; next, the redundant state information time series (D) output by the latch1、D2、······、DM-1、DM) Inputting the data to a redundant state information time sequence storage module shown in fig. 2, after the measurement is finished, obtaining a storage address high order according to the data measured by the delay loop interpolator, simultaneously performing natural binary coding on the redundant state information time sequence, and calibrating the natural binary coding to obtain a characteristic time sequence and a storage low order address; then storing the time sequence of the measurement data of the delay ring interpolator and the characteristic redundancy state information into a storage unit according to the storage address; finally, the measurement data statistical analysis module calculates the time measurement according to the time sequence coding of the measurement data and the characteristic redundant state information of the delay ring interpolator, the measurement resolution of the delay line interpolator and the equivalent time width of the subdivided code element of the redundant state informationQuantitative results.
In the process of coding the redundant state information time sequence, the equivalent time width of the subdivided code element needs to be known, and the equivalent time width can be obtained by adopting a code density statistical test method. In the code element statistical test, the principle shown in fig. 4 is adopted to analyze the redundant state information time sequence to obtain the equivalent time width of the redundant state information subdivision code element of the delay loop, the time-code element conversion relation curve corresponding to the high-precision time measuring device is obtained by combining the measurement result of the delay loop interpolator and the equivalent time width of the redundant state information subdivision code element, and the time measurement result can be calculated according to the conversion relation curve.
More specifically, the measurement method of the high-precision time measurement device based on the redundant state information of the delay loop of the present invention is as follows:
1) the delay loop interpolator measures the measured time interval by adopting a cycle reduction method, a starting signal and an ending signal of the measured time interval are circularly transmitted in a delay loop formed by FPGA logic gates, and meanwhile, a delay loop logic gate state information latch module latches output state information of each logic gate of the delay loop.
The cyclic reduction method utilizes two identical delay loops to continuously reduce the time interval of two cyclic pulses through cyclic transmission until the time interval of the two cyclic pulses is smaller than the integral delay difference of the two delay loops, namely the measurement resolution of a delay loop interpolator.
2) When the delay ring interpolator is used for measurement, the state information latching module of the delay ring logic gate synchronously latches the redundant state information of the delay ring by adopting a reference clock, and the second-order equivalent subdivision of the measured time interval is realized according to the state information redundant state information time sequence and the measurement data of the delay ring interpolator.
When the delay ring interpolator is used for measurement, the delay ring logic gate state information latch module synchronously latches output state information of each logic gate of a delay ring, and utilizes the inconsistent characteristic of the inherent delay of the logic gates to realize second-order subdivision of the measurement resolution of the delay ring interpolator, so that second-order time measurement is realized, and the time measurement resolution and the measurement precision are improved.
3) When the measurement of the delay ring interpolator is finished, the redundant state information time sequence storage module generates a characteristic time sequence according to the latched delay ring redundant state time sequence and stores the characteristic time sequence in the storage unit. The redundant state information latching time sequence adopts natural binary coding to reduce data storage space, and stores the redundant state information into the storage unit.
4) The redundant state information time sequence storage module analyzes the direct statistical rule of the redundant state information characteristic time sequence and the measured time interval, and measures the equivalent time width of the second-order subdivision code element by adopting code density statistics. The redundant state information time sequence storage module is composed of a coding circuit and a storage unit, a storage address is determined according to mixed coding of delay ring interpolation measurement data and a redundant state information latch time sequence, the redundant state information latch time sequence adopts natural binary coding to reduce data storage space, and the redundant state information is stored in the storage unit.
5) And the measured data statistical analysis module calculates the measured time interval according to the equivalent time width of the second-order subdivision code element, the measurement resolution of the delay loop interpolator and the measured data.
The measurement data statistical analysis module analyzes the statistical rule between the measured time interval and the redundant state information time sequence by using the kernel controller according to the delay ring redundant state information latching time sequence, then generates a characteristic redundant state information time sequence and a corresponding code element equivalent time width, and finally realizes second-order equivalent time measurement according to the delay ring interpolator measurement resolution and the code element equivalent time width.
The invention has been realized in the low-performance embedded Smartfusion FPGA platform, and can also be realized by adopting other FPGA platforms, a Cortex-M3 inner core in the Smartfusion FPGA is used as a core controller of a measurement data statistical analysis module to realize the code element analysis, statistics, storage and time calculation measurement results, and FPGA logic resources are used for realizing the delay loop interpolator and a redundant state information subdivision circuit, namely, the Cortex-M3 is used as the core controller of the measurement data statistical analysis module, and an APB bus in the FPGA is used for realizing the data interaction of the Cortex-M3 inner core, the delay loop interpolator, the delay loop logic gate state information latch module and the redundant state information time sequence storage module. The SRAM module is used for realizing a measurement data storage module, and an APB bus inside the FPGA is used for realizing data interaction between a Cortex-M3 kernel and a logic resource.
In the embodiment of the invention, the delay ring of the delay ring interpolator is realized by connecting a plurality of multi-bit adders in series, the adders have special carry chain resources, the delay difference between transmission delays of each bit of adder is small, and the second-order subdivision resolution realized by the redundant state information subdivision circuit is high. And adjusting the layout and the wiring of the delay loop adder by Smartfusion FPGA design software to adjust the measurement resolution of the delay loop interpolator. The frequency of the high-precision clock shown in fig. 1 is 100MHz, the clock period is 10ns, so the measurement range of the delay loop interpolator is slightly larger than 10ns, and the combination of the reference clock counter can cover the second-order time measurement range. The subdivision resolution of the subdivision circuit is determined by the difference of the transmission delays of the delay loop logic gates, the invention is realized by adopting the adder logic gates with special carry chains, the difference of the transmission delays of each adder logic gate is smaller, so the second-order subdivision resolution is high, and meanwhile, the measurement range is slightly larger than the measurement resolution of the delay loop interpolator, thereby ensuring that the delay loop interpolator can be effectively subdivided.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A high-precision time measuring device based on delay loop redundant state information is characterized by comprising a delay loop interpolator, a delay loop logic gate state information latching module, a redundant state information time sequence storage module and a measured data statistical analysis module, wherein,
the delay loop interpolator is connected with a delay loop logic gate state information latch module, a redundant state information time sequence storage module and a high-precision clock, the delay loop logic gate state information latch module is connected with the delay loop interpolator, the redundant state information time sequence storage module and the high-precision clock, the redundant state information time sequence storage module is connected with the delay loop interpolator, the delay loop logic gate state information latch module, a measurement data statistical analysis module and the high-precision clock, and the measurement data statistical analysis module is connected with the redundant state information time sequence storage module and the high-precision clock;
the time delay loop interpolator is used for measuring the interval of the measured time, and comprises a first time delay loop and a second time delay loop which are parallel and identical, wherein the first time delay loop and the second time delay loop are both composed of FPGA logic gate units, the first time delay loop is used for inputting a pulse signal of the measured time, and the second time delay loop is used for inputting a reference clock;
the delay ring logic gate state information latching module consists of a delay ring state information synchronous locking circuit which is synchronously driven by a reference clock and is used for synchronously latching redundant state information at corresponding delay units in the first delay ring and the second delay ring and coding the redundant state information to acquire a redundant state information time sequence;
the redundancy state information time sequence storage module comprises a measurement data coding circuit and a storage unit, wherein the measurement data coding circuit is used for carrying out natural binary coding and coding calibration on a redundancy state information time sequence according to the measurement data of the delay loop interpolator and the redundancy state information time sequence so as to obtain a characteristic time sequence and store the characteristic time sequence in the storage unit;
and the measurement data statistical analysis module calculates a time measurement result according to the measurement data and the characteristic time sequence of the delay loop interpolator, the resolution of the delay loop interpolator and the equivalent time width of the redundant state information subdivision code element.
2. The device according to claim 1, wherein the FPGA logic gate in the FPGA logic gate unit is a logic gate with a carry chain, the delay unit in the FPGA logic gate unit is a multi-bit adder, and each bit adder has a set carry chain resource.
3. The apparatus according to claim 1, wherein the apparatus further comprises a high-precision clock for high-precision reference clock, and the reference clock is used to trigger the delay loop state information synchronization locking circuit to latch the redundant state information at the corresponding delay cells in the first delay loop and the second delay loop.
4. A high-precision time measurement device based on the redundant state information of the delay loop according to claim 1, the measuring data coding circuit is characterized by comprising an address coder, a natural binary coder and a coding calibration unit, wherein the address coder is in bidirectional data interaction with the storage unit, the address encoder reads the measurement data and the redundant state information time series stored with the delay loop interpolator in the memory unit, and the time sequence of the measurement data and the redundant state information of the delay loop interpolator is mixed and coded to determine the storage address, the natural binary encoder is for binary encoding a redundant state information time sequence, and the time sequence of the redundant state information after binary coding is sent to a coding calibration unit for calibration, to generate a characteristic time series, the code calibration unit storing the characteristic time series in the storage unit.
5. The apparatus of claim 4, wherein the address encoder is a hybrid encoder, which obtains the high bits of the storage address according to the measurement data of the delay-loop interpolator and obtains the low bits of the storage address according to the natural binary coding of the time sequence of the redundant state information.
6. The device of claim 1, wherein the measurement data statistical analysis module analyzes a statistical rule between the measured time interval and the redundant state information time sequence according to the redundant state information time sequence by using the FPGA core controller, generates a feature time sequence and a symbol equivalent time width corresponding to the feature time sequence according to the statistical rule, and finally implements second-order equivalent time measurement according to the delay loop interpolator measurement resolution and the symbol equivalent time width.
7. The device for measuring time with high precision based on the redundant state information of the delay loop as claimed in claim 6, characterized in that a Cortex-M3 kernel is used as a core controller of the statistical analysis module of the measured data, and an APB bus inside the FPGA is used to realize the data interaction between the Cortex-M3 kernel and the delay loop interpolator, the latch module of the state information of the logic gate of the delay loop and the time sequence storage module of the redundant state information.
8. A method for measuring time intervals using a high accuracy time measuring device according to any of claims 1-7, comprising the steps of:
1) inputting measured time and a reference clock, measuring a measured time interval by a delay loop interpolator by adopting a cycle reduction method, and circularly transmitting a starting signal and an ending signal of the measured time interval in a first delay loop and a second delay loop respectively;
2) when the delay ring interpolator is used for measurement, the delay ring logic gate state information latching module synchronously latches the state information output by each logic gate by adopting a reference clock, and second-order equivalent subdivision of a measured time interval is realized according to a redundant state information time sequence in the state information and the measurement data of the delay ring interpolator;
3) when the measurement of the delay loop interpolator is finished, the redundant state information time sequence storage module carries out natural binary coding and coding calibration on the redundant state information time sequence so as to obtain a characteristic time sequence and a storage low-order address, and the characteristic time sequence and the storage low-order address are stored in the storage unit;
4) and the measurement data statistical analysis module calculates the measured time interval according to the measurement data and the characteristic time sequence of the delay loop interpolator, the resolution of the delay loop interpolator and the equivalent time width of the redundant state information subdivision code element.
9. The method of claim 8, wherein the delay loop state information synchronous locking circuit of the delay loop logic gate state information latch module operates synchronously with the delay loop interpolator during the measurement interval.
10. The method of claim 8, wherein the redundant state information subdivision symbol equivalent time width is obtained using a cryptographic statistical test method;
and the resolution of the delay ring interpolator is the integral delay difference value of the two delay rings of the first delay ring and the second delay ring.
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| US4908784A (en) * | 1987-08-04 | 1990-03-13 | Wave Technologies, Inc. | Method and apparatus for asynchronous time measurement |
| ATE208101T1 (en) * | 1996-04-02 | 2001-11-15 | Lecroy Corp | METHOD AND DEVICE FOR HIGHLY ACCURATE MEASURING TIME INTERVALS |
| CN100412729C (en) * | 2005-05-13 | 2008-08-20 | 清华大学 | Method and device for measuring time interval through delay line in cascaded two stages |
| CN101976037B (en) * | 2010-11-29 | 2012-01-25 | 北京一朴科技有限公司 | Method and device for measuring time intervals of repeated synchronous interpolation simulation |
| CN102253643B (en) * | 2011-06-23 | 2013-03-20 | 山东力创科技有限公司 | High-precision time measuring circuit and method |
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| CN103186097B (en) * | 2013-03-27 | 2015-06-17 | 西安电子科技大学 | High-definition time interval measuring device based on FPGA (Field Programmable Gate Array) |
| CN104111601B (en) * | 2014-07-30 | 2016-08-24 | 中国科学院测量与地球物理研究所 | A kind of time-to-digit converter based on time delay ring "flop-out" method and time interval measurement method thereof |
| CN106814595B (en) * | 2017-02-08 | 2022-03-18 | 中国科学院精密测量科学与技术创新研究院 | High-precision TDC based on equivalent subdivision and equivalent measurement method thereof |
| EP3647884B1 (en) * | 2017-06-30 | 2022-04-13 | SZ DJI Technology Co., Ltd. | Circuit, method and related chip for time measurement, system, and device |
| CN110658715B (en) * | 2018-06-29 | 2021-05-04 | 南京理工大学 | TDC circuit based on tap dynamic adjustable carry chain fine time interpolation delay line |
| CN110515292B (en) * | 2019-08-12 | 2021-04-27 | 南京理工大学 | TDC circuit based on bidirectional running annular carry chain and measuring method |
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