CN102346236A - Time parameter measurement system - Google Patents

Abstract

The invention discloses a time parameter measurement system for digital integrated circuits. The system is implemented by converting a to-be-measured signal IN into a time interval start signal Start and a stop signal Stop as well as pulse signals RStart and RStop by a channel circuit unit; then, the four signals are respectively provided for an accurate time measurement unit and a coarse time measurement unit to carry out measurement, wherein the accurate time measurement unit is composed of a multi-stage delay line and a calibration unit, and used for carrying out measurement under the condition that the rising edge of the to-be-measured signal is steep; and the coarse time measurement unit is composed of a jittering shielding circuit, a counter 1 and a counter 2 (the operating frequencies of the counter 1 and the counter 2 are complementary), and used for carrying out measurement under the condition that the rising edge of the to-be-measured signal is slow. By using the system disclosed by the invention, the difficulty of improving the resolution ratio of a time parameter measurement system for high-precision digital integrated circuits in the prior art is overcome, and the technical difficulty that the measurement bandwidth of a time parameter measurement system is limited caused by the jitter of output signals of a comparator for channel circuits.

Description

A Time Parameter Measuring System

technical field

The invention belongs to the technical field of electronic measurement, and more specifically relates to a digital integrated circuit time parameter measurement system.

Background technique

As the foundation and core of the information industry, the integrated circuit is a strategic industry for national economic and social development. It plays an important role in promoting economic development, social progress, improving people's living standards and ensuring national security. It has become the focus of current international competition. Focus and an important indicator to measure the degree of modernization and comprehensive national strength of a country or region.

High-precision time parameter measurement systems play a pivotal role in the design, verification and packaging of integrated circuits. It is a powerful means of testing and verifying the qualification of integrated circuits and time-related parameters.

FIG. 1 is a schematic diagram of an existing time parameter measurement system.

As shown in Figure 1, the time parameter measurement system includes three parts: the main control unit, the channel circuit unit and the measurement unit. Among them, the main control unit is responsible for sending out various control signals of the channel circuit unit and the measurement unit and reading back the measurement results. The signal IN to be tested is connected to the positive terminals of the comparators A1 and A2 in the channel circuit unit, and the negative terminals of the comparators A1 and A2 are connected to the level comparison signals VrefA and VrefB. The level of the signal IN to be measured is compared with the comparison levels VrefA and VrefB in the comparators A1 and A2 respectively, and the output signals RStart and RStop, the signals RStart and RStop are converted into measurement in the time interval signal generation circuit in the channel circuit unit The time interval start signal Start and stop signal Stop that the unit can recognize, and then sent to the measurement unit for XOR, as the enable signal of the counter is connected to the enable terminal EN of the counter, the counter counts, and outputs the output CNT representing the time interval [31:0]. Among them, CLK is the counting pulse signal of the counter, connected to the CP terminal of the counter, and the counter output CNT[31:0] is 32-bit binary data.

FIG. 2 is a measurement timing waveform diagram of the time parameter measurement system in FIG. 1 .

The channel circuit unit first converts the signal IN to be tested into signals RStart and RStop, and the time interval signal generating circuit converts the signals RStart and RStop into a time interval start signal Start and a stop signal Stop. Assuming that the value of the counter output CNT[31:0] is N, and the counting pulse of the counter, that is, the period of CLK is T, then the time interval T _x , that is, the time when the signal IN to be tested is between VrefA and VrefB is:

T _x = NT (1)

At this time, the time interval measurement resolution is the counting pulse period T of the counter.

If the test resolution is required to be 1 ns, the frequency of the clock CLK is required to be 1 GHz. The higher the resolution requirement, the higher the counting pulse frequency of the counter is required. If the resolution is increased to 125 ps, the CLK frequency is required to be 8 GHz, which is very difficult to implement in the prior art. Obviously, it is difficult to improve the resolution only by increasing the pulse frequency of the counter.

At the same time, when the rising edge of the signal IN to be tested is slow, the output of the comparators A1 and A2 in the channel circuit unit will jitter, resulting in the jitter phenomenon of the output pulse signals RStart and RStop, which will eventually make the measurement of the measurement unit difficult, and the time parameter measurement system Measurement bandwidth is limited.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art and provide a time parameter measurement system with high resolution and high measurement bandwidth.

In order to achieve the above object, the time parameter measurement system of the present invention includes:

a main control unit;

A channel circuit unit, which is used to compare the signal to be tested in the comparator in the channel circuit unit, and output two pulse signals RStart and RStop. At the same time, under the control of the main control unit, the pulse signals RStart and RStop The time interval signal generation circuit in the unit is converted into a time interval start signal Start and a stop signal Stop;

It is characterized in that it also includes:

A time precision measurement unit, which is used for measurement when the rising edge of the signal to be tested is relatively steep and there is no jitter in the output of the comparator. It is composed of a multi-stage delay line and an encoder;

Multiple delay lines are sequentially connected in series through interconnection lines to form a multi-stage delay line, and the delay line includes multiple delay units and multiple D flip-flops; the time interval start signal Start from the upper stage is connected to the first delay unit, if The delay line is the first stage, then it is connected to the time interval start signal Start output by the channel circuit unit, and then each delay unit is connected to a D flip-flop after delaying the time interval start signal Start sequentially, and the D terminal of each D flip-flop The time interval start signal Start after the delay unit delay is connected in turn, the clock pulse CP end of each D flip-flop is connected to the time interval stop signal Stop, and the reset terminal R is connected to the reset signal RESET sent by the main control unit;

The output of the Q terminal of the D flip-flop on each delay line is sent to the encoder. When the time interval stop signal Stop arrives, the output of the Q terminal of each D flip-flop is locked, and the start signal of the time interval Start within the representative time interval T _x is obtained. The encoder outputs N with the number of delay units, then the time interval T _x is:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; ROUND</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; \&Delta;\; L</span>}}<span\; class="notranslate">\; ,</span>$

Among them, ROUND represents the rounding operation, N ₂ represents the number of delay units of the single-stage passive delay line, and t _ΔL is the delay time of the interconnection line;

A time rough measurement unit, used for measurement when the rising edge of the signal to be tested is relatively slow, and the output pulse signals RStart and RStop of the comparator are jittered. It is composed of a jitter shielding circuit and a time interval measurement unit. The jitter shielding circuit includes a debounce circuit , waveform recovery circuit and time interval signal generation circuit;

The debounce circuit includes two debounce D flip-flops, two NOT gates, two programmable delay modules, a synchronous D flip-flop and a NAND gate;

The pulse signals RStart and RStop output by the comparator in the channel circuit unit are input to the clock pulse CP terminal of the respective de-jittering D flip-flops, and the output of the two de-jittering D flip-flops outputs Q-terminal delays Δt _L1 , Δt through their respective programmable delay modules After _L2 , after passing through a NOT gate, they are input to their respective reset R terminals, and the data D terminals of the two debounce D flip-flops are connected to the Q terminal output of the synchronous D flip-flop. The delay time of the programmable delay module Δt _L1 , Δt _L2 should be greater than the edge jitter time Δt _start and Δt _stop of the respective pulse signals RStart and RStop; the pulse signals RStart and RStop are connected to the synchronous D flip-flop clock pulse CP terminal after passing through the non-AND gate, and the reset R terminal of the synchronous D flip-flop The synchronous reset signal TRI is connected, and the data D terminal is connected to a high level; the respective debounce D flip-flops of the pulse signals RStart and RStop output debounced signal Q _start and signal Q _stop ;

The waveform recovery circuit includes two JK flip-flops, the J and K terminals of the two JK flip-flops are connected to high level, the reset R terminal is connected to the synchronous reset signal TRI from the main control unit, and the clock pulse CP terminal of the two JK flip-flops Connect with two debounce D flip-flop output Q terminals respectively, and output the recovery signal JStart and signal JStop of the debounced signal Q _start and signal Q _stop ;

The time interval signal generation circuit includes two D flip-flops. The D terminal of one D flip-flop is connected to high level Vcc, the clock pulse CP is connected to signal JStart, and the Q terminal outputs the time interval start signal JJStart; the D terminal of the other D flip-flop The signal JStart is connected, the clock pulse terminal CP is connected to the signal JStop, and the Q terminal outputs the time interval stop signal JJStop; the reset terminals R of the two D flip-flops are connected to the system reset signal RESET;

The time interval measurement unit is used to measure the time interval T _x of the time interval start signal JJStart and stop signal JJStop whose rising edges are one after the other.

The purpose of the invention of the present invention is achieved like this:

The signal to be tested is compared in the comparator in the channel circuit unit, and two pulse signals RStart and RStop are output. At the same time, under the control of the main control unit, the time interval signal generation circuit of the pulse signal RStart and RStop in the channel circuit unit In the middle, it is converted into a time interval start signal Start and a stop signal Stop. Since the time precision measurement unit adopting a multi-level delay line structure has a high measurement resolution, it overcomes the difficulty in generating high-frequency counting pulse signals in the prior art. The defect that the resolution time parameter measurement system is not easy to realize. At the same time, a time rough measurement unit with a jitter shielding circuit is adopted, which overcomes the defects of the prior art that the comparator output jitters caused by the slow rising edge of the signal to be tested and the measurement bandwidth of the time parameter measurement system is limited.

Description of drawings

FIG. 1 is a schematic diagram of a prior art time parameter measurement system.

Fig. 2 is a working sequence diagram of the time parameter measuring system in Fig. 1 .

Fig. 3 is a schematic diagram of a specific embodiment of the channel circuit unit in the present invention;

Fig. 4 is a structural diagram of a specific embodiment of the precise time measurement unit in the present invention;

Fig. 5 is a working sequence diagram of the time precision measurement unit;

Fig. 6 is a schematic diagram of a specific embodiment of the rough time measurement unit in the present invention;

Fig. 7 is a schematic diagram of the embodiment of the jitter shielding circuit shown in Fig. 6;

Fig. 8 is a working timing diagram of the jitter shielding circuit shown in Fig. 7;

Fig. 9 is a functional block diagram of a specific embodiment of the time parameter measurement system of the present invention.

Detailed ways

Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

Example

1. Channel circuit unit

Fig. 3 is a schematic diagram of a specific embodiment of the channel circuit unit in the present invention.

The channel circuit unit is the front end of the time parameter measurement system. In this embodiment, the channel circuit unit includes: an input interface circuit, a high-speed comparator, a data selector and a time interval generation circuit. Its function is to correctly and effectively introduce the signal to be measured into the time parameter measurement system, and convert the signal to be measured into pulse signals RStart, RStop, and time interval start signals Start and stop signals that can be recognized by the time rough measurement unit and the time fine measurement unit Stop.

As shown in Figure 3, in this implementation, the signal IN to be tested is connected to the input interface circuit. In the input interface circuit, the resistors R1 and R2 connected in series to the ground divide the voltage of the signal IN to be tested, and the relay RELAY1 selects the signal IN to be tested. Directly or select the divided voltage signal into the high-speed comparator. Then connect this signal to the positive terminals + of the comparators A1 and A2, and connect the negative terminals - of the comparators A1 and A2 to the comparison levels VrefA and VrefB respectively.

The data selector selects the positive output or the reverse output of the comparators A1 and A2 through the control signals SelStr and SelStop, and the selected signals RStart and RStop are sent to the time interval signal generation circuit to generate the time interval start signal Start and stop signal Stop.

The time interval signal generation circuit includes two D flip-flops D1 and D2. The data D terminal of D1 is connected to high level Vcc, the clock pulse CP is connected to the pulse signal RStart, and the Q terminal outputs the time interval start signal Start; the data D terminal of D2 is connected to On the Q terminal of D1, the clock pulse CP is connected to the pulse signal RStop, and the Q terminal outputs the time interval stop signal Stop. The reset terminals R of D1 and D2 are both connected to the reset signal RESET from the main control unit.

The channel circuit unit works like this:

Taking the measurement of the rise time of the signal IN to be tested as an example, the relay RELAY1 first selects the voltage measurement range of the signal IN to be tested. Then set the comparison level VrefA to be 10% of the divided voltage amplitude of the signal IN to be tested, and set the comparison level VrefB to be 90% of the amplitude of the signal IN to be tested. At the same time, the main control unit starts to control the signal SelStr and stops the control signal SelStop, so that the data selector selects the positive output of the comparators A1 and A2. Finally, the main control unit sends out a reset signal RESET. At this time, after D flip-flop D1 appears the time interval start signal Start with the rising edge before it, and after the time interval start signal Start becomes high level, D flip-flop D2 appears the time interval stop signal Stop after the rising edge, and the data The selector outputs pulse signals RStart and RStop. When the rising edge of the signal IN to be tested is slow, there will be jitter in the output of the comparators A1 and A2 in the channel circuit unit, resulting in jitter in the output pulse signals RStart and RStop.

2. Time precision measurement unit

Fig. 4 is a specific implementation of the precise time measuring unit in the present invention. Figure 5 is the corresponding working sequence diagram.

In this embodiment, as shown in FIG. 4 , the precise time measurement unit is composed of a multi-stage delay line and a calibration unit. The multi-stage delay line is composed of 7 delay lines with the same structure and 6 interconnection lines, and the delay line is composed of delay units L ₁ -L ₆₈ and D flip-flops DFFE1-DFFE68. The calibration unit is composed of 2 delay lines with the same structure and 1 interconnection line.

In the delay line structure, the delay units L ₁ -L ₆₈ are sequentially connected in series, and the time interval signal Start from the upper stage is connected to the first delay unit. If the delay line is the first stage, then it is connected to the time output by the channel circuit unit The interval start signal Start, is then sequentially transmitted on the multi-stage delay line. The output of each delay line is connected to the data end of D flip-flop DFFE1D-FFE68 in turn. The time interval stop signal Stop is connected to the clock terminals of all D flip-flops. The reset terminal R of all D flip-flops is connected to the reset signal RESET, so that the output state of the delay unit can be latched by the D flip-flop, that is, A_Q1...A_Q68, B_Q1...B_Q68,..., G_Q1...G_Q68. Then send the output to the decimal encoder to obtain the total number of delay units transmitted between the time interval start signal Start and the stop signal Stop. The output result of the encoder is N, and the delay time of a single delay unit is t, that is, the time interval T _x is obtained:

T _x =N*t (2)

With the birth of large-scale programmable logic devices CPLD and FPGA, it provides a good physical design platform for the measurement circuit shown in Figure 4. To build a delay line in FPGA needs to meet the following two conditions: first, the delay time t of the delay unit is required to be very small and very stable; second, there must be such a special structure inside the FPGA to facilitate the construction of the delay line. In this embodiment, Altera's ACEX1K50 series FPGA is selected to realize the multi-stage delay line and calibration unit shown in FIG. 4 .

Under normal circumstances, the length of the internal delay line of the FPGA is limited. According to the device manual, the maximum is 72 stages, and the delay time t of a single-stage delay unit is about 125ps. It can be seen that the maximum measurement time interval is 125ps*72=9ns. In the present invention, the dynamic measurement range of the time interval can be expanded by cascading a plurality of such single delay lines by using interconnection lines in the FPGA.

In this embodiment, as shown in FIG. 4 . The output of the single delay line of the upper stage is connected to the input of the single delay line of the next stage through the interconnection line, and they are cascaded in turn to form a multi-stage delay line structure composed of 7 single delay lines and 6 interconnection lines.

Figure 5 is the working sequence of the multi-stage delay line, D ₁ -D ₄₇₆ is the output of each delay unit of the delay line, the transmission state of the delay unit on the delay line is latched by the time interval stop signal Stop signal, and then the transmission state The output is encoded by a decimal encoder. The output result of the encoder is N, the delay time of the delay unit is t, and the delay time of the interconnection line is t _ΔL , then the time interval T _x is:

T _x ＝N*t+N ₁ *t _ΔL (3)

and _N1 is:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="N"\; filenames="HDA0000069763570000011.png,HDA0000069763570000031.png"\; state="\{\{state\}\}">N</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; ROUND</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Among them, ROUND represents a rounding operation, and N ₂ represents the number of delay units of a single delay line. Bring formula (4) into formula (3), then T _x is:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; ROUND</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; \&Delta;L</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

In this embodiment, the time precision measurement unit: N ₂ =68, N ₁ =6, t=125ps, measurement range: 0ns-50ns, measurement resolution 125ps.

At the same time, due to differences in FPGA power consumption, operating temperature, and resources used, the delay time t of the delay units in the multi-stage delay line and the delay time _tΔL of the interconnection lines will vary. Therefore, in this embodiment, a calibration unit is provided for the multi-stage delay line to measure the magnitudes of t and _tΔL in real time, and to calibrate the measurement performance of the time precision measurement unit.

The schematic diagram of the delay line calibration unit is shown in Figure 4.

In this embodiment, the calibration unit is composed of 2 delay lines, 1 interconnection line and encoder 2 .

The working principle of the calibration unit is as follows: it is assumed that the delay time of a single delay line is approximately t _L . First, two time interval signals SStart and SStop are generated by a standard instrument, and the time interval at this time is T _x1 , and T _x1 <t _L . The time interval start signal SStart is input from the delay line 1, and the time interval stop signal SStop latches the output states of the delay units in the delay line 1 and delay line 2, and then the output result N _cal-1 is obtained through the decimal encoder. Similarly, two time interval signals SStart and SSstop are generated by the standard instrument again, the time interval at this time is T _x2 , and t _L <T _x2 <2*t _L , and the output result N _cal-2 is obtained similarly.

It can be seen from the formula (3):

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; cal</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; t</span>}\\ {\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; cal</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; \&Delta;L</span>}}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Then t and t _ΔL :

$\left\{\begin{array}{c}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; cal</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}\\ {\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; \&Delta;L</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; cal</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; cal</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

At this time, t and t _ΔL in the system working environment can be measured through formula (7), and t and t _ΔL are substituted into formula (5), achieving the purpose of calibrating the time precision measurement unit.

3. Rough time measurement unit

In this embodiment, as shown in FIG. 3 , the pulse signals RStart and RStop are obtained from the outputs of the comparators A1 and A2 through the data selector. When the rising edge of the signal to be tested is relatively steep and the output pulse signals RStart and RStop of the comparators A1 and A2 have no jitter, the pulse signals RStart and RStop can be directly used to trigger D flip-flops D1 and D2 to generate the time interval start signal Start and stop signal Stop . When the rising edge of the signal to be tested is relatively slow and the output pulse signals RStart and RStop of the comparators A1 and A2 jitter, if the reset signal RESET resets the D flip-flops D1 and D2, the pulse signal RStart is at a high level or the falling edge jitters During the period, the falling edge jitter will cause the D flip-flop D1 to flip from low level to high level, which will mistakenly judge the falling edge as a rising edge, resulting in an error in the measurement of time parameters. At this time, the pulse signals RStart and RStop cannot be directly used to trigger the D flip-flop to generate the time interval start signal Start Start and stop signal Stop.

Wherein, the coarse time measurement unit is also implemented in the FPGA of the fine time measurement unit.

Fig. 6 is a schematic diagram of a specific implementation of the rough time measurement unit.

和CLK，使能端EN接异或门输出，且

和CLK相位相差180°，频率均为125MHz，则测量分辨力为4ns。在计数器时钟频率不变的情况下，分辨力提高了一倍。As shown in Figure 6, the time rough measurement unit includes a jitter shielding circuit and a time interval measurement unit. In this embodiment, in order to improve the resolution, the counting time interval measurement unit includes two counters, namely counters 1 and 2 and a different OR gate. Among them, the clock terminals CP of counters 1 and 2 are respectively connected to the clock signal

and CLK, the enable terminal EN is connected to the XOR gate output, and

The phase difference with CLK is 180°, and the frequency is 125MHz, so the measurement resolution is 4ns. Under the condition that the clock frequency of the counter remains unchanged, the resolution is doubled.

The coarse time measurement unit works like this:

As shown in Fig. 7 and Fig. 8, firstly, given a low level of the synchronous reset signal TRI, the output of the synchronous D flip-flop 5 is low, at this time, the outputs Qstart and Qstop of the two debounce D flip-flops 3 and 4, The outputs JStart and JStop of the two JK flip-flops 1 and 2 are low; when the given synchronous reset signal is high, the synchronous D flip-flop 5 and the two JK flip-flops 1 and 2 are enabled. If the pulses RStart and RStop output by the data selector in the channel circuit unit are at low level at the same time, the synchronous D flip-flop 5 is triggered and outputs high level, enabling the two debounce D flip-flops 3 and 4 .

The synchronous D flip-flop 5 and the synchronous reset signal TRI make the two debounce D flip-flops D active at low level at the same time when the pulse signals RStart and RStop start to work, so that the output JStart and JStop of the two JK flip-flops are low at the same time , to keep its state consistent, thus ensuring that the timing of the entire jitter shielding circuit is synchronous and consistent.

The pulse signals RStart and RStop are restored to signals JStart and JStop without jitter after passing through the jitter shielding circuit. Then, in the time interval signal generating circuit, the time interval start signal JJStart and the stop signal JJStop are generated through the reset signal RESET. Signals JJStart and JJStop output CNTEN signal after exclusive OR in the exclusive OR gate, and count in counters 1 and 2 to measure the time interval T _x . Assuming that the measurement results of counter 1 and counter 2 are CNT1 and CNT2 respectively, the time interval Tx is:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="CNT"\; filenames="HDA0000069763570000011.png,HDA0000069763570000031.png"\; state="\{\{state\}\}">CNT</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; CNT</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Among them, T is the counting pulse CLK period of the counter.

Fig. 7 is a schematic diagram of a specific embodiment of the jitter shielding circuit.

As shown in Figure 7, the jitter shielding circuit includes a de-jitter circuit, a waveform recovery circuit and a time interval signal generation circuit.

As shown in FIG. 7 , the debounce circuit includes a synchronous D flip-flop (D flip-flop 5 ), two debounce D flip-flops ( D flip-flops 3 , 4 ), two NOT gates and two programmable delay modules. The pulse signals RStart and RStop are connected to the CP terminal of the synchronous D flip-flop after passing through the non-AND gate, the reset R terminal is connected to the synchronous reset signal TRI, and the data D terminal is connected to high level; at the same time, the pulse signals RStart and RStop input their respective debounce D triggers The clock CP terminals of devices 3 and 4, the output Q terminals are delayed by Δt _L1 and Δt _L2 through their respective programmable delay modules, and then input to the reset R terminals of debounce D flip-flops 3 and 4 after passing through a NOT gate respectively. The data D terminals of the two debounce D flip-flops 3 and 4 are connected to the Q terminal output of the synchronous D flip-flop, and the outputs of the debounce D flip-flops 3 and 4 are represented by Q _Start and Q _Stop respectively, and the delay of the programmable delay module The times Δt _L1 , Δt _L2 should be greater than the edge jitter times Δt _start , Δt _stop of the respective pulse signals RStart and RStop respectively.

As shown in Figure 7, the waveform recovery circuit includes two JK flip-flops, namely JK flip-flops 1 and 2, the J and K terminals of the two JK flip-flops are connected to high-level Vcc, and the reset R terminal is connected to the synchronous reset signal TRI. The clock pulse CP terminals of the two JK flip-flops are respectively connected to the output Q terminals of the two dejittering D flip-flops 3 and 4 . The outputs of the two JK flip-flops are represented by JStart and JStop respectively.

As shown in Figure 7, the time interval signal generation circuit is the same as the time interval signal generation circuit in the channel circuit unit of Figure 3, including two D flip-flops 6, 7, the data D terminal of the D flip-flop 6 is connected to a high level Vcc, The clock pulse CP is connected to the signal JStart, and the Q terminal outputs the time interval start signal JJStart; the D terminal of the D flip-flop 7 is connected to the Q terminal of the D flip-flop 6, the clock pulse terminal CP is connected to the signal JStop, and the Q terminal outputs the time interval stop signal JJStop. The reset terminals R of the D flip-flops 1 and 2 are both connected to the reset signal RESET.

FIG. 8 is a working timing diagram of the jitter shielding circuit shown in FIG. 7 .

The jitter shield circuit works like this:

The principle of eliminating the jitter of the pulse signal RStart and RStop is similar. Taking the pulse signal RStart as an example, as shown in Figure 8, the jitter time of the pulse signal RStart is Δt _start . When the pulse signal RStart arrives, the data D of the debounce D flip-flop 3 The terminal is the high level output by the synchronous D flip-flop 5 after timing synchronization. When the clock pulse CP terminal of the debounce D flip-flop 3 receives the rising edge of the pulse RStart, the output terminal Q of the debounce D flip-flop 3 outputs the signal Q _start as a high level, and the signal Q _start passes through the programmable delay module 1 The output is delayed for a period of time Δt _L1 , the delay Δt _L1 is the value set by the main control unit in advance, and the delay time Δt _L1 is greater than the edge jitter time Δt _start of the pulse RStart. The pulse Q _start resets the debounce D flip-flop 3 after passing through the negation of the NOT gate. At this time, the debounce D flip-flop 3 outputs the pulse Q _start equal to the low level, until the rising edge of the pulse RStart signal arrives, the debounce is triggered again D flip-flop 3, the output pulse Q _start of the debounced D flip-flop 3 becomes high level again, and then the pulse Q _start is delayed by the programmable delay module 1 for a period of time Δt _L1 before being output. Then, the debounce D flip-flop 3 is reset after being inverted by the NOT gate. At this time, the debounce D flip-flop 3 outputs a pulse Q _start equal to low level again, so the pulse RStart is converted into a pulse Q _start . And the high level width of the pulse Q _start is equal to Δt _L1 .

Since the pulse Q _start is connected to the clock terminal CP of the JK flip-flop 1, and the data terminals J and K of the JK flip-flop 1 are both connected to a fixed high level. It can be known from the working principle of the JK flip-flop that when there is a rising edge, the output of the JK flip-flop flips from state 0 to state 1, or from state 1 to state 0. In this way, the JK flip-flop converts the signal Q _start into the signal JStart. And it can be known that the JStart signal is the restored signal after the jitter is removed from the RStart signal.

Fig. 9 is a functional block diagram of a specific embodiment of the time parameter measurement system.

As shown in FIG. 9 , in this embodiment, the time parameter measurement system of the present invention includes a main control unit, a channel circuit unit, a precise time measurement unit and a rough time measurement unit.

The main control unit issues a control command, and the channel circuit unit converts the signal to be tested into the time interval start signal Start and stop signal Stop, and the pulse signals RStart and RStop after the pulse generated by the comparator passes through the data selector.

In the measurement range of 0ns-50ns, the time precision measurement unit is used for measurement, and the time interval between the time interval start signal Start and the stop signal Stop is measured. Finally, the measurement results are transmitted from the SPI interface to the main control unit.

When the measurement range is 50ns-1ms, the time rough measurement unit is used for measurement. Pass the pulses RStart and RStop output by the comparator through the data selector through the jitter shielding circuit to remove the signal jitter, and then send them to the counter for measurement. Finally, the measurement results are transmitted from the SPI interface to the main control unit.

The control signal from the main control unit generates various control signals in the control logic circuit, including the synchronous reset signal TRI, the reset signal RESET, and the control signals of the channel circuit unit, the time fine measurement unit and the time rough measurement unit, etc.

In this embodiment, the digital integrated circuit time parameter measurement system of the present invention provides a time fine measurement unit and a time rough measurement unit for measurement. It not only solves the difficulty of improving the resolution of the time parameter measurement, but also solves the defects of the output signal jitter of the comparator and the limitation of the measurement bandwidth of the time parameter measurement system. The test results prove that the test resolution, repeatability and stability of the system meet the requirements of various indicators of the digital integrated circuit time parameter test system, and the achieved measurement indicators are:

1. Time precision measurement unit: the dynamic measurement range is 0ns-50ns, the resolution is 125ps, and the test accuracy is 500ps±1%.

2. Time rough measurement unit: dynamic measurement range 50ns-1ms, resolution 4ns, test accuracy 4ns±0.1%.

At the same time, the time parameter measurement system of the present invention also has important application value and development significance in various fields such as theoretical research, test science and engineering, medical technology and science, communication and navigation, and modulation domain analyzer.

Although the illustrative specific embodiments of the present invention have been described above, so that those skilled in the art can understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, As long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are included in the protection list.

Claims (3)

1. time parameter measuring system comprises:

One main control unit;

One channel circuit unit; Be used for measured signal is compared in the comparer of channel circuit unit; Output two pulse signals RStart and RStop; Simultaneously, under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in the circuit and converts time interval commencing signal Start and stop signal Stop into;

It is characterized in that also comprising:

One time accurate measurement unit, it is more precipitous to be used for the measured signal rising edge, and comparer is exported the measurement under the situation that does not have shake, is made up of multilevel delay line and scrambler;

Successively with many lag line formation multilevel delay connected in series lines, lag line comprises a plurality of delay cells and a plurality of d type flip flop through interconnection line; Time interval commencing signal Start from upper level connects first delay cell; If lag line is the first order; Then connect the time interval commencing signal Start of circuit unit output; After each delay cell postpones time interval commencing signal Start successively then, all be connected to a d type flip flop, the D end of each d type flip flop meets the time interval commencing signal Start after the delay units delay successively; The time clock CP end of each d type flip flop all meets time interval stop signal Stop, and its reset terminal R meets the reset signal RESET that main control unit sends;

The Q end output of the d type flip flop on each lag line is sent in the scrambler, and when time interval stop signal Stop arrived, the Q of each d type flip flop end output locking obtained representing time interval T _xScrambler output N, the then time interval T of the delay cell number of interior time interval commencing signal Start process _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}},$

Wherein, ROUND representes rounding operation, N ₂The delay cell number of expression single-stage passive delay, t _{Δ L}Be the time delay of interconnection line;

One time bigness scale unit; It is slower to be used for the measured signal rising edge; There are the measurement under the situation of shaking in comparer output pulse signal RStart and RStop; Be made up of dither mask circuit and time interval measurement unit, the dither mask circuit comprises that debouncing circuit, waveform restoring circuit and time interval signal produce circuit;

Debouncing circuit comprises that two are removed to shake d type flip flop, two not gates, two programmable delay modules, a synchronous d type flip flop and a NAND gate;

Pulse signal RStart that comparer is exported in the channel circuit unit and RStop import the time clock CP end that removes to shake d type flip flop separately, and programmable delay module delay Δ t is separately passed through in two outputs of going to shake d type flip flop output Q end _L1Δ t _L2After, behind the door non-through one respectively, be input to the R end that resets separately, two are gone the data D that shakes d type flip flop to hold the Q end output that all connects synchronous d type flip flop, Δ t time delay of programmable delay module _L1, Δ t _L2Should be respectively greater than the edge shake time Δ t of pulse signal RStart and RStop separately _Start,Δ t _StopPulse signal RStart and RStop be through receiving synchronous d type flip flop time clock CP end behind the NAND gate, the R termination that resets of d type flip flop is from the synchronous reset signal TRI of main control unit, data D termination high level synchronously; Pulse signal RStart and RStop going separately shaken the signal Q after d type flip flop output goes to shake _StartWith signal Q _Stop

The waveform restoring circuit comprises two JK flip-flops; The J of two JK flip-flops, K end all connect high level; The R termination that resets synchronous reset signal TRI, the time clock CP of two JK flip-flops end remove to shake d type flip flop output Q end and are connected with two respectively, export the signal Q after going to shake _StartWith signal Q _StopRestoring signal JStart and signal JStop;

Time interval signal produces circuit and comprises two d type flip flops, the D termination high level Vcc of a d type flip flop, and time clock CP termination signal JStart, Q end output time is commencing signal JJStart at interval; The D termination signal JStart of another d type flip flop, clock pulse terminal CP meets signal JStop, and Q end output time is stop signal JJStop at interval; The equal welding system reset signal of the reset terminal R RESET of two d type flip flops;

The time interval measurement unit is used to measure the time interval T that rising edge is tandem time interval commencing signal JJStart, stop signal JJStop _x

2. time parameter measuring system according to claim 1 is characterized in that also comprising:

One delay line calibration unit, the delay line calibration unit is made up of two lag lines, an interconnection line and a scrambler;

Produce former and later two time interval signals SStart and SStop through a reference instrument, the time interval of this moment is T _X1, and T _X1＜t _L, time interval commencing signal SStart is from lag line 1 input, and time interval stop signal SStop latchs the output state of delay cell in lag line 1 and the lag line 2, obtains exporting N as a result through decimal encoder then _Cal-1In like manner, produce two time interval signal SStart and SStop through reference instrument once more, the time interval of this moment is T _X2, and t _L＜T _X2＜2*t _L, in like manner obtain exporting N as a result _Cal-2, then, the t and t time delay of interconnection line time delay of delay cell _{Δ L}:

$\left\{\begin{array}{c}t=\frac{T_{x1}}{N_{\mathrm{cal}-1}}\\ t_{\mathrm{\&Delta;L}}=T_{x2}-N_{\mathrm{cal}-2}*\frac{T_{x1}}{N_{\mathrm{cal}-1}}\end{array}\right.$

T and t time delay of interconnection line time delay with delay cell _{Δ L}The substitution formula:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}}$

Proofreaied and correct time interval T thereby reach _X:, i.e. the purpose of smart time measuring unit.

3. time parameter measuring system according to claim 1; It is characterized in that; Described time interval measurement unit comprises two counters and an XOR gate; The clock end CP of two countings meets clock signal

and CLK respectively; Enable Pin EN connects XOR gate output, and

and CLK 180 ° of phasic differences mutually;

The output result of two counters is respectively CNT1 and CNT2, and then time interval Tx is:

$T_x=\frac{\mathrm{CNT}1+\mathrm{CNT}2}{2}*T$

Wherein, T is the count pulse clk cycle of counter.

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