WO2018032644A1 - Bandwidth modulation domain measurement system and method therefor - Google Patents

Abstract

The present invention provides a bandwidth modulation domain measurement system, comprising: a signal synchronization unit, a logic selection unit, a first tapped delay line multipath time delay unit, a second tapped delay line multipath time delay unit, a first data buffer unit, a second data buffer unit, and a processing unit. The signal synchronization unit receives a signal to be measured and uses same as an input, and an output signal of the signal synchronization unit is connected to the logic selection unit. The logic selection unit receives the output signal of the signal synchronization unit and uses same as an input, and an output signal of the logic selection unit is connected to the first tapped delay line multipath time delay unit and the second tapped delay line multipath time delay unit. The first tapped delay line multipath time delay unit is connected to the first data buffer unit. The second tapped delay line multipath time delay unit is connected to the second data buffer unit. Outputs of the first data buffer unit and the second data buffer unit are connected to the processing unit. The measurement system of the present invention features a simple structure, and greatly simplifies circuit and sequence design difficulty and complexity.

Description

Broadband modulation domain measurement system and method thereof Technical field

The present invention relates to the field of testing technologies, and in particular, to a wideband modulation domain measurement system, and to a wideband modulation domain measurement method.

Background technique

The modulation domain, time domain, and frequency domain are also referred to as "three domains." Time domain analysis measures the relationship of input signal amplitude with time; frequency domain analysis measures the relationship of input signal amplitude with frequency; and modulation domain analysis measures the relationship of input signal frequency with time.

With the development of communication technology, the frequency conversion, continuous wave frequency modulation, linear frequency modulation, pulse modulation, digital modulation and combined modulation technology have been rapidly developed and applied, and the frequency band has also been greatly expanded, and higher requirements have been put forward for the indicators. . In order to meet new demands, modern modulation domain analysis requires measurement requirements such as large bandwidth, high speed and high resolution, no dead zone and short sampling interval.

Because modulation domain analysis has unique advantages over time domain analysis and frequency domain analysis, modulation domain analysis has been widely used in anti-jamming communication, agile radar, and electronic warfare systems. It is the development, production, maintenance, etc. of military and civilian electronic systems. The necessary equipment for the stage.

Modulation domain analysis accurately measures the transient characteristics of the signal under test by high-speed continuous zero idle measurement. The typical measurement timing is shown in Figure 1. The gate signal is synchronized with the signal under test, and the signal to be measured is controlled by the synchronous gate. The counter can eliminate ±1 signal error of the measured signal. Gate time is measured with a higher frequency standard time base signal, which results in higher frequency resolution than conventional counters. Since the standard time base signal is not synchronized with the synchronous gate, there is still ±1 standard time base error. In order to improve the test The quantity resolution also requires precise time-interpolation measurement of the error of the standard time base and the front edge of the gate and the trailing edge of the gate. The measurement results are calculated as follows:

f ₁ =N ₁ /(T ₁ +ΔT ₁ -ΔT ₂ ) (1)

Where: f ₁ is a frequency measurement;

N ₁ is the measured signal count value;

T1 is calculated based on the time base count value;

ΔT ₁ and ΔT ₂ are precision interpolated measurements.

The typical system used in the modulation domain measurement is shown in Figure 2. The gate generation unit first generates the original gate G ₀ . The original gate is synchronized with the signal under test to generate the synchronous gate signal G _s , G _s as two sets of event counters and time counters. When the energy signal, G _s is high level, the control event counting unit 1 and the time counting unit 1 count the measured signal and the time base signal. When G _s is low level, the control event counting unit 2 and the time counting unit 2 are controlled. The measurement signal and the time base signal are counted. Simultaneously, the synchronous gate signal and the time base signal generate a synchronous gate leading edge error pulse E ₁ and a trailing edge error pulse E ₂ via the gate logic control unit, and the two error pulses are sent to the charging and discharging circuit of the analog interpolation unit, and the linear error pulse is applied. Expanded into a relatively large pulse, after the expansion process to complete the error compensation and counting, can effectively improve the time or frequency resolution.

The method of broadening the error pulse is to charge a capacitor with a constant current while the error pulse is high; then discharge at a slow N times (for example, N=1000), then the time during which the capacitor is discharged to the initial state is the error pulse. N times the width, the amplified pulse signal can be obtained by the shaping circuit at the time of the charging of the capacitor and the time when the capacitor is discharged to the initial state, and then the measurement is counted by the standard clock to obtain the expanded pulse width.

Another method of error pulse expansion is to convert the error pulse into a ramp voltage according to the required ratio. At the start and end times of the error pulse, the voltage is sampled by A/D, and the measured voltage is measured. The pressure value and the voltage conversion ratio are calculated to obtain an expanded correction value.

Finally, the event count value, the time count value and the before and after interpolation correction values are uniformly calculated according to formula (1), and the final measured signal frequency is obtained.

In the above measurement system, the error pulse charge and discharge circuit of the analog interpolation unit is a key part, which directly determines the measurement accuracy and measurement speed of the entire system. The phase difference between the time base signal and the synchronous gate signal is the error pulse signal to be measured. The range of the error pulses E ₁ and E ₂ is 0 to a time base signal period, and it is possible to directly charge it with the pulse. The situation, which leads to analog interpolation failure or a large error, so the error pulse is generally stretched, and the error pulse is linearly converted into a relatively large pulse or a relatively large voltage, and then followed. Processing, error pulse charging and discharging circuit is generally implemented by a current source and a bridge diode charging and discharging circuit.

The main limitation of the above measurement system is that in order to avoid the situation that the analog interpolation is invalid or the error is large due to the narrow error pulse, the error pulse width is not required to be too small, and the error pulse width needs to be expanded; in order to achieve higher precision, It is required to expand the error pulse by a large multiple. The combined effect of the error pulse width and the larger multiple expansion allows the total time of the interpolation extension to scale up. When the error pulse is extended by the comparison circuit, the spread pulse will be wider, so that the interpolation extension time is longer; when the AD converter sampling mode is used for expansion, in order to fully utilize the effective range of the AD converter, charge and discharge are required. The effective voltage range is wider, and the interpolation is extended for a longer period of time. At the same time, a certain reset time is reserved for the analog interpolation unit after each measurement, so these two methods will eventually limit the minimum sampling interval of continuous measurement.

Since the analog circuit is sensitive to operating temperature, the analog interpolation method is less stable. At the same time, due to the certain leakage current of the circuit itself, the capacitor charging output voltage has a certain nonlinearity, which also has a great influence on the measurement accuracy. To achieve higher resolution, accurate calibration of the voltage nonlinearity is required. In addition, due to the inherent charge and discharge time limitation of the analog circuit, the time interval for a single measurement of the analog interpolation method is not too small, which is greatly limited in the field of high-speed short sampling interval measurement.

In order to achieve high resolution requirements, the vernier method is used to measure the error pulse. The cursor method uses the principle of the vernier caliper to measure the difference between the edge of the gate and the rising edge of the standard counting clock. Usually, a pair of cursor clocks are designed. When the counting gate is opened and closed, the cursor counter is started, and the cursor clock continuously tracks the standard counting clock. The cursor counter is turned off when the clock edge coincides with the rising edge of the standard count clock.

The measurement error is proportional to the difference between the standard count clock period and the wiper clock period. The smaller the difference between the standard count clock and the wiper clock, the higher the resolution. The cursor tracking time is inversely proportional to the difference between the count clock period and the cursor clock period. The smaller the difference between the count clock and the cursor clock, the longer the cursor tracking time. In order to achieve higher resolution and minimize measurement time, it is necessary to use the highest possible standard clock frequency and vernier clock frequency, and complex high-resolution frequency control technology is required to generate standard count clock and cursor clock, and strictly control all The frequency and phase of the clock, and achieve very high precision and stability, the circuit is complex, and the implementation is difficult. At the same time, when the interval between the edge of the counting gate and the rising edge of the counting clock is small, due to the limitation of the response time of the device itself, there is a certain dead zone in the starting and closing of the cursor counter, so that the minimum tracking time is limited.

Based on the measurement system shown in Figure 2, with the development of programmable logic devices, the implementation shown in Figure 3 has been developed.

The gate generating unit first generates the original gate G ₀ , and the original gate synchronizes with the measured signal to generate a synchronous gate signal G _s , G _s as an enable signal of two sets of event counting units and time counting units, and when G _s is high level, the high speed event counting unit 1, a low speed event counting means, time counting unit 1 counts the high-speed and low-speed time unit 1 is operated, when G _s is low, high speed event counting unit 2, a low speed event counting unit 2, the high-speed and low-speed time counting unit 2 The time counting unit 2 operates. The two sets of counting units are controlled by the gate synchronizing signal G _s generated by the gate synchronizing unit. When one set of counting units is operating, the other group performs parameter buffer processing, synchronization and reset operations. At the same time, the synchronous gate signal and the time base signal generate a synchronous gate leading edge error pulse E ₁ and a trailing edge error pulse E ₂ through the gate logic control unit, and the two error pulses are sent to the digital interpolation processing unit, and the error pulse is linearly expanded to be relative Large pulses, after error processing, complete error compensation and counting, which can effectively improve time or frequency resolution.

When all the event counting unit and the time counting unit are implemented by a dedicated chip, if the long-term measurement requirement is to be met, a high bit width counting is required, which is realized by cascading multiple dedicated counting chips, and the printed board design is complicated and the implementation cost is realized. high. When all event counters and time counters are implemented by programmable devices, the advantage is that the integration and design flexibility can be greatly improved, and the cost can be reduced, but it is difficult to achieve large bandwidth measurement due to the speed limitation of the logic chip itself. Claim. In the implementation shown in FIG. 3, the high-speed event counting unit and the high-speed time counting unit are composed of a dedicated high-speed counter chip, and the low-speed event counting unit and the low-speed time counting unit are implemented inside the programmable logic chip, and receive the high-speed event counting unit. The highest bit output is used as an input and is responsible for counting the highest bit of the input. The implementation scheme shown in Figure 3 makes full use of the advantages of fast chip, high performance, large bandwidth, programmable logic device programming, flexible configuration, and good scalability. It is rationally designed and integrated to make full use of it. With their respective characteristics, the frequency range of the signal under test is expanded.

The implementation shown in Figure 3 uses digital interpolation techniques. The digital interpolation technique is characterized by the characteristics of the propagation delay of the electrical signal to complete the measurement of the error pulse signal. It does not have the charge and discharge link required for analog interpolation. Increases the speed of interpolation and extends the effective range of sampling intervals. The principle of digital interpolation is shown in Figure 4. Digital interpolation uses a set of delay units with theoretically equal propagation delays to form a delay chain. The method of "serial delay, parallel counting" is used to achieve high resolution time. measuring. Time delay interpolation The resolution depends on the delay time of the unit delay unit. The smaller the delay time, the higher the measurement resolution.

The prior art solutions have the following disadvantages:

(1) The prior art includes two symmetrical event counting, time counting, interpolation counting and the like, and the implementation and control are very complicated.

When all event counters and time counters are implemented by dedicated chips, if long-term measurement requirements are to be met, high bit-width counting is required. This is achieved by cascading multiple dedicated counting chips, and the printed board design is complicated and the implementation cost is high.

When all event counters and time counters are implemented by programmable devices, the advantage is that the integration and design flexibility can be greatly improved, and the cost can be reduced, but it is difficult to achieve large bandwidth measurement due to the speed limitation of the logic chip itself. Claim.

Reasonable design and integration of dedicated chips and programmable logic devices can fully utilize their respective characteristics to meet the large bandwidth measurement requirements of the modulation domain, but further enhance the design complexity.

(2) There are great limitations in high-speed frequency measurement.

High-resolution measurements can be achieved with analog interpolation, but analog interpolation is less stable due to the higher sensitivity of the analog circuit to operating temperature. At the same time, due to the certain leakage current of the circuit itself, the capacitor charging output voltage has a certain nonlinearity, which also has a great influence on the measurement accuracy. To achieve higher resolution, accurate calibration of the voltage nonlinearity is required. In addition, due to the inherent charge and discharge time limitation of the analog circuit, the time interval for a single measurement of the analog interpolation method is not too small, which is greatly limited in the field of high-speed short sampling interval measurement.

The vernier method requires the use of the highest possible standard clock frequency and the vernier clock frequency, and requires complex high-resolution frequency control technology to generate the standard count clock and the vernier clock, and strictly control the frequency and phase of all the clocks. The circuit is complicated and difficult to implement. Big. At the same time, when counting the edge of the gate and rising edge of the count clock When the interval between the two is small, due to the response time of the device itself, there is a certain dead zone in the start and stop of the cursor counter, so that the minimum tracking time is limited.

The digital interpolation technique is used to construct the delay chain of "serial delay and parallel counting" to complete the measurement of the error pulse signal. It does not simulate the charging and discharging links required for interpolation, and can further improve the speed of interpolation and expansion. In order to meet the continuous dead zone measurement requirements, a symmetric two-way measurement channel alternate operation mode is adopted, and the two channels are respectively controlled by the complementary two-way gate synchronization signals G _s and /G _s generated by the gate high-speed synchronization unit, in order to ensure each unit Accurate synchronization, and each gate can accurately count events and time, the gate time width can not be too small, the highest level of the prior art, the minimum gate width is 100ns, and the fast broadband frequency hopping signal is still not fast and accurate. The frequency switching time is measured.

(3) In the existing implementation scheme, since the event signal and the time signal are asynchronous signals, the synchronous gate is completely synchronized with the event signal. If the edge of the event and the time signal are very close, the time counting unit and the error pulse extracting unit are in the gate. During signal synchronization, it is inevitable that there will be occasional ±1 errors and timing errors will occur.

(4) The implementation of the prior art solution is complicated, resulting in high cost of the prior art solution.

Summary of the invention

In order to solve the above deficiencies in the prior art, the present invention discloses a wideband modulation domain measurement system and a method thereof. Compared with the prior art solution, the present invention has a simple structure, and the gate generation unit, the gate synchronization unit, and the time counting unit are The event counting unit and the error extraction unit are all simplified, which greatly simplifies the design difficulty and complexity of the circuit and the timing.

The technical solution of the present invention is implemented as follows:

A wideband modulation domain measurement system includes: a signal synchronization unit, a logic selection unit, and a first tap a delay line multiplex delay unit, a second tap delay line multiplex delay unit, a first data buffer unit, a second data buffer unit, and a processing unit;

The signal synchronization unit receives the measured signal as an input, and the output signal is connected to the logic selection unit; the logic selection unit receives the output signal of the signal synchronization unit as an input, the output signal and the first tap delay line multi-channel delay unit and the second tap extension The time line multi-channel delay unit is connected; the first tap delay line multi-channel delay unit is connected with the first data buffer unit; the second tap delay line multi-channel delay unit is connected with the second data buffer unit; the first data The outputs of the buffer unit and the second data buffer unit are coupled to the processing unit.

Optionally, the signal synchronization unit is implemented by a programmable logic chip, and when the measurement is started, the timing control signal is synchronously generated by the rising edge of the measured signal, and sent to the logic selection unit; according to the requirement of the measurement resolution, the M signals are selected every interval. Cycle, output a synchronization signal, M ≥ 1.

Optionally, the logic selection unit receives an output signal of the signal synchronization unit, and is logically selected and controlled to be sent to the first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit;

After the first tap delay line delay unit performs a multiple measurement; measured at initial startup, a first tapped delay line multiplexer and the STOP START delay unit using _a logic selection signal generation unit and the STOP START ₁ When starting the measurement for the second time, use STOP _2N-2 and STOP _2N-1 as START and STOP ₁ ; when starting the measurement for the third time, use STOP _3N-4 and STOP _3N-3 as START and STOP ₁ ...;

The START and STOP ₁ of the second tap delay line multi-channel delay unit share the same signal as the STOP _N-1 and STOP _{N of the} first tap delay line multi-channel delay unit to form a cascade structure.

Optionally, the first tap delay line multiple delay unit and the second tap delay line multiple delay unit are used to extract a delay state between the START signal and STOP ₁ , STOP ₂ ... STOP _N , Then calculate the delay time between them;

The first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit are in the alternation In order to ensure the operation of the multi-channel delay unit of one tap delay line, the data of the other channel can be correctly latched and reset in time, and the multi-channel delay unit of the tap delay line also synchronously outputs the LOCK signal for The data buffer unit latches the data. After the data is latched, the TTL signal is also generated inside the multi-channel delay unit of the tap delay line for the internal state reset of the multi-channel delay unit of the tap delay line.

Optionally, the first data buffer unit and the second data buffer unit are responsible for latching the measurement data of the first tap delay line multiple delay unit and the second tap delay line multiple delay unit in time.

Optionally, the processing unit is responsible for interacting with the first data buffer unit and the second data buffer unit, reading measurement data through the high speed interface, and performing final operation, processing, and display on the data.

Optionally, in the above broadband modulation domain measurement system, the front end adds a prescaler unit.

The invention also proposes a wideband modulation domain measurement method, which uses the above measurement system to perform modulation domain measurement on the measured signal.

The beneficial effects of the invention are:

(1) The structure is simple, and the gate generating unit, the gate synchronizing unit, the time counting unit, the event counting unit, and the error extracting unit are all simplified, which greatly simplifies the design difficulty and complexity of the circuit and the timing;

(2) No gate generation unit, gate synchronization unit, time counting unit, error extraction unit, etc. are completely synchronized by the event signal, eliminating the synchronization error problem of the asynchronous signal such as the gate signal, the event signal and the time signal, and the work is more stable. High reliability;

(3) The circuit and timing are simplified, the cost is low, it is easy to implement with a programmable device, and it is also easy to customize a dedicated logic chip with high integration and good confidentiality.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

Figure 1 is a timing diagram of zero idle count operation;

Figure 2 is a block diagram showing a typical system used in modulation domain measurement;

Figure 3 is a block diagram of another typical system used in modulation domain measurement;

Figure 4 is a schematic diagram of digital interpolation;

Figure 5 is a schematic diagram of a wideband modulation domain measurement system of the present invention;

Figure 6 is a timing diagram of a signal synchronizing unit of the present invention;

7 is a schematic diagram of a tap delay line multi-channel delay unit of the present invention;

8 is a package diagram of a tap delay line multi-channel delay unit of the present invention;

Fig. 9 is a schematic view showing the basic structure of a tapped delay line circuit of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

As shown in FIG. 5, the present invention provides a wideband modulation domain measurement system, including: a signal synchronization unit, a logic selection unit, a tapped delay line multiple delay unit, a data buffer unit, and a processing unit.

The signal synchronizing unit receives the measured signal as an input, and the output signal thereof is connected to the logic selecting unit; the logic selecting unit receives the output signal of the signal synchronizing unit as an input, the output signal and the first tap delay line multi-channel delay unit and the The two-tap delay line is connected by a multi-channel delay unit; the first tap delay line multi-channel delay unit is connected to the first data buffer unit; the second tap delay line multi-channel delay unit is connected to the second data buffer unit; The outputs of the first data buffer unit and the second data buffer unit are coupled to the processing unit.

The signal synchronization unit receives the measured signal as an input, and when the measurement is started, the timing control signal is synchronously generated by the rising edge of the measured signal, and sent to the logic selection unit.

The signal synchronization unit is realized by a programmable logic chip. The timing is as shown in Fig. 6. From the rising edge of the signal under test, signals such as START, LOCK, RESET, and STOP are synchronously generated and sent to the logic selection unit. According to the needs of the measurement resolution, M signal periods can be selected every interval, and a synchronization signal can be output, and the minimum value of M can be 1. If the time interval between STOP ₁ and START is T ₁ , the time interval between STOP ₂ and START is T ₂ , and the time interval between STOP ₃ and START is T ₃ ..., then f ₁ =M/T ₁ , f ₂ =M/(T ₂ -T ₁ ), f ₃ =M/(T ₃ -T ₂ )......

The logic selection unit is implemented by a programmable logic chip, and receives the output signal of the signal synchronization unit. The “logic selection” of the dashed box is part of the logic selection unit. The reason why it is drawn outside is to explain the source of the START and STOP1 signals more clearly. And a cascading relationship between the first tap delay line multi-delay unit and the second tap delay line multi-channel delay unit. After the first tap delay line delay unit performs a multiple measurement; measured at initial startup, a first tapped delay line multiplexer and the STOP START delay unit using _a logic selection signal generation unit and the STOP START ₁ When starting the measurement for the second time, use STOP _2N-2 and STOP _2N-1 as START and STOP ₁ ; when starting the measurement for the third time, use STOP _3N-4 and STOP _3N-3 as START and STOP ₁ .... The START and STOP ₁ of the first tap delay line multiplex delay unit and the STOP _N-1 and STOP _{N of the} second tap delay line multiplex delay unit share the same signal to form a cascade structure. This cascading method eliminates systematic errors between the two tap delay line multiple delay units.

The first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit are used to extract the delay state between the START signal and STOP ₁ , STOP ₂ ... STOP _N , and then calculate between them Delay time. The first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit are in an alternate working state, in order to ensure that one channel tap delay line multi-channel delay unit works, the other way data can be correct The latch output and the timely reset, the tap delay line multi-channel delay unit also synchronously outputs the LOCK signal for the data buffer unit to latch the data. After the data is latched, the tap delay line multi-channel delay unit is also internally generated. The RESET signal is used for the internal state reset of the tap delay line multi-delay unit. The relevant timing is clearly given in Figure 6.

The first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit can be implemented by a programmable logic chip, or can be implemented by a dedicated chip, as shown in FIG. 7 , the tap delay line is multi-channel The delay unit includes a multi-way cascaded delay line circuit structure that supports the same start signal and multiple end signals. The above-mentioned multi-way cascaded delay line circuit structure is packaged into one module, and the output latch signal is considered, and the tap delay line multi-channel delay unit can be obtained, as shown in FIG.

The tap delay structure is a basic implementation structure of digital interpolation. It is an all-digital high-precision time interval measurement method. When an electrical signal is transmitted through an electronic component and a connecting wire, a time delay phenomenon must be generated as a measurement time. Means of separation. Figure 9 is a schematic diagram showing the basic structure of a tapped delay line circuit.

The tapped delay line circuit utilizes a logic buffer gate whose output logic state changes with the input as a basic component for delay, and each delay component is followed by a flip-flop. The start pulse signal is input to the series input end of the first delay unit. Since the signal takes time through each logic gate and the connecting wire, this signal will be transmitted through each logic buffer gate in turn, so that the output of each buffer gate Taking the delay time of τ as the interval Separately, changing its output state in turn. When the rising edge of the stop signal STOP comes, each flip-flop records how many logic buffer gates have changed state up to this point, and then the internal circuit converts the number of delay units whose states have changed into digital signal outputs. The time interval to be tested can be obtained by the following formula:

T=m×τ (2)

In the formula, T is the time interval between the rising edge of the START signal and the rising edge of the STOP signal, and m is the number of delay cells that have changed state. The delay time of the delay unit is also the minimum time interval that the tap delay line circuit can resolve, which determines the resolution of the time interval measurement. The number of delay units is multiplied by the delay time of each unit, which determines the delay time measurement. range.

In FIG. 5, the first data buffer unit and the second data buffer unit are responsible for latching the measurement data of the first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit in time.

The processing unit is responsible for interacting with the data buffer unit, reading the measurement data through the high-speed interface, and performing the final calculation, processing, and display of the data.

On the basis of the embodiment shown in FIG. 5, the prescaler unit is added to the front end of the wideband modulation domain measurement system, and the frequency measurement range can be further expanded to realize ultra-wideband frequency measurement.

Based on the above wideband modulation domain measurement system, the present invention also proposes a wideband modulation domain measurement method. The measurement principle has been described in detail in the measurement system, and will not be described herein.

The wideband modulation domain measurement system of the present invention has the following advantages:

(1) The realization of the block diagram structure is simple, and the gate generation unit, the gate synchronization unit, the time counting unit, the event counting unit, and the error extraction unit are all simplified, which greatly simplifies the design difficulty and complexity of the circuit and the timing.

(2) When the signal synchronization unit generates the START and STOP signals, it can select M signal periods per interval according to the needs of the measurement resolution, and output a synchronization signal. The minimum value of M can be 1, which can be greatly The sampling interval of the frequency signal is reduced to meet the frequency switching time measurement requirement of the broadband fast frequency hopping signal.

(3) In the existing implementation scheme, since the event signal and the time signal are asynchronous signals, the synchronous gate is completely synchronized with the event signal. If the edge of the event and the time signal are very close, the time counting unit and the error pulse extracting unit are in the gate. During signal synchronization, it is inevitable that there will be occasional ±1 errors and timing errors will occur. The scheme does not need the gate generating unit, the gate synchronizing unit, the time counting unit, the error extracting unit, etc., and is completely synchronized by the event signal, eliminating the synchronization error problem of the asynchronous signal, and the work is more stable and the reliability is high.

(4) For the chips of the tapped delay line multiplex structure produced by other manufacturers, referring to the principle block diagram and the timing diagram of the present invention, the upgrade can be easily replaced and the scalability is good.

(5) The technical solution of the present invention has a simple structure, simplified circuit and timing, and low cost.

(6) It is easy to implement with a programmable device, and it is also easy to customize a dedicated logic chip with high integration and good confidentiality.

(7) On the basis of the principle block diagram of the present invention, the front end adds a prescaler unit, which can further expand the frequency measurement range to realize ultra-wideband frequency measurement.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are included in the spirit and scope of the present invention, should be included in the present invention. Within the scope of protection.

Claims (8)

1. A wideband modulation domain measurement system, comprising: a signal synchronization unit, a logic selection unit, a first tap delay line multiple delay unit, a second tap delay line multiple delay unit, a first data buffer unit, a second data buffer unit and a processing unit;

   The signal synchronization unit receives the measured signal as an input, and the output signal is connected to the logic selection unit; the logic selection unit receives the output signal of the signal synchronization unit as an input, the output signal and the first tap delay line multi-channel delay unit and the second tap extension The time line multi-channel delay unit is connected; the first tap delay line multi-channel delay unit is connected with the first data buffer unit; the second tap delay line multi-channel delay unit is connected with the second data buffer unit; the first data The outputs of the buffer unit and the second data buffer unit are coupled to the processing unit.
2. The wideband modulation domain measurement system according to claim 1, wherein the signal synchronization unit is implemented by a programmable logic chip, and when the measurement is started, the timing control signal is synchronously generated by the rising edge of the measured signal and sent to the logic selection unit; According to the needs of measurement resolution, select M signal periods per interval and output a synchronization signal, M≥1.
3. The wideband modulation domain measurement system according to claim 1, wherein the logic selection unit receives an output signal of the signal synchronization unit, and is logically selected and controlled to be sent to the first tap delay line multi-channel delay unit and Second tap delay line multi-channel delay unit;

   After the first tap delay line delay unit performs a multiple measurement; measured at initial startup, a first tapped delay line multiplexer and the STOP START delay unit using _a logic selection signal generation unit and the STOP START ₁ When starting the measurement for the second time, use STOP _2N-2 and STOP _2N-1 as START and STOP ₁ ; when starting the measurement for the third time, use STOP _3N-4 and STOP _3N-3 as START and STOP ₁ ...;

   The START and STOP ₁ of the second tap delay line multi-channel delay unit share the same signal as the STOP _N-1 and STOP _{N of the} first tap delay line multi-channel delay unit to form a cascade structure.
4. The wideband modulation domain measurement system according to claim 3, wherein said first tap delay line multiplex delay unit and said second tap delay line multiplex delay unit are configured to extract a START signal and STOP ₁ , STOP ₂ ... the delay state between STOP _N , and then calculate the delay time between them;

   The first tap delay line multi-channel delay unit and the second tap delay line multi-channel delay unit are in an alternate working state, in order to ensure that one channel tap delay line multi-channel delay unit works, the other way data can be correct The latch output and the timely reset, the tap delay line multi-channel delay unit also synchronously outputs the LOCK signal for the data buffer unit to latch the data. After the data is latched, the tap delay line multi-channel delay unit is also internally generated. The RESET signal is used for the internal state reset of the tap delay line multi-delay unit.
5. The wideband modulation domain measurement system according to claim 1, wherein said first data buffer unit and said second data buffer unit are responsible for latching the first tap delay line multi-channel delay unit and the second tap delay in time. Measurement data of the time line multi-channel delay unit.
6. The wideband modulation domain measurement system according to claim 1, wherein said processing unit is responsible for interacting with said first data buffer unit and said second data buffer unit, reading measurement data through a high speed interface, and being responsible for data Perform final calculations, processing, and display.
7. The wideband modulation domain measurement system according to any one of claims 1 to 6, wherein the front end adds a prescaler unit.
8. A wideband modulation domain measurement method, characterized in that the measurement signal is subjected to modulation domain measurement using the measurement system according to any one of claims 1 to 7.

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