CN110350892B - Time delay device and method based on DDS clock phase shift technology - Google Patents
Time delay device and method based on DDS clock phase shift technology Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention belongs to the technical field of sampling oscilloscopes, and particularly relates to a time delay device and a time delay method based on a DDS clock phase shift technology, wherein the time delay device comprises a trigger input module, a DDS module, an FPGA module, a time delay pulse synchronization module and a sampling trigger pulse output module, wherein the trigger input module is connected with the input end of the DDS module; the frequency measurement module in the FPGA module is connected with the output end of the DDS module; a control communication module in the FPGA module is connected with a communication interface of the DDS module; the DDS module is connected with the data input end of the delay pulse synchronization module; the pulse signal generating module of the FPGA module is connected with the clock input end of the delay pulse synchronization module; the output end of the delay pulse synchronization module is connected with the sampling trigger pulse output module. The scheme is applied to a sampling oscilloscope, and can solve the problems of low delay precision and small range in sequential equivalent sampling.
Description
Technical Field
The invention belongs to the technical field of sampling oscilloscopes, and particularly relates to a time delay device and a time delay method based on a DDS (direct digital synthesizer) clock phase shifting technology.
Background
The equivalent sampling technique is a non-real-time sampling technique, and can perform undistorted sampling on a periodic signal with a sampling frequency much lower than that of an original signal. The sampling oscilloscope adopts a sequential equivalent sampling technology, and the upper limit of the frequency can be expanded to dozens of GHz by a sampling device 'sampler'. The synchronous trigger signal is input into the oscilloscope time base unit, the sampling pulse is subjected to stepping delay according to the delay amount corresponding to the time base, the sampling pulse controls the sampler to sample at different positions behind the initial point of the measured signal through a plurality of cycles, and finally the waveform of the measured signal is displayed in an expanded mode. The equivalent sampling rate that the sequential equivalent sampling can realize depends mainly on the delay precision of the time base unit. The high-precision delay method adopted in the current engineering is a dual-ramp comparison method and a special delay chip method.
The dual ramp comparison method is described in the article entitled "design of high precision step delay system for time domain reflectometer". The method can output delay pulses with the highest precision and the step value of 8.6ps, and although the problem of uneven step delay amount corresponding to a non-linear region of capacitor charging is solved, the fast and slow ramp waves have high noise and cannot be applied to an equivalent sampling system with higher precision requirement. The adoption of the special delay chip can generate 10ps stepping delay precision, the single-chip delay range is 10ns, and the defects of low delay precision and small delay range exist. The improvement of the upper limit of the sampling frequency of the equivalent sampling oscilloscope is limited by low delay precision, the maximum equivalent sampling rate of the method is 110GSa/s, and equivalent sampling of high-frequency signals above 22GHz cannot be met in engineering.
Disclosure of Invention
Aiming at the technical problem, the invention provides a time delay device and a time delay method based on a DDS clock phase shift technology, which can improve the time delay precision in equivalent sampling.
In order to solve the technical problems, the invention adopts the technical scheme that:
a time delay device based on DDS clock phase shift technology comprises a trigger input module, a DDS module, an FPGA module, a time delay pulse synchronization module and a sampling trigger pulse output module, wherein the trigger input module is connected with the input end of the DDS module; the frequency measurement module in the FPGA module is connected with the output end of the DDS module; a control communication module in the FPGA module is connected with a communication interface of the DDS module; the DDS module is connected with the data input end of the delay pulse synchronization module; the pulse signal generating module of the FPGA module is connected with the clock input end of the delay pulse synchronization module; the output end of the delay pulse synchronization module is connected with the sampling trigger pulse output module.
The DDS module adopts a DDS chip AD9914.
A time delay method based on DDS clock phase shift technology comprises the following steps:
s1, determining a delay parameter: the FPGA module receives the stepping delay quantity delta t and the phase-shifting step number N; outputting a periodic pulse signal D;
s2, generating a clock signal CLK: an external trigger signal is input into a DDS module, the DDS carries out frequency division by an integer value and outputs a clock signal CLK; inputting the CLK signal into an FPGA frequency measurement module, and measuring the frequency of the CLK signal by the FPGA to obtain a period T, namely a delay range;
s3, calculating DDS phase control words;
and S4, transmitting the step number N of the stepping phase shift to the FPGA according to the upper computer, increasing the parameter of each phase shift by delta theta, completing the phase shift for N times, obtaining the N delta t delay, and finishing the system execution.
In the S3: the FPGA determines a phase offset delta theta according to the received delay time delta t; the ratio of the delay time delta T to the period T of the divided synchronous clock CLK signal is the same as the ratio of the phase shift value delta theta to the total phase value 2 pi, so that:
converting the phase offset into a phase control word POW of the DDS, and the calculation formula is as follows:
wherein m is the phase tuning resolution digit of the DDS;
and writing the phase control word POW into a DDS chip of the U2 to finish one-time phase shifting operation, and outputting a CLK _1 signal by the DDS.
Compared with the prior art, the invention has the following beneficial effects:
the CLK signal is phase-shifted by N times by taking the delta theta as a stepping value, and the pulse signal D generated by the FPGA is synchronized by the CLK signal, so that the relative sequential time delay can be realized. The precise time delay is indirectly obtained by utilizing the conversion of the phase and the time, and the phase shift parameter delta theta is determined by the delay parameter delta T transmitted by an upper computer, the number of sampling points and the clock period T of the signal CLK. When the scheme is applied to the sampling oscilloscope, the sampling points are more, the CLK signal period is smaller, and the required delay range is larger than the period T, the CLK period T is enlarged by integral multiple frequency division through the DDS, so that the period T is larger than the required traversal time window time, and the problems of low delay precision and small range in the sequential equivalent sampling are solved.
The DDS technology is adopted to tune the external trigger signal, the delay step length can be flexibly selected, and the DDS has more flexible application compared with a special delay chip which generates the delay step length of integral multiple of 10 ps. The high-frequency external trigger signal input can be realized, the 1ps delay precision can be generated under the condition of low enough jitter, the delay precision can be higher than that of a special delay chip by adopting a high-phase resolution DDS chip, the equivalent sampling rate of more than 1TS/s can be obtained in an equivalent sampling system, and the upper limit of the frequency of equivalent sampling is improved. And the FPGA is adopted to control the whole system, so that debugging and expansion are facilitated. The circuit system has high integration level and strong signal anti-interference capability.
Drawings
FIG. 1 is a schematic block diagram of the connection of the present invention;
FIG. 2 is a schematic diagram of the D flip-flop clock phase tuning delay of the present invention;
FIG. 3 is a schematic of the sampling of the present invention as applied to sequential equivalent sampling;
wherein: u1 is a trigger input module, U2 is a DDS module, U3 is an FPGA module, U4 is a delay pulse synchronization module, and U5 is a sampling trigger pulse output module.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 and 2, a time delay device based on the DDS clock phase shift technology includes a trigger input module U1, a DDS module U2, an FPGA module U3, a delay pulse synchronization module U4, and a sampling trigger pulse output module U5. The trigger input module U1 is connected with the input of the DDS module U2; a frequency measurement module in the FPGA module U3 is connected with the output of the DDS module U2; a control communication module in the FPGA module U3 is connected with a communication interface of the DDS module U2; the DDS module U2 is connected with the data input end of the delay pulse synchronization module U4; a pulse signal generating module of the FPGA module U3 is connected with a clock input end of a delay pulse synchronization module U4; the output end of the delay pulse synchronization module U4 is connected with the sampling trigger pulse output module U5.
In the figure, a signal D is a periodic narrow pulse signal generated by an FPGA, and the signal is input to a data input end of a D trigger in a delay pulse synchronization module U4; the signal CLK is a clock signal which is output by the DDS module U2 through frequency tuning and is synchronous with the external trigger signal, and is input to a clock input end of a D trigger in the delay pulse synchronization module U4; the signal Q is a delay sampling trigger pulse signal synchronously output by a D trigger in a delay pulse synchronous module U4.
The circuit modules are composed and functionally designed as follows:
1. trigger input module U1
The trigger input module is used for receiving synchronous external trigger analog signals which are coaxially divided by the detected signals and have the same frequency or frequency division of integral multiple, and carrying out single-end to differential processing on the signals, and the U1 is connected with the DDS module U2.
DDS Module U2
The DDS module U2 comprises a DDS chip, a peripheral function circuit thereof and an output filter circuit. In the invention, in order to realize high-frequency external trigger signal input and realize time delay of subpicosecond magnitude, an internal clock speed of 3.5GSPS, 16-bit phase tuning resolution, 32-bit frequency control words and a DDS chip internally integrating a 12-bit DAC are selected. The DDS has a fractional frequency division mode, the frequency tuning precision can reach the pico-hertz magnitude, and the precision requirement of the DDS is met. The module has the functions of carrying out frequency division and phase shift operation on an external trigger signal according to a phase shift parameter and transmitting a tuned signal serving as a clock signal to the delay pulse synchronization module U4.
FPGA Module U3
The FPGA module U3 mainly implements three functions: measuring the frequency of a signal CLK output by the DDS module U2; receiving the delay delta T transmitted by the upper computer, calculating by combining the CLK period T to obtain frequency and phase control words, and writing the frequency and phase control words into a DDS register; and generating a fixed-period low-frequency pulse signal D, and inputting the fixed-period low-frequency pulse signal D into the input end of a D trigger in the U4.
4. Time delay pulse synchronization module U4
The delay pulse synchronization module U4 is composed of a D trigger circuit. A low-frequency pulse signal D generated by the FPGA is input to a data input end of a D trigger of the module, and a signal CLK output by DDS tuning is input to a clock end of the D trigger. The module realizes the output of a delay signal, and the D trigger outputs a synchronous signal which is a sampling trigger pulse signal. The invention uses D trigger with input frequency up to 6GHz, which possesses low propagation delay and phase noise.
5. Sampling trigger pulse output module U5
The sampling trigger pulse output module U5 has the function of providing driving force for the sampling trigger pulse signal generated by the U4 module, and the driving force is sent into the narrow pulse signal generating circuit after level matching to generate a sampling pulse signal to control the sampler to sample.
As shown in fig. 3, the external trigger signal input DDS tunes the output synchronization signal CLK. And a periodic pulse signal generated by the FPGA is input into a data end of the D trigger, CLK is used as a clock signal and input into the D trigger, and a sampling position corresponding to a falling edge of an output pulse signal Q after synchronization is a first point of a detected signal. Next, the CLK signal is subjected to phase shifting through the DDS, a sampling trigger pulse Q _1 is obtained after synchronization of the D trigger, the falling edge of the sampling trigger pulse Q _1 is delayed by delta t compared with the falling edge of the Q pulse signal, a second point is obtained by sampling on the falling edge, the CLK signal is subjected to phase shifting by 2 delta theta to obtain Q _2, the falling edge is delayed by 2 delta t compared with the falling edge of the Q pulse signal, and a third point is obtained by sampling on the falling edge. The waveform of a complete time window can be traversed through N times of phase shifting operation, N delta t time delay is realized, and the waveform can be recovered by sequentially arranging sampling points.
In order to more intuitively and specifically illustrate the present invention, the delay method based on the DDS clock phase shift technique in the present embodiment is 800MHz based on the external trigger signal input, and includes the following steps:
s1, determining a delay parameter:
setting the delay delta t in the FPGA to be 5ps, and setting the stepping value to be 1023;
the FPGA outputs periodic pulses D with the frequency of 40 KHz.
S2, generating a clock signal CLK:
when external trigger is input to DDS in U2, since the maximum value of the DDS output frequency is 40% of the frequency value of the input signal, the DDS output frequency is divided by 8, and the frequency of the clock signal CLK is tuned and output to be 100MHz through the DDS frequency.
And inputting the CLK signal into a clock end of the D trigger, and simultaneously measuring the frequency by the FPGA to obtain the period T1=10ns.
S3, DDS phase control word calculation:
convert Δ t to a phase offset parameter:
convert it to a phase control word:
and converting the discarded decimal place into hexadecimal place to obtain POW =0020, and inputting the POW =0020 into the DDS chip operation register bit. The DDS outputs a delay signal for shifting the phase by one unit to complete one phase shifting operation.
And S4, sending a phase-shifting step number instruction N =1023, wherein the system needs to complete 1023 phase-shifting operations by taking 0.18-degree as a stepping unit. The Nth time phase shift parameter is increased to delta theta N =1023 × Δ θ =184.14 degrees, POW =82F1, and the delay range is 5.115ns in the case of the delay parameter and the number of phase shift steps, and the system is finished.
When the scheme is applied to the sampling oscilloscope, the sampling points are more, the CLK signal period is smaller, and the required delay range is larger than the period T, the CLK period T is enlarged by integral multiple frequency division through the DDS, and the problems of low delay precision and small range in sequential equivalent sampling are solved.
Although only the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art, and all changes are encompassed in the scope of the present invention.
Claims (4)
1. A time delay method based on DDS clock phase shift technology is characterized by comprising the following steps:
s1, determining a delay parameter: the FPGA module receives the stepping delay quantity delta t and the phase-shifting step number N; outputting a periodic pulse signal D;
s2, generating a clock signal CLK: an external trigger signal is input into a DDS module, the DDS carries out frequency division by an integer value and outputs a clock signal CLK; inputting the CLK signal into an FPGA frequency measurement module, and measuring the frequency of the CLK signal by the FPGA to obtain a period T, namely a delay range;
s3, calculating DDS phase control words;
and S4, transmitting the step number N of the stepping phase shift to the FPGA according to the upper computer, increasing the parameter of each phase shift by delta theta, completing the phase shift for N times, obtaining the N delta t delay, and finishing the system execution.
2. The DDS clock phase shifting technique as claimed in claim 1, wherein in S3:
the FPGA determines a phase offset delta theta according to the received delay time delta t; the ratio of the delay time delta T to the period T of the divided synchronous clock CLK signal is the same as the ratio of the phase shift value delta theta to the total phase value 2 pi, so that:
converting the phase offset into a phase control word POW of the DDS, and the calculation formula is as follows:
wherein m is the phase tuning resolution digit of the DDS;
and writing the phase control word POW into a DDS chip of the U2 to finish one-time phase shifting operation, and outputting a CLK _1 signal by the DDS.
3. The delay device based on DDS clock phase shift technique adopted by the delay method according to claim 1, characterized in that: the device comprises a trigger input module, a DDS module, an FPGA module, a delay pulse synchronization module and a sampling trigger pulse output module, wherein the trigger input module is connected with the input end of the DDS module; the frequency measurement module in the FPGA module is connected with the output end of the DDS module; a control communication module in the FPGA module is connected with a communication interface of the DDS module; the DDS module is connected with the data input end of the delay pulse synchronization module; the pulse signal generating module of the FPGA module is connected with the clock input end of the delay pulse synchronization module; the output end of the delay pulse synchronization module is connected with the sampling trigger pulse output module.
4. The delay device according to claim 3, wherein the delay device is based on DDS clock phase shift technology, and comprises: the DDS module adopts a DDS chip AD9914.
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| CN111413677B (en) * | 2020-02-27 | 2022-09-16 | 湖南师范大学 | Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device |
| CN112436825A (en) * | 2020-10-15 | 2021-03-02 | 中北大学 | High-precision combined delay system and method based on FPGA and delay chip |
| CN113009201B (en) * | 2021-02-24 | 2022-08-23 | 普源精电科技股份有限公司 | Electric signal sampling device |
| CN113064213B (en) * | 2021-03-10 | 2023-05-09 | 欧姆龙(上海)有限公司 | Light receiving device and photoelectric sensor |
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