CN111413677B - Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device - Google Patents
Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device Download PDFInfo
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- CN111413677B CN111413677B CN202010124043.6A CN202010124043A CN111413677B CN 111413677 B CN111413677 B CN 111413677B CN 202010124043 A CN202010124043 A CN 202010124043A CN 111413677 B CN111413677 B CN 111413677B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
- G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
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Abstract
The invention discloses a difference frequency-delay type receiving and sending clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device, wherein the method comprises the steps of obtaining a clock 3 by aiming at clock 1 frequency division and obtaining a clock 4 by aiming at clock 2 frequency division; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero; buffering the clock 3 and outputting to control the transmitter to transmit pulses; buffering the clock 4 and outputting to control a receiver to receive radar echo; the circuit comprises a transmitting clock circuit unit, a receiving clock circuit unit and a controller, wherein the transmitting clock circuit unit and the receiving clock circuit unit respectively comprise a clock source, a frequency divider and a buffer which are sequentially connected. The invention can solve the bottleneck problem of time stepping between receiving and transmitting when a delayer is independently adopted, is beneficial to improving the frequency of the receiver for receiving signals, and overcomes the defects of poor real-time performance, low signal refresh rate and data redundancy of differential frequency type receiving.
Description
Technical Field
The invention belongs to the technical field of ultra-wideband pulse receiving, and particularly relates to a difference frequency-delay type receiving and transmitting clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device.
Background
Ultra-wideband radars are gaining increasing attention in the fields of military, commerce, environmental protection and the like due to their high range resolution, strong penetration, low interception rate and strong interference resistance. The performance of ultra-wideband radar has reached a higher level with the development of wideband microwave devices and the enhancement of signal processing capability of software algorithms since the 90 s of the 20 th century. The ultra-wideband synthetic aperture radar of Swedish, America, Italy, Russia and other countries realizes multiple flight experiments and enters into the practical application stage. In the commercial ultra-wideband radar, the ultra-wideband through-wall radar, the ground penetrating radar and the life detection radar have wide application prospects. The through-wall radar is an ultra-wideband pulse radar and is mainly applied to the military and public safety fields of anti-terrorism warfare, disaster rescue, urban roadway battle and the like. By emitting the ultra-high frequency radar pulse and receiving the echo signal, the through-wall radar can penetrate through doors, brick walls, stone slabs and concrete walls, can comprehensively cover the internal space, can quickly estimate the conditions in a room, and can acquire the accurate position information of the hidden human body and the hidden moving object. Ground Penetrating Radar (also called Ground Penetrating Radar) and geological Radar. Is a nondestructive detection method for determining the distribution of underground media by using radio waves with the frequency of 106-109 Hz. The ground penetrating radar method is that high-frequency electromagnetic waves are transmitted to the underground through a transmitting antenna, the electromagnetic waves reflected back to the ground are received through a receiving antenna, the electromagnetic waves are reflected when encountering interface surfaces with electrical property differences during propagation in the underground medium, and the spatial position, the structure, the form and the burial depth of the underground medium are deduced according to the characteristics of the received electromagnetic waves such as the waveform, the amplitude intensity and the time change. The life detection radar is based on the principle of an ultra-wideband radar, and achieves the purposes of detecting, searching and rescuing survivors buried in ruins by using the human body micro-motion Doppler echo effect carried by nanosecond electromagnetic pulses. It can search the life information quickly and efficiently, and bring the hope of life to the trapped people. The life detection radar based on the ultra-wideband technology has the advantages of low radiation power, no influence on a human body, low system power consumption, convenient power supply, portability, strong capability of penetrating through an obstacle, capability of detecting life information of the human body after the obstacle, and strong anti-multipath and narrowband interference capability.
The typical ultra-wideband radar system consists of a transmitter, a receiver, a transmitting antenna, a receiving antenna, a radar master control system and a data acquisition, processing and display system. The ultra-wideband signal generated by the transmitter is converted into electromagnetic wave radiation by the transmitting antenna, and part of the electromagnetic wave energy reflected and scattered by the target is captured by the receiving antenna and converted into a voltage signal for rear-end processing. Due to the difference of the distance and the scattering characteristic of the target, the amplitude and the time delay of the echo signals corresponding to different targets received by the receiver also have difference, and the target can be detected by identifying the difference through processing the received data. However, since the clock pulses of the transmitter and the receiver are high-frequency pulses, it is very difficult to control the synchronization of the clock pulses of the transmitter and the receiver.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a difference frequency-delay type receiving and transmitting clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device.
In order to solve the technical problems, the invention adopts the technical scheme that:
a difference frequency-delay type transceiving clock synchronization method for an ultra-wideband pulse radar receiving device comprises the following implementation steps:
1) dividing the frequency of the clock 1 by an N frequency divider to obtain a clock 3, and dividing the frequency of the clock 2 by the N frequency divider to obtain a clock 4; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero;
2) respectively buffering the clocks 3 and then outputting to control the transmitter to transmit pulses; and buffering the clock 4 and outputting to control the receiver to receive the radar echo.
Optionally, the timing in step 1) is delayed by controlling the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 at zero, specifically, the phase of the clock 3 and the clock 4 is kept at zero every time the clock 3 or the clock 4 is delayed by t' = N/Δ f, where N is a division multiple of the frequency divider, and Δ f is a clock frequency difference between the clock 1 and the clock 2.
In addition, the invention also provides a difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving device, which comprises a transmitting clock circuit unit, a receiving clock circuit unit and a controller, wherein the transmitting clock circuit unit and the receiving clock circuit unit respectively comprise a clock source, a frequency divider and a buffer which are sequentially connected, at least one of the transmitting clock circuit unit and the receiving clock circuit unit is positioned between the frequency divider and the buffer and is connected with the time delay in series, and the control end of the time delay and the control end of the frequency divider are respectively connected with the controller.
Optionally, the clock source of the transmission clock circuit unit is a temperature compensated crystal oscillator.
Optionally, the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator, a control end of the voltage-controlled temperature-compensated crystal oscillator is connected to a digital module conversion controller, and a control end of the digital module conversion controller is connected to the control unit.
In addition, the invention also provides an ultra-wideband pulse radar receiving device, which comprises a clock synchronization circuit, a buffer, a transmitter and a receiver, wherein the clock synchronization circuit is the difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving device, the output end of the transmitting clock circuit unit is connected with the clock input end of the transmitter through the buffer, and the output end of the receiving clock circuit unit is connected with the clock input end of the receiver through the buffer.
Optionally, the receiver includes a receiving antenna, a low noise amplifier, a symmetric sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit, the receiving antenna is connected to one input end of the symmetric sampling gate pulse circuit through the low noise amplifier, the input end of the symmetric sampling gate pulse circuit is connected to the buffer, the output end of the symmetric sampling gate pulse circuit is connected to the other input end of the sample-and-hold circuit, and the output end of the sample-and-hold circuit outputs the received signal through the baseband signal filtering and amplifying circuit.
Optionally, the symmetrical sampling gate pulse circuit comprises a differential operational amplifier U 1 PNP type microwave triode Q with complementary broadband 1 And NPN type microwave triode Q 2 Resistance R 9 ～R 12 Resistance R L1 ～R L2 Short circuit line T 1 ～T 2 Diode D 2 ～D 4 And a capacitor C 5 ～C 8 Differential operational amplifier U 1 At the input of a clock signal as a control signal V s Under the drive of the PNP type microwave triode Q, a pair of differential signals are generated at a non-inverting output end and an inverting output end and are respectively output to the PNP type microwave triode Q 1 And NPN type microwave triode Q 2 PNP type microwave triode Q 1 And NPN type microwave triode Q 2 The emitting electrodes of the two are mutually communicated, and the PNP type microwave triode Q 1 Collector through resistor R 9 PNP type microwave triode Q connected with negative power supply-Vcc 1 Is further passed through a capacitor C 5 Diode D in the forward direction 3 Capacitor C 7 Resistance R L1 Ground, diode D 3 Capacitor C 7 The intermediate contact between the two is passed through a short circuit line T 2 Ground, capacitor C 5 Diode D 3 Intermediate contact between them is through resistance R 11 NPN type microwave triode Q connected with negative power supply-Vcc 2 Collector through resistor R 10 Is connected with a positive power supply + Vcc and is also provided with an NPN type microwave triode Q 2 Is further passed through a capacitor C 6 Diode D in the reverse direction 4 Capacitor C 8 Resistance R L2 Ground, diode D 4 Capacitor C 8 The intermediate contact point between the two is connected with a short circuit line T 1 Ground, capacitor C 6 Diode D 4 The intermediate contact point therebetween passes through the resistor R 12 A capacitor C connected to the positive power supply + Vcc 6 Diode D 4 The intermediate junction between them also passing through a forward diode D 2 Connected to a capacitor C 5 Diode D 3 Intermediate junction between them.
Optionally, the sample-and-hold circuit comprises a diode bridge, a resistor Rs, a resistor R t1 And a resistor R t2 Diode D 21 Diode D 22 Capacitor C 21 Capacitor C 22 Short circuit line T 21 Short circuit line T 22 One of the diode bridgeOne bridge arm as one input end connected to the antenna via resistor Rs and the other bridge arm as the output end of the sample hold circuit, and the diode bridge and the input end connected to the antenna via resistor Rs are connected via resistor R t1 Resistance R t2 The positive unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit sequentially passes through the diode D 21 Capacitor C 21 The reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is sequentially connected with the anode of the diode bridge 22 Capacitor C 22 Connected to the cathode of a diode bridge, a diode D 21 Capacitor C 21 The intermediate contact between the two is passed through a short circuit line T 21 Ground, diode D 22 Capacitor C 22 The intermediate contact between the two is passed through a short circuit line T 22 And (4) grounding.
Compared with the prior art, the invention has the following advantages:
1. the invention divides the frequency of the clock 1 by the N frequency divider to obtain the clock 3, divides the frequency of the clock 2 by the N frequency divider to obtain the clock 4, divides the frequency of the clock to generate controllable frequency difference, and equivalently samples the input high-speed signal, thereby solving the bottleneck problem of time stepping between receiving and transmitting when a delayer is independently adopted, and being beneficial to improving the frequency of the signal received by a receiver.
2. The invention keeps the phase of the clock 3 and the clock 4 to be zero by controlling the clock 3 or the clock 4 to carry out time delay at regular time, thereby overcoming the defects of poor real-time performance, low signal refreshing rate and data redundancy of differential frequency type receiving.
Drawings
Fig. 1 is a flowchart illustrating a method for synchronizing a transmit/receive clock according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a transceiver clock synchronization apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a specific implementation of the transceiver clock synchronization apparatus according to the embodiment of the present invention.
Fig. 4 is a schematic diagram of a basic structure of an ultra-wideband pulse radar receiving device according to an embodiment of the present invention.
FIG. 5 is a schematic circuit diagram of a symmetrical sampling gate pulse circuit according to an embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a sample-and-hold circuit according to an embodiment of the present invention.
Fig. 7 shows the sampling result of the 1GHz sinusoidal signal in the embodiment of the present invention.
Fig. 8 shows the sampling result of the 5GHz sinusoidal signal in the embodiment of the present invention.
Fig. 9 is a 500ps short pulse signal in an embodiment of the present invention.
Fig. 10 shows the results of sampling a 500ps short pulse in an embodiment of the present invention.
Fig. 11 shows a-scan radar signals received by an ultra-wideband pulse radar in an embodiment of the invention.
Fig. 12 is a B-scan radar signal received by an ultra-wideband pulse radar in an embodiment of the invention.
Fig. 13 is a receiver conversion loss in an embodiment of the present invention.
Fig. 14 shows the power of the baseband signal output from the receiver in the embodiment of the present invention.
Detailed Description
As shown in fig. 1, the implementation steps of the difference frequency-delay type transceiving clock synchronization method for the ultra-wideband pulse radar receiving apparatus of this embodiment include:
1) dividing the frequency of the clock 1 by an N frequency divider to obtain a clock 3, and dividing the frequency of the clock 2 by the N frequency divider to obtain a clock 4; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero;
2) respectively buffering the clocks 3 and then outputting to control the transmitter to transmit pulses; and buffering the clock 4 and outputting to control the receiver to receive the radar echo.
Suppose clock 1 has a clock frequency f 0 + Δ f, clock 2 having a clock frequency f 0 And Δ f is the clock frequency difference between clock 1 and clock 2. If the clock 1 is directly adopted to control the transmitter to transmit pulses and the clock 2 controls the receiver to receive radar echoes, the time step length tau during sampling is as follows:
at this time, the time t required by the radar to obtain a piece of A-Scan data is as follows:
when f is 0 And when the frequency is 10MHz and the frequency is delta f =0.0001MHz, the time step is tau 1ps, and an A-Scan waveform is obtained every t =10 ms. Each waveform corresponds to a radar echo with an original time length of 100ns, and the maximum detection distance is about 15 m. However, since the clock pulses of the transmitter and the receiver are high-frequency pulses, it is very difficult to control the synchronization of the clock pulses of the transmitter and the receiver. In view of the above technical problems, in the present embodiment, a clock 3 is obtained by dividing a clock 1 by an N-divider, and a clock 4 is obtained by dividing a clock 2 by an N-divider, so that a controllable frequency difference can be generated between the clock 3 and the clock 4 by the frequency division, so as to perform equivalent sampling on an input high-speed signal. Assuming that the frequency divider is an N-frequency divider, the divided clock frequencies are respectively (f) 0 + Δ f)/N and f 0 and/N. If the clock is adopted to respectively control the radar transmitter and the receiver, the sampling time step length is N times of the original sampling time step length. The time required for the radar to obtain an A-Scan waveform is also N times the original time. The time length of each waveform corresponding to the original radar echo is also N times of the original time length. In order to improve the real-time performance of the radar and reduce redundant data, the time of each A-Scan waveform is shortened in a delay compensation mode by cascading a delay timer behind a frequency divider to delay the divided clock.
In this embodiment, in the step 1), delaying the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 at zero by controlling the clock 3 or the clock 4 specifically means that the phase of the clock 3 and the clock 4 is kept at zero every time t' = N/Δ f elapses by controlling the clock 3 or the clock 4 to delay, where N is a division multiple of the frequency divider, and Δ f is a clock frequency difference between the clock 1 and the clock 2.
The particular choice in this embodiment is to control the clock 3 delay to keep the phase of clock 3 and clock 4 at zero. The frequency of the clock 3 is (f) which is the clock obtained by dividing the frequency of the clock 1 0 + Δ f)/N; the clock obtained by dividing clock 2 is clock 4 with frequency f 0 At the time of/N. Every time the phases of the two clock signals of clock 3 and clock 4 are aligned once over time t' = N/Δ f: when the time t passes 1 If =1/Δ f, the phase of clock 3 advances relative to clock 4
Corresponding rising or falling edge time lead Δ t ═ 1/[ N (f) 0 +Δf 0 )]. At this time, the clock 3 is delayed by Δ t 1/[ N (f) by the programmable delay unit 0 +Δf 0 )]Then the phase difference between clock 3 and clock 4 will be zero. Similarly, when the time t passes N-1 When the phase of clock 3 is advanced relative to clock 4 by (N-1)/Δ f
Corresponding rising or falling edge time lead Δ t ═ N-1/[ N (f) 0 +Δf 0 )]. At this time, if the clock 3 is delayed by Δ t by the programmable delay unit (N-1)/[ N (f)/] 0 +Δf 0 )]Then the phase difference between clock 3 and clock 4 will be restored to zero. When the time t passes N When N/Δ f, clock 3 is delayed back to 0, and the phase difference between clock 3 and clock 4 will be zero. Thus, the delay compensation is performed on the clock 3, so that the phase alignment of the two clocks is performed by changing the elapsed time to 1/N of the previous time. Similarly, the length of each A-Scan radar signal waveform is reduced to 1/N, so that the defects of poor real-time performance, low signal refresh rate and data redundancy of differential frequency type receiving are overcome. The bottleneck of time stepping between reception and transmission can be solved by using a delayer alone.
As shown in fig. 2, the present embodiment further provides a difference frequency-delay type transceiving clock synchronization circuit for an ultra-wideband pulse radar receiving apparatus, including a transmitting clock circuit unit, a receiving clock circuit unit, and a controller, where the transmitting clock circuit unit and the receiving clock circuit unit both include a clock source, a frequency divider, and a buffer, which are connected in sequence, at least one of the transmitting clock circuit unit and the receiving clock circuit unit is located between the frequency divider and the buffer, and is connected in series with the delay, and a control end of the delay and a control end of the frequency divider are connected with the controller respectively.
As shown in fig. 3, the clock source of the transmission clock circuit unit is a temperature compensated crystal oscillator, in this embodiment, the output signal of the temperature compensated crystal oscillator is a HCMOS type square wave of 10MHz, and the frequency stability of the output signal is within ± 1 PPM.
As shown in fig. 3, the clock source of the receiving clock circuit unit is a voltage-controlled temperature compensation crystal oscillator, a control end of the voltage-controlled temperature compensation crystal oscillator is connected to a digital module conversion controller (DAC LTC2641), and a control end of the digital module conversion controller (DAC LTC2641) is connected to the control unit. When the control voltage is the central voltage, the output signal of the voltage-controlled temperature compensation crystal oscillator is a HCMOS type square wave of 10 MHz. The voltage-controlled temperature compensation crystal oscillator can generate a frequency deviation of +/-3 PPM to +/-15 PPM within the control voltage range of 0.1 multiplied by VDD to 0.9 multiplied by VDD. The control voltage of the VCOSC is provided by a digital block converter controller (DAC LTC 2641). And adjusting the output analog voltage of a digital module conversion controller (DAC LTC2641), so that the output signal of the voltage-controlled crystal oscillator generates-10 PPM frequency deviation and outputs an HCMOS type square wave with the frequency of 9.9999 MH.
As shown in fig. 3, in this embodiment, a CPLD chip with a model number of XC95144 is adopted, and functions of a controller and a frequency dividing unit are integrated at the same time, where the frequency dividing unit includes two frequency dividers for performing N-frequency division on an output clock of a temperature compensated crystal oscillator and an output clock of a voltage controlled temperature compensated crystal oscillator, respectively.
As shown in fig. 3, the delay unit in this embodiment adopts a DS1023-200 programmable delay unit, and the DS1023-200 programmable delay unit performs delay compensation on the output clock of the frequency divider under the control of the CPLD chip. The output clock after delay compensation is reversed by a Schmidt reverser and then respectively used as a control clock of a transmitter and a receiver to drive the transmitter and the receiver
As shown in fig. 3, the buffers of the transmit clock circuit unit and the receive clock circuit unit in this embodiment are implemented by a schmitt inverter with model number SN74 LVC-G14.
In addition, as shown in fig. 4, this embodiment further provides an ultra-wideband pulse radar receiving apparatus, which includes a clock synchronization circuit, a buffer, a transmitter, and a receiver, where the clock synchronization circuit is the difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving apparatus in this embodiment, an output end of the transmitting clock circuit unit is connected to a clock input end of the transmitter through the buffer, and an output end of the receiving clock circuit unit is connected to a clock input end of the receiver through the buffer.
The transmitter in this embodiment has the same structure as the conventional transmitter, and employs a nanosecond pulse generating circuit. On the basis, the embodiment also provides a circuit improvement of the receiver, which comprises a symmetrical sampling gate pulse circuit and a sample hold circuit. As shown in fig. 4, the receiver includes a receiving antenna, a low noise amplifier, a symmetric sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit, where the receiving antenna is connected to one input end of the symmetric sampling gate pulse circuit through the low noise amplifier, the input end of the symmetric sampling gate pulse circuit is connected to a buffer, the output end of the symmetric sampling gate pulse circuit is connected to the other input end of the sample-and-hold circuit, and the output end of the sample-and-hold circuit outputs a received signal through the baseband signal filtering and amplifying circuit.
As shown in FIG. 5, the symmetrical sampling gate pulse circuit includes a differential operational amplifier U 1 PNP type microwave triode Q with complementary broadband 1 And NPN type microwave triode Q 2 Resistance R 9 ～R 12 Resistance R L1 ～R L2 Short circuit line T 1 ～T 2 Diode D 2 ～D 4 And a capacitor C 5 ～C 8 Differential operational amplifier U 1 At the input of a clock signal as a control signal V s Under the drive of the PNP type microwave triode Q, a pair of differential signals are generated at a non-inverting output end and an inverting output end and are respectively output to the PNP type microwave triode Q 1 And NPN type microwave triode Q 2 PNP type microwave triode Q 1 And NPN type microwave triode Q 2 The emitting electrodes of the two are mutually communicated, and the PNP type microwave triode Q 1 Collector through resistor R 9 PNP type microwave triode Q connected with negative power supply-Vcc 1 Is further passed through a capacitor C 5 Diode D in the forward direction 3 Capacitor C 7 Resistance R L1 Ground, diode D 3 Capacitor C 7 The intermediate contact between the two is passed through a short circuit line T 2 Ground, capacitor C 5 Diode D 3 Intermediate contact between them is through resistance R 11 NPN type microwave triode Q connected with negative power supply-Vcc 2 Collector through resistor R 10 Is connected with a positive power supply + Vcc and is also provided with an NPN type microwave triode Q 2 Is further passed through a capacitor C 6 Diode D in the reverse direction 4 Capacitor C 8 Resistance R L2 Ground, diode D 4 Capacitor C 8 The intermediate contact between the two is passed through a short circuit line T 1 Ground, capacitor C 6 Diode D 4 Intermediate contact between them is through resistance R 12 A capacitor C connected to the positive power supply + Vcc 6 Diode D 4 The intermediate junction between them also passing through a forward diode D 2 Connected to a capacitor C 5 Diode D 3 Intermediate junction between them.
The symmetrical sampling gate pulse circuit can generate symmetrical narrow pulses (a pair of pulses with opposite positive and negative polarities). The generation process of the symmetrical pulse signal can be divided into generation of step signal, reverse conduction to reverse cut-off of step recovery diode, reverse cut-off of step diode, forward conduction of step diode, and Q of PNP type microwave triode 1 And NPN type microwave triode Q 2 The switching from on to off is performed in several stages. Differential operational amplifier U 1 In the control signal V s Generates a pair of differential signals at the in-phase output terminal and the inverted output terminal. When the control signal V s At the arrival of the rising edge of (2), at the differential operational amplifier U 1 The in-phase output end and the reverse output end respectively obtain a rising edge and a falling edge. Driven by the differential signal, PNP type microwave triode Q 1 And NPN type microwave triode Q 2 Meanwhile, the liquid crystal rapidly enters a saturation region from a cut-off region through an amplification region. Due to the symmetrical circuit structure, the PNP type microwave triode Q 1 Before the collector voltage is cut off by the triode, -V CC Rapidly jumping to 0, and NPN type microwave triode Q 2 Before the collector voltage is cut off by the triode CC Rapidly dropping to 0. Thereby forming a PNP type microwave triode Q 1 And NPN type microwave triode Q 2 The collector of (a) obtains two rapidly symmetrical differential step signals.
In PNP type microwave triode Q 1 And NPN type microwave triode Q 2 Before conduction, the capacitor C 5 、C 6 The voltages of the left polar plate to earth are respectively power voltage-V CC And + V CC The voltage to ground of the right plate is slightly lower and slightly higher than 0 respectively. When PNP type microwave triode Q 1 NPN type microwave triode Q 2 When simultaneously turned on, the capacitor C 5 And C 6 At the same time, the diode D starts to discharge through the discharge loop 2 By PNP type microwave triode Q 1 And NPN type microwave triode Q 2 Forward conduction before turn-off becomes reverse biased. Diode D 2 Is a step recovery diode, when diode D 2 The reverse bias does not cut off immediately, but completely after the storage time and the step time. From reverse bias to the end of the storage time, diode D 2 The impedance is small as when conducting in the forward direction. At this time, the capacitance C 5 And C 6 Mainly by PNP type microwave triode Q 1 NPN type microwave triode Q 2 Collector-emitter and diode D 3 The discharge circuit is configured to discharge. In the diode D 2 Storage period of (2), Q 1 、Q 2 The transition from the cut-off region to the saturation region is through the amplification region. At this time, PNP type microwave triode Q 1 NPN type microwave triode Q 2 And a diode D and equivalent impedance between the collector and emitter of 2 Is much larger than the equivalent impedance of diode D 2 The voltage division obtained at both ends is very small, diode D 3 、D 4 Can not be conducted in the forward direction, and the output signal is almost zero. In the step period, the diode D 3 The reverse conduction is quickly changed into the reverse cut-off, and the impedance is quickly changed from small to large. At this time, for the capacitor C 5 、C 6 To say two polesThe plate still stores a large amount of charge and the discharge continues with diode D 3 Of the diode D 3 The reverse voltage across the terminals rises rapidly. When the voltage is higher than the diode D 3 And D 4 At the on-voltage of diode D 3 、D 4 Are conducted and pass through the diode D respectively 3 And D 4 And outputting a voltage signal which rapidly rises and rapidly falls. The rise and fall times of which are mainly determined by the diode D 3 Is determined. If a step recovery diode with the step time of less than 100ps is adopted, the rising edge or the falling edge of the output voltage signal can reach less than 100 ps. When diode D 2 If PNP type microwave triode Q is completely cut off 1 NPN type microwave triode Q 2 After deep saturation, the amplitude of the output voltage reaches a maximum. Due to the symmetrical circuit structure, the output signal amplitude is also symmetrical. When diode D 3 After complete cut-off, the capacitance C 5 And C 6 Mainly by PNP type microwave triode Q 1 NPN type microwave triode Q 2 Collector-emitter, diode D 3 、D 4 And a short circuit line T 1 Short circuit line T 2 Capacitor C 7 Capacitor C 8 Resistance R L1 Resistance R L2 The formed discharge loop discharges, and the discharge current of the capacitor decreases exponentially. At this time, via the diode D 3 The output voltage decreases exponentially through a diode D 4 The output voltage rises exponentially. When diode D 2 Voltage across lower than diode D 3 And a diode D 4 At the on-voltage of diode D 3 And a diode D 4 And when the circuit is cut off, the output signal is 0. Thus, respectively at D at the same time 3 The cathode of (2) obtains a positive pulse signal at D 4 The anode of (2) gets a negative pulse signal. Positive pulse signal to short circuit line T 1 And a resistance R L1 Two-way propagation, negative pulse signal to short circuit line T 2 And a resistance R L1 Two directions of propagation. The signal propagating in the direction of the short-circuit line is reflected at the short-circuit and then is reversed and then also flows to the resistor R L1 And a resistance R L2 The combination of the directional propagation and the previously arriving signalA monocycle pulse signal.
As shown in FIG. 6, the sample-and-hold circuit includes a diode bridge, a resistor Rs, and a resistor R t1 Resistance R t2 Diode D 21 Diode D 22 Capacitor C 21 Capacitor C 22 Short circuit line T 21 Short circuit line T 22 One bridge arm of the diode bridge is used as an input end and connected with the antenna through a resistor Rs, the other bridge arm is used as an output end of the sample hold circuit, and the input ends of the diode bridge and the antenna connected through the resistor Rs are respectively connected with the output end of the sample hold circuit through a resistor R t1 Resistance R t2 The output end of the positive unipolar pulse signal output by the symmetrical sampling gate pulse circuit is grounded and sequentially passes through the diode D 21 Capacitor C 21 The reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is connected with the anode of the diode bridge and sequentially passes through the diode D 22 Capacitor C 22 Connected to the cathode of a diode bridge, a diode D 21 Capacitor C 21 The intermediate contact between the two is passed through a short circuit line T 21 Ground, diode D 22 Capacitor C 22 The intermediate contact between the two is passed through a short circuit line T 22 And (4) grounding. Symmetrical unipolar pulse signals generated by the symmetrical pulse generating circuit pass through the Schottky diode D 21 And D 22 The rectified pulse width is further narrowed and the tail is reduced. Rectified pulse signal is sent to a capacitor C 21 、C 22 And short-circuit lines. To the capacitor C 21 、C 22 The directionally propagated pulse signal rapidly charges the left plate of the capacitor, D 21 、D 22 And (4) rapidly stopping. Capacitor C 21 、C 22 Combining with diode bridge to form high-pass filter, making the diode bridge quickly conduct by pulse signal coupled by capacitor, and making the sampled signal pass through diode bridge and capacitor C s Charging, and obtaining a signal which is proportional to the signal amplitude at the output end. The pulse signal propagating towards the short circuit line direction generates total reflection and phase inversion at a short position, the pulse signal returns along the transmission line after reflection and is superposed with the original pulse signal to generate a monocycle signal, the pulse width of the front half part of the monocycle signal is narrowed relative to the original unipolar pulse width, thus the pulse width of the front half part of the monocycle signal is narrowed, and the pulse width of the front half part of the monocycle signal is shortened relative to the original unipolar pulse widthThe sampling aperture is reduced during sampling, which is beneficial to improving the resolution of the sampling signal and the bandwidth of the receiver. Because the positive and negative pulses of the capacitor are respectively opposite to the capacitor C 21 And C 22 Charging, C 21 The voltage of the right plate to the left plate is rapidly reduced, C 22 The voltage of the right plate to the left plate rises rapidly when C 21 Right polar plate pair C 22 When the voltage of the right polar plate is lower than the conduction voltage of the diode bridge, the two bridge tube bridges are cut off, and the sampling of the signal is stopped. In the latter half period of the monocycle pulse signal, the diode bridge is in a reverse bias state. When there is no pulse signal, the capacitor C is coupled by the previous pulse 21 、C 22 The accumulated charges can not be released due to the cut-off of the diode bridge during charging, so that the diode bridge is also in a cut-off state, and the receiving runaway caused by the overlarge amplitude of the sampled signal when no direct current reverse bias voltage exists is avoided. And integrating, holding and amplifying the sampling signal to obtain a receiving signal.
In the embodiment, the ultra-wideband pulse radar receiving device is manufactured by using a TP2 microwave circuit board (dielectric constant is 10.2, thickness is 0.05in, and loss angle is 0.0023) produced by Jiangsu Taixing microwave material factory. The diode bridge adopts HSMS286P manufactured by Agilent company; the differential amplifier was a THS4502 manufactured by TI, and the amplifier for amplifying the sampled signal was a TL071 operational amplifier manufactured by TI.
The performance of the receiver in the ultra-wideband pulse radar receiving apparatus in this embodiment will be tested using a difference frequency receiving scheme. Assume that the clock frequency (transmitter control clock) of the received signal is f 1 The clock frequency sampled by the receiver (receiver control clock) is f 2 ，f 1 And f 2 The following relationship is satisfied: f. of 1 ＝N 1 f 2 +Δf
In the above formula, N 1 Is an integer, Δ f is the clock frequency f 1 Clock frequency f 2 A frequency offset in between. Similar to continuous wave mixing, the frequency of the down-converted signal obtained after sample and hold is Δ f.
FIG. 7 shows the clock frequency f in this embodiment 1 Sine signal of power 0dBm at 1GHz, clock frequency f 2 The receiver outputs a signal waveform when the frequency is 0.9999 MHz. FIG. 8 shows the clock frequency f in this embodiment 1 Sinusoidal signal with power of 0dBm at 5GHz, clock frequency f 2 The receiver outputs a signal waveform when the frequency is 0.9999 MHz. FIG. 9 shows the clock frequency f in this embodiment 1 5 MHz. FIG. 10 shows the clock frequency f in this embodiment 2 The receiver outputs a signal waveform when the signal of figure 7 is sampled at 4.9999 MHz. FIG. 11 shows the clock frequency f in this embodiment 1 5MHz, clock frequency f 2 The receiver samples the a-scan radar signal obtained from the received antenna signal at 4.9999 MHz. Fig. 12 shows a corresponding B-scan radar signal in this embodiment. Fig. 13 shows the measured and calculated receiver conversion loss in this embodiment. FIG. 14 shows the clock frequency f in this embodiment 1 And when the frequency is 2GHz, the power of the baseband signal output by the receiver corresponds to the power of the sampled signal. As can be seen from fig. 7 to 14, in the receiving apparatus of the ultra-wideband pulse radar in this embodiment, the receiver can effectively receive an input high-speed signal, a bottleneck problem of time stepping between receiving and transmitting when a delay unit is separately used can be solved, and a frequency range of the received signal is wide.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (6)
1. A difference frequency-delay type transceiving clock synchronization method for an ultra-wideband pulse radar receiving device is characterized by comprising the following implementation steps:
1) dividing the frequency of the clock 1 by an N frequency divider to obtain a clock 3, and dividing the frequency of the clock 2 by the N frequency divider to obtain a clock 4; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero;
2) respectively buffering the clocks 3 and then outputting to control the transmitter to transmit pulses; buffering the clock 4 and outputting to control a receiver to receive radar echo;
the step 1) of delaying the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 to zero specifically means that each time passest′=N/ΔfControlling clock 3 or clock 4 to delay to keep the phase of clock 3 and clock 4 at zero, whereinNIs the division multiple, Δ, of the frequency dividerfThe clock frequency difference between clock 1 and clock 2.
2. A difference frequency-delay type transceiving clock synchronizing circuit for an ultra-wideband pulse radar receiving device based on the difference frequency-delay type transceiving clock synchronizing method for the ultra-wideband pulse radar receiving device of claim 1, comprising a transmitting clock circuit unit, a receiving clock circuit unit and a controller, wherein the transmitting clock circuit unit and the receiving clock circuit unit respectively comprise a clock source, a frequency divider and a buffer which are sequentially connected, at least one of the transmitting clock circuit unit and the receiving clock circuit unit is arranged between the frequency divider and the buffer and is serially connected with the time delay, and a control end of the time delay and a control end of the frequency divider are respectively connected with the controller.
3. The difference frequency-delay type transceiving clock synchronization circuit for an ultra-wideband pulse radar receiving apparatus according to claim 2, wherein a clock source of the transmitting clock circuit unit is a temperature compensated crystal oscillator.
4. The difference frequency-delay type transceiving clock synchronizing circuit for an ultra-wideband pulse radar receiving device according to claim 2, wherein the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator, a control end of the voltage-controlled temperature-compensated crystal oscillator is connected to a digital module conversion controller, and a control end of the digital module conversion controller is connected to the control unit.
5. Ultra-wideband pulse radar receiverThe device comprises a clock synchronization circuit, a transmitter and a receiver, and is characterized in that the clock synchronization circuit is the difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving device as claimed in any one of claims 2 to 4, the output end of the transmitting clock circuit unit is connected with the clock input end of the transmitter, the output end of the receiving clock circuit unit is connected with the clock input end of the receiver, the receiver comprises a receiving antenna, a low noise amplifier, a symmetrical sampling gate pulse circuit, a sampling holding circuit and a baseband signal filtering amplifying circuit, the receiving antenna is connected with one input end of the symmetrical sampling gate pulse circuit through the low noise amplifier, the input end of the symmetrical sampling gate pulse circuit is connected with a buffer, and the output end of the symmetrical sampling gate pulse circuit is connected with the other input end of the sampling holding circuit, the output end of the sample hold circuit outputs the received signal through the baseband signal filtering and amplifying circuit, and the symmetrical sampling gate pulse circuit comprises a differential operational amplifier U 1 PNP type microwave triode Q with complementary broadband 1 And NPN type microwave triode Q 2 Resistance R 9 ～R 12 Resistance R L1 ～R L2 Short circuit line T 1 ～T 2 Diode D 2 ～D 4 And a capacitor C 5 ～C 8 Differential operational amplifier U 1 Under the drive of the input clock signal as a control signal Vs, a pair of differential signals are generated at a non-inverting output end and an inverting output end and are respectively output to a PNP type microwave triode Q 1 And NPN type microwave triode Q 2 PNP type microwave triode Q 1 And NPN type microwave triode Q 2 The emitting electrodes of the two are mutually communicated, and the PNP type microwave triode Q 1 Collector through resistor R 9 PNP type microwave triode Q connected with negative power supply-Vcc 1 Is further passed through a capacitor C 5 Diode D in the forward direction 3 Capacitor C 7 Resistance R L1 Ground, diode D 3 Capacitor C 7 The intermediate contact between the two is passed through a short circuit line T 2 Ground, capacitor C 5 Diode D 3 Intermediate contact between them is through resistance R 11 And negative power-Vcc phaseEven, NPN type microwave triode Q 2 Collector through resistor R 10 Is connected with a positive power supply + Vcc and is also provided with an NPN type microwave triode Q 2 Is further passed through a capacitor C 6 Diode D in the reverse direction 4 Capacitor C 8 Resistance R L2 Ground, diode D 4 Capacitor C 8 The intermediate contact between the two is passed through a short circuit line T 1 Ground, capacitor C 6 Diode D 4 Intermediate contact between them is through resistance R 12 A capacitor C connected to the positive power supply + Vcc 6 Diode D 4 The intermediate junction between them also passing through a forward diode D 2 Connected to a capacitor C 5 Diode D 3 Intermediate junction between them.
6. The UWB pulse radar receiver of claim 5 wherein the sample-and-hold circuit comprises a diode bridge, a resistor Rs, a resistor R t1 Resistance R t2 Diode D 21 Diode D 22 Capacitor C 21 Capacitor C 22 Short circuit line T 21 Short circuit line T 22 One bridge arm of the diode bridge is used as an input end and connected with the antenna through a resistor Rs, the other bridge arm of the diode bridge is used as an output end of the sample hold circuit, and the input ends of the diode bridge and the antenna connected through the resistor Rs are respectively connected through a resistor R t1 Resistance R t2 The positive unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit sequentially passes through the diode D 21 Capacitor C 21 The reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is sequentially connected with the anode of the diode bridge 22 Capacitor C 22 Connected to the cathode of the diode bridge, diode D 21 Capacitor C 21 The intermediate contact between the two is passed through a short circuit line T 21 Ground, diode D 22 Capacitor C 22 The intermediate contact between the two is passed through a short circuit line T 22 And is grounded.
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