CN111413677B - Difference frequency-delay type transceiver clock synchronization method, circuit and ultra-wideband pulse radar receiving device - Google Patents

Abstract

The invention discloses a difference frequency-delay type receiving and sending clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device, wherein the method comprises the steps of obtaining a clock 3 by aiming at clock 1 frequency division and obtaining a clock 4 by aiming at clock 2 frequency division; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero; buffering the clock 3 and outputting to control the transmitter to transmit pulses; buffering the clock 4 and outputting to control a receiver to receive radar echo; the circuit comprises a transmitting clock circuit unit, a receiving clock circuit unit and a controller, wherein the transmitting clock circuit unit and the receiving clock circuit unit respectively comprise a clock source, a frequency divider and a buffer which are sequentially connected. The invention can solve the bottleneck problem of time stepping between receiving and transmitting when a delayer is independently adopted, is beneficial to improving the frequency of the receiver for receiving signals, and overcomes the defects of poor real-time performance, low signal refresh rate and data redundancy of differential frequency type receiving.

Description

Difference frequency-delay type transceiver clock synchronization method, circuit and ultra-wideband pulse radar receiving device

technical field

The invention belongs to the technical field of ultra-wideband pulse receiving, and in particular relates to a difference frequency-delay type transceiver clock synchronization method, circuit and ultra-wideband pulse radar receiving device.

Background technique

UWB radar has attracted increasing attention in military, commercial, environmental protection and other fields due to its high range resolution, strong penetration, low interception rate and strong anti-jamming. Since the 1990s, with the development of broadband microwave devices and the enhancement of software algorithm signal processing capabilities, the performance of UWB radar has reached a high level. The ultra-wideband synthetic aperture radar in Sweden, the United States, Italy, Russia and other countries has achieved many flight experiments and entered the stage of practical application. Among commercial ultra-wideband radars, ultra-wideband through-wall radar, ground penetrating radar, and life detection radar have broad application prospects. Through-wall radar is an ultra-wideband pulsed radar, which is mainly used in military and public security fields such as anti-terrorism struggle, disaster rescue, and urban street fighting. By transmitting ultra-high frequency radar pulses and receiving echo signals, through-wall radar can penetrate doors, brick walls, slate and concrete walls, fully cover the interior space, and quickly estimate the situation in the room to obtain hidden Precise location information of unknown human and moving objects. Ground Penetrating Radar (Ground Penetrating Radar) is also known as ground penetrating radar and geological radar. It is a non-destructive detection method that uses radio waves with a frequency between 106-109Hz to determine the distribution of underground media. The ground penetrating radar method is to transmit high-frequency electromagnetic waves to the ground through the transmitting antenna, and receive the electromagnetic waves reflected back to the ground through the receiving antenna. When the electromagnetic waves are propagated in the underground medium, they will be reflected when they encounter an interface with electrical differences. According to the received electromagnetic waves The characteristics of the waveform, amplitude intensity and time change of the subsurface infer the spatial location, structure, morphology and burial depth of the subsurface medium. Life detection radar is based on the principle of ultra-wideband radar, using the Doppler echo effect of human fretting carried by nanosecond electromagnetic pulses to achieve the purpose of detection and search and rescue of survivors buried in the ruins. It can quickly and efficiently search for life information and bring life hope to the trapped people. The life detection radar based on ultra-wideband technology has low radiation power, no impact on the human body, low system power consumption, convenient power supply, easy portability, strong ability to penetrate obstacles, can detect human life information behind obstacles, anti-multipath and The advantage of strong narrowband interference capability.

A typical UWB radar system consists of transmitter, receiver, transmitting antenna, receiving antenna, radar main control system and data acquisition, processing and display system. The ultra-wideband signal generated by the transmitter is converted into electromagnetic waves and radiated by the transmitting antenna. Part of the electromagnetic wave energy reflected and scattered by the target is captured by the receiving antenna and converted into a voltage signal for back-end processing. Due to the differences in the distance and scattering characteristics of the targets, the amplitude and delay of the echo signals received by the receiver corresponding to different targets will also be different. By processing the received data and identifying these differences, the target can be detected. However, since the clock pulses of the transmitter and the receiver are high-frequency pulses, it is very difficult to control the synchronization of the clock pulses of the transmitter and the receiver.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention: in view of the above-mentioned problems of the prior art, a difference frequency-delay type transceiver clock synchronization method, circuit and ultra-wideband pulse radar receiving device are provided. Controlling the frequency difference, implementing equivalent sampling for the input high-speed signal, can solve the time step bottleneck problem between reception and transmission when the delay device is used alone, and can help to increase the frequency of the receiver's receiving signal, overcoming the difference frequency It has the disadvantages of poor real-time reception, low signal refresh rate and data redundancy.

In order to solve the above-mentioned technical problems, the technical scheme adopted in the present invention is:

A difference frequency-delay type transceiver clock synchronization method for an ultra-wideband pulse radar receiving device, the implementation steps include:

1) The clock 1 is divided by the N frequency divider to obtain the clock 3, and the clock 2 is divided by the N frequency divider to obtain the clock 4; the timing is delayed by controlling the clock 3 or the clock 4. phase remains at zero;

2) The clock 3 is respectively buffered and output to control the transmitter to transmit pulses; the clock 4 is buffered and output to control the receiver to receive radar echoes.

Optionally, in step 1), the timing is delayed by controlling the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 at zero. Specifically, it means that every elapsed time t'=N/Δf controls the clock 3 or the clock 4 to delay. Keep the phase of clock 3 and clock 4 at zero, where N is the frequency division multiple of the frequency divider, and Δf is the clock frequency difference between clock 1 and clock 2.

In addition, the present invention also provides a difference frequency-delay type transceiver clock synchronization circuit for an ultra-wideband pulse radar receiving device, comprising a transmitting clock circuit unit, a receiving clock circuit unit and a controller, the transmitting clock circuit unit, the receiving clock circuit unit, the receiving clock circuit unit and the controller. The clock circuit units all include a clock source, a frequency divider, and a buffer that are connected in sequence, and at least one of the transmit clock circuit unit and the receive clock circuit unit is located between the frequency divider and the buffer, and a delay is connected in series , the control end of the delay device and the control end of the frequency divider are respectively connected with the controller.

Optionally, the clock source of the transmit clock circuit unit is a temperature compensated crystal oscillator.

Optionally, the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator, and the control end of the voltage-controlled temperature-compensated crystal oscillator is connected with a digital module conversion controller, and the digital module conversion controller is The control terminal is connected with the control unit.

In addition, the present invention also provides an ultra-wideband pulse radar receiving device, comprising a clock synchronization circuit, a buffer, a transmitter and a receiver, wherein the clock synchronization circuit is the aforementioned difference frequency-delay for the ultra-wideband pulse radar receiving device The output end of the transmit clock circuit unit is connected to the clock input end of the transmitter through a buffer, and the output end of the receive clock circuit unit is connected to the clock input end of the receiver through a buffer.

Optionally, the receiver includes a receiving antenna, a low-noise amplifier, a symmetrical sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit, and the receiving antenna passes through one input end of the low-noise amplifier and the symmetrical sampling gate pulse circuit. The input end of the symmetrical sampling gate pulse circuit is connected to the buffer, and the output end is connected to another input end of the sample and hold circuit. The output end of the sample and hold circuit outputs the received signal through the baseband signal filtering and amplifying circuit.

Optionally, the symmetrical sampling gate pulse circuit includes a differential operational amplifier U ₁ , complementary broadband PNP microwave triode Q ₁ and NPN microwave triode Q ₂ , resistors R ₉ ˜R ₁₂ , resistors R _{L1 ˜R L2} , short Routes T1 _- T2, diodes D2 _- D4 and capacitors _{C5 -} C8, the differential operational amplifier U1 generates _a non _- inverting output terminal and an _inverting output terminal driven by the input clock signal as the control signal _Vs. The differential signals are output to the PNP microwave triode Q ₁ and the NPN microwave triode Q ₂ respectively. The emitters of the PNP microwave triode Q ₁ and the NPN microwave triode Q ₂ are connected to each other, and the collector of the PNP microwave triode Q ₁ is connected to each other. The electrode is connected to the negative power supply -Vcc through the resistor R ₉ , and the collector of the PNP microwave triode Q ₁ is also connected to the ground through the capacitor C ₅ , the forward diode D ₃ , the capacitor C ₇ , the resistor R _L1 in turn, the diode D ₃ , the capacitor _The intermediate point between C7 is grounded through the short _- circuit line T2, the intermediate point between the capacitor _C5 and the diode _D3 is connected to the negative power supply _-Vcc through the resistor R11, and the collector of the NPN microwave triode _Q2 is connected through the resistor _R10 It is connected to the positive power supply +Vcc, and the collector of the NPN microwave triode Q ₂ is also grounded through the capacitor C ₆ , the reverse diode D ₄ , the capacitor C ₈ , and the resistor R _L2 in turn, and the middle between the diode D ₄ and the capacitor C ₈ is connected to the ground. _The contact is grounded through the short _- circuit line T1, the intermediate point between the capacitor _C6 and the diode D4 is connected to the positive power supply ₊ Vcc through the resistor _R12 , and the intermediate point between the capacitor _C6 and the diode D4 also passes through the forward diode _D2 Connect to the intermediate junction between capacitor _C5 and diode _D3 .

Optionally, the sample-and-hold circuit includes a diode bridge, a resistor Rs, a resistor R _t1 , a resistor R _t2 , a diode D ₂₁ , a diode D ₂₂ , a capacitor C ₂₁ , a capacitor C ₂₂ , a short-circuit line T ₂₁ , and a short-circuit line T ₂₂ , One bridge arm of the diode bridge is used as an input end and is connected to the antenna through the resistor Rs, and the other bridge arm is used as the output end of the sample-and-hold circuit. _t1 , the resistance R _t2 is grounded, the output terminal of the forward unipolar pulse signal output by the symmetrical sampling gate pulse circuit is connected to the positive pole of the diode bridge through the diode D ₂₁ , the capacitor C ₂₁ in turn, and the output terminal of the symmetrical sampling gate pulse circuit is connected. The output terminal of the reverse unipolar pulse signal is connected to the cathode of the diode bridge through the diode D ₂₂ and the capacitor C ₂₂ in turn. The intermediate point between the diode D ₂₁ and the capacitor C ₂₁ is grounded through the short-circuit line T _{21 .} The intermediate point between ₂₂ is grounded by a short-circuit line T ₂₂ .

Compared with the prior art, the present invention has the following advantages:

1. In the present invention, the clock 1 is divided by the N frequency divider to obtain the clock 3, and the clock 2 is divided by the N frequency divider to obtain the clock 4. The purpose of the clock frequency division is to generate a controllable frequency difference, and the input high-speed The signal implements equivalent sampling, which can solve the time step bottleneck problem between reception and transmission when the delay device is used alone, and can help to increase the frequency of the signal received by the receiver.

2. The present invention maintains the phase of clock 3 and clock 4 to be zero by controlling clock 3 or clock 4 to delay, thereby overcoming the disadvantages of poor real-time performance, low signal refresh rate and data redundancy in differential frequency reception.

Description of drawings

FIG. 1 is a schematic flowchart of a method for synchronizing sending and receiving clocks according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a principle structure of a transceiver clock synchronization apparatus according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a specific implementation of a transceiver clock synchronization apparatus according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a basic structure of an ultra-wideband pulse radar receiving apparatus in an embodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit principle of a symmetrical sampling gate pulse circuit in an embodiment of the present invention.

FIG. 6 is a schematic diagram of a circuit principle of a sample-and-hold circuit in an embodiment of the present invention.

FIG. 7 is a sampling result of a 1 GHz sinusoidal signal in an embodiment of the present invention.

FIG. 8 is a sampling result of a 5 GHz sinusoidal signal in an embodiment of the present invention.

FIG. 9 is a 500ps short pulse signal in an embodiment of the present invention.

FIG. 10 is a sampling result of a 500ps short pulse in an embodiment of the present invention.

FIG. 11 is an A-scan radar signal received by the ultra-wideband pulsed radar in the embodiment of the present invention.

FIG. 12 is a B-scan radar signal received by the ultra-wideband pulse radar in the embodiment of the present invention.

FIG. 13 is a receiver conversion loss in an embodiment of the present invention.

FIG. 14 is the baseband signal power output by the receiver in the embodiment of the present invention.

Detailed ways

As shown in FIG. 1 , the implementation steps of the difference frequency-delay type transceiver clock synchronization method for an ultra-wideband pulse radar receiving device in this embodiment include:

1) The clock 1 is divided by the N frequency divider to obtain the clock 3, and the clock 2 is divided by the N frequency divider to obtain the clock 4; the timing is delayed by controlling the clock 3 or the clock 4. phase remains at zero;

2) The clock 3 is respectively buffered and output to control the transmitter to transmit pulses; the clock 4 is buffered and output to control the receiver to receive radar echoes.

Assume that the clock frequency of clock 1 is f ₀ +Δf, the clock frequency of clock 2 is f ₀ , and Δf is the clock frequency difference between clock 1 and clock 2. If clock 1 is directly used to control the transmitter to transmit pulses, and clock 2 is used to control the receiver to receive radar echoes, the time step τ during sampling is:

At this time, the time t required for the radar to obtain an A-Scan data is:

When f ₀ =10MHz, Δf=0.0001MHz, the time step is τ=1ps, and an A-Scan waveform is obtained every t=10ms. Each waveform corresponds to a radar echo with an original time length of 100ns, corresponding to a maximum detection distance of about 15m. However, since the clock pulses of the transmitter and the receiver are high-frequency pulses, it is very difficult to control the synchronization of the clock pulses of the transmitter and the receiver. In view of the above technical problems, in this embodiment, the clock 1 is divided by the N frequency divider to obtain the clock 3, and the clock 2 is divided by the N frequency divider to obtain the clock 4. By dividing the frequency, the clock 3 and the clock 4 can be divided. A controllable frequency difference is generated between the two to facilitate equivalent sampling of the input high-speed signal. Assuming that the frequency divider is an N frequency divider, the divided clock frequencies are (f ₀ +Δf)/N and f ₀ /N, respectively. If this clock is used to control the radar transmitter and receiver respectively, the sampling time step is N times the original. At this time, the time required for the radar to obtain an A-Scan waveform also becomes N times the original. The time length of each waveform corresponding to the original radar echo is also N times the original. In order to improve the real-time performance of the radar and reduce redundant data, the time of each A-Scan waveform is shortened by means of delay compensation by cascading delayers after the frequency divider to delay the frequency-divided clock.

In this embodiment, the timing in step 1) is delayed by controlling the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 at zero. The delay keeps the phases of clock 3 and clock 4 at zero, where N is the division multiple of the frequency divider and Δf is the clock frequency difference between clock 1 and clock 2.

对应上升沿或下降沿时间超前Δt＝1/[N(f₀+Δf₀)]。此时，若通过可编程延时器使时钟3延时Δt＝1/[N(f₀+Δf₀)]，则时钟3与时钟4的相位差将为零。同理，当历经时间t_N-1＝(N-1)/Δf时，时钟3相对时钟4的相位超前

对应上升沿或下降沿时间超前Δt＝(N-1)/[N(f₀+Δf₀)]。此时，若通过可编程延时器使时钟3延时Δt＝(N-1)/[N(f₀+Δf₀)]，则时钟3与时钟4的相位差将恢复为零。当历经时间t_N＝N/Δf时，使时钟3延时恢复为0，这时时钟3与时钟4的相位差将同样为零。这样，通过对时钟3进行延时补偿，使原来两时钟相位对齐历经时间变为以前的1/N。同样，每道A-Scan雷达信号波形的长度也降为原来的1/N，从而克服了差频式接收实时性差、信号刷新率低及数据冗余的弊端。同时单独采用延时器时接收与发射之间的时间步进瓶颈可以得到解决。In this embodiment, the specific choice is to control the delay of clock 3 to keep the phase of clock 3 and clock 4 at zero. Let the clock obtained by dividing the clock by 1 be the frequency of the clock 3 as (f ₀ +Δf)/N; the clock obtained by dividing the clock by 2 is the clock 4, and its frequency is f ₀ /N. When the phases of the two clock signals of clock 3 and clock 4 are aligned once every elapsed time t'=N/Δf: when the elapsed time t ₁ =1/Δf, the phase of clock 3 relative to clock 4 is advanced

The corresponding rising edge or falling edge time leads by Δt=1/[N(f ₀ +Δf ₀ )]. At this time, if clock 3 is delayed by Δt=1/[N(f ₀ +Δf ₀ )] through a programmable delay device, the phase difference between clock 3 and clock 4 will be zero. Similarly, when the elapsed time t _N-1 =(N-1)/Δf, the phase of clock 3 relative to clock 4 leads

The corresponding rising edge or falling edge time leads Δt=(N-1)/[N(f ₀ +Δf ₀ )]. At this time, if clock 3 is delayed by Δt=(N−1)/[N(f ₀ +Δf ₀ )] through a programmable delay device, the phase difference between clock 3 and clock 4 will return to zero. When the elapsed time t _N =N/Δf, the delay of clock 3 is restored to 0, and the phase difference between clock 3 and clock 4 will also be zero at this time. In this way, by performing delay compensation on clock 3, the original phase alignment elapsed time of the two clocks becomes 1/N of the previous one. Similarly, the length of each A-Scan radar signal waveform is also reduced to 1/N of the original, thus overcoming the disadvantages of poor real-time performance, low signal refresh rate and data redundancy in differential frequency reception. At the same time, the time step bottleneck between reception and transmission can be solved when the delay device is used alone.

As shown in FIG. 2 , this embodiment also provides a differential frequency-delay type transceiver clock synchronization circuit for an ultra-wideband pulse radar receiving device, including a transmit clock circuit unit, a receive clock circuit unit and a controller, and a transmit clock circuit The unit and the receiving clock circuit unit both include a clock source, a frequency divider, and a buffer that are connected in sequence. At least one of the transmitting clock circuit unit and the receiving clock circuit unit is located between the frequency divider and the buffer, and a delay is connected in series. The control end of the delayer and the control end of the frequency divider are respectively connected with the controller.

As shown in FIG. 3 , the clock source of the transmitting clock circuit unit is a temperature-compensated crystal oscillator. In this embodiment, the output signal of the temperature-compensated crystal oscillator is a 10MHz HCMOS type square wave, and the frequency stability of the output signal is within ±1PPM.

As shown in Figure 3, the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator, and the control end of the voltage-controlled temperature-compensated crystal oscillator is connected with a digital module conversion controller (DAC LTC2641), and the digital module conversion controller ( The control terminal of DACLTC2641) is connected with the control unit. When the control voltage is the center voltage, the output signal of the voltage-controlled temperature-compensated crystal oscillator is a 10MHz HCMOS type square wave. The voltage-controlled temperature-compensated crystal oscillator can generate a frequency deviation of ±3PPM-±15PPM in the control voltage range of 0.1×VDD-0.9×VDD. The control voltage of the voltage-controlled temperature-compensated crystal oscillator is provided by the digital module conversion controller (DAC LTC2641). Adjust the digital module conversion controller (DAC LTC2641) to output the analog voltage, so that the output signal of the voltage-controlled crystal oscillator produces a frequency offset of -10PPM, and the output frequency is HCMOS type square wave with a frequency of 9.9999MH.

As shown in Figure 3, the CPLD chip with the model XC95144 is used in this embodiment to integrate the functions of the controller and the frequency division unit at the same time. The clock and the output clock of the voltage-controlled temperature-compensated crystal oscillator are divided by N.

As shown in FIG. 3 , in this embodiment, the delay device adopts a DS1023-200 programmable delay device, and the DS1023-200 programmable delay device performs delay compensation on the output clock of the frequency divider under the control of the CPLD chip. The output clock after delay compensation is reversed by Schmitt inverter and used as transmitter and receiver control clock to drive transmitter and receiver respectively.

As shown in FIG. 3 , in this embodiment, the buffers of the transmitting clock circuit unit and the receiving clock circuit unit are implemented by a Schmitt inverter whose model is SN74LVC-G14.

In addition, as shown in FIG. 4 , this embodiment also provides an ultra-wideband pulse radar receiving device, including a clock synchronization circuit, a buffer, a transmitter and a receiver. The clock synchronization circuit is used for the ultra-wideband pulse radar in this embodiment. The difference frequency-delay type transceiver clock synchronization circuit of the receiving device, the output end of the transmitting clock circuit unit is connected with the clock input end of the transmitter through the buffer, and the output end of the receiving clock circuit unit is connected with the clock input end of the receiver through the buffer connected.

The transmitter in this embodiment has the same structure as the existing transmitter, and adopts a nanosecond pulse generating circuit. On this basis, this embodiment further provides a circuit improvement of the receiver, including a symmetrical sampling gate pulse circuit and a sampling and holding circuit. As shown in Figure 4, the receiver includes a receiving antenna, a low-noise amplifier, a symmetrical sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit. The receiving antenna is connected to one input end of the symmetrical sampling gate pulse circuit through a low-noise amplifier. The input end of the symmetrical sampling gate pulse circuit is connected to the buffer, and the output end is connected to the other input end of the sampling and holding circuit. The output end of the sampling and holding circuit outputs the received signal through the baseband signal filtering and amplifying circuit.

As shown in FIG. 5 , the symmetrical sampling gate pulse circuit includes a differential operational amplifier U ₁ , a complementary broadband PNP type microwave triode Q ₁ and an NPN type microwave triode Q ₂ , resistors R ₉ ˜R ₁₂ , resistors R _{L1 ˜R L2} , short Routes T1 _- T2, diodes D2 _- D4 and capacitors _{C5 -} C8, the differential operational amplifier U1 generates _a non _- inverting output terminal and an _inverting output terminal driven by the input clock signal as the control signal _Vs. The differential signals are output to the PNP microwave triode Q ₁ and the NPN microwave triode Q ₂ respectively. The emitters of the PNP microwave triode Q ₁ and the NPN microwave triode Q ₂ are connected to each other, and the collector of the PNP microwave triode Q ₁ is connected to each other. The electrode is connected to the negative power supply -Vcc through the resistor R ₉ , and the collector of the PNP microwave triode Q ₁ is also connected to the ground through the capacitor C ₅ , the forward diode D ₃ , the capacitor C ₇ , the resistor R _L1 in turn, the diode D ₃ , the capacitor _The intermediate point between C7 is grounded through the short _- circuit line T2, the intermediate point between the capacitor _C5 and the diode _D3 is connected to the negative power supply _-Vcc through the resistor R11, and the collector of the NPN microwave triode _Q2 is connected through the resistor _R10 It is connected to the positive power supply +Vcc, and the collector of the NPN microwave triode Q ₂ is also grounded through the capacitor C ₆ , the reverse diode D ₄ , the capacitor C ₈ , and the resistor R _L2 in turn, and the middle between the diode D ₄ and the capacitor C ₈ is connected to the ground. _The contact is grounded through the short _- circuit line T1, the intermediate point between the capacitor _C6 and the diode D4 is connected to the positive power supply ₊ Vcc through the resistor _R12 , and the intermediate point between the capacitor _C6 and the diode D4 also passes through the forward diode _D2 Connect to the intermediate junction between capacitor _C5 and diode _D3 .

The symmetrical sampling gate pulse circuit can generate symmetrical narrow pulses (a pair of pulses with opposite polarities). According to the dynamic process of the circuit, the generation process of the symmetrical pulse signal can be divided into step signal generation, step recovery diode reverse conduction to reverse cutoff, step diode reverse cutoff, step diode forward conduction, PNP type microwave triode. Q ₁ and NPN type microwave triode Q ₂ turn from on to off in several stages. The differential operational amplifier U1 is driven by the control signal _Vs to generate _a pair of differential signals at the non-inverting output terminal and the inverting output terminal. When the rising edge of the control signal V _s comes, the non-inverting output terminal and the reverse output terminal of the differential operational amplifier U ₁ will get a rising edge and a falling edge, respectively. Driven by the differential signal, the PNP microwave triode Q ₁ and the NPN microwave triode Q ₂ rapidly enter the saturation region from the cut-off region through the amplification region at the same time. Due to the symmetrical circuit structure, the collector voltage of the PNP microwave triode Q ₁ jumps rapidly from -V _CC before the transistor is turned off to 0, while the collector voltage of the NPN microwave triode Q ₂ jumps rapidly from the V _CC before the transistor is turned off. is 0. Therefore, two fast symmetrical differential step signals are obtained at the collectors of the PNP type microwave triode Q ₁ and the NPN type microwave triode Q ₂ .

Before the PNP type microwave triode Q ₁ and the NPN type microwave triode Q ₂ are turned on, the voltages of the left plates of capacitors C ₅ and C ₆ to the ground are the power supply voltages -V _CC and +V _CC respectively, and the voltages of the right plates to the ground are slightly below and slightly above 0. When the PNP type microwave triode Q ₁ and the NPN type microwave triode Q ₂ are turned on at the same time, the capacitors C ₅ and C ₆ start to discharge through the discharge circuit at the same time, and the diode D ₂ is cut off by the PNP type microwave triode Q ₁ and the NPN type microwave triode Q ₂ The previous forward conduction becomes reverse biased. The diode D ₂ is a step recovery diode, and when the diode D ₂ is reverse biased, it cannot be turned off immediately, but will be completely turned off after the storage time and the step time. From reverse bias to the end of the storage time, diode D2 has low _impedance as it does in forward conduction. At this time, the capacitors C ₅ and C ₆ are mainly discharged through the discharge circuit composed of the PNP type microwave triode Q ₁ , the collector-emitter of the NPN type microwave triode Q ₂ and the diode D ₃ . During the storage period _of diode D2, Q1 and _Q2 transition from the cut _- off region to the saturation region through the amplification region. At this time, the equivalent impedance between the collector and the emitter of the PNP microwave triode Q ₁ and the NPN microwave triode Q ₂ is much larger than the equivalent impedance of the diode D ₂ , and the voltage across the diode D ₂ is divided. Very small, diodes D ₃ and D ₄ cannot conduct forward, and the output signal is almost zero. During the step time period, the diode _D3 is rapidly turned from reverse conduction to reverse cutoff, and the impedance rapidly changes from very small to very large. At this time, for capacitors C ₅ and C ₆ , a large amount of charges are still stored on the two plates, and the discharge continues. With the rapid increase of the impedance of the diode D ₃ , the reverse voltage across the diode D ₃ rises rapidly. When the voltage is higher than the turn- _on voltage of the diodes _D3 and D4, the diodes _D3 and D4 are turned _on , respectively outputting voltage signals with fast rising and falling rapidly through the diodes _D3 and D4 _. Its rise and fall times are mainly determined by the step time of diode _D3 . If a step recovery diode with a step time of less than 100ps is used, the rising edge or falling edge of the output voltage signal can also be less than 100ps. When the diode D ₂ is completely cut off, if the PNP type microwave triode Q ₁ and the NPN type microwave triode Q ₂ are deeply saturated, the amplitude of the output voltage reaches the maximum. Due to the symmetrical circuit structure, the output signal amplitude is also symmetrical. When the diode _D3 is completely cut off, the capacitors _C5 and _C6 mainly pass through the collector _- emitter _of the PNP microwave triode Q1, the NPN microwave triode _Q2 , the diodes _D3 , _D4 and the short circuit T1, short circuit The discharge circuit formed by the route T ₂ , the capacitor C ₇ , the capacitor C ₈ , the resistor R _L1 , and the resistor R _L2 discharges, and the capacitor discharge current decreases exponentially. At this time, the voltage output by diode _D3 decreases exponentially, and the voltage outputted by diode D4 increases exponentially _. When the voltage across the diode D2 is lower than the turn _{- on} voltage of the diode _D3 and the diode D4, the diode _D3 and the diode D4 are _turned off, and the output signal is 0. _In this way, a positive pulse signal is obtained at the cathode of _D3 and a negative pulse signal is obtained at the anode of D4 at the same time. The positive pulse signal propagates in both directions of the short _- circuit line T1 and the resistor R _L1 , and the negative pulse signal propagates in the _two directions of the short-circuit line T2 and the resistor R _L1 . The signal propagating in the direction of the short-circuit line is reflected at the short-circuit and then reversed, and then also propagates in the direction of the resistance _RL1 and the resistance _RL2 and is synthesized with the previously arrived signal to form a single-cycle pulse signal.

As shown in FIG. 6 , the sample and hold circuit includes a diode bridge, a resistor Rs, a resistor R _t1 , a resistor R _t2 , a diode D ₂₁ , a diode D ₂₂ , a capacitor C ₂₁ , a capacitor C ₂₂ , a short circuit T ₂₁ , and a short circuit T ₂₂ , One bridge arm of the diode bridge is used as an input end and is connected to the antenna through the resistor _Rs , and the other bridge arm is used as the output end of the sample and hold circuit. _t2 is grounded, the output terminal of the forward unipolar pulse signal output by the symmetrical sampling gate pulse circuit is connected to the positive pole of the diode bridge through the diode D ₂₁ and the capacitor C ₂₁ in turn, and the reverse unipolar pulse signal output by the symmetrical sampling gate pulse circuit is output. The terminals are connected to the cathode of the diode bridge through the diode D ₂₂ and the capacitor C ₂₂ in turn. The intermediate point between the diode D ₂₁ and the capacitor C ₂₁ is grounded through the short circuit T ₂₁ , and the intermediate point between the diode D ₂₂ and the capacitor C ₂₂ is connected to the ground through the short circuit T 21 . Route T ₂₂ is grounded. The symmetrical unipolar pulse signal generated by the symmetrical pulse generating circuit is rectified by the Schottky diodes D ₂₁ and D ₂₂ and the pulse width is further narrowed and tailing is reduced. The rectified pulse signal propagates in two directions of the capacitors C ₂₁ , C ₂₂ and the short circuit. The pulse signal propagating in the direction of the capacitors C ₂₁ and C ₂₂ makes the left pole plate of the capacitor charge rapidly, and D ₂₁ and D ₂₂ are quickly turned off. Capacitors C ₂₁ and C ₂₂ are combined with the diode bridge to form a high-pass filter. The pulse signal coupled by the capacitor makes the diode bridge conduct quickly. At this time, the sampled signal is charged to the capacitor C _s through the diode bridge, and the signal amplitude is obtained at the output end. proportional signal. The pulse signal propagating in the direction of the short-circuit line produces total reflection and phase inversion at the short point. After the reflection, it returns along the transmission line and is superimposed with the original pulse signal to generate a single-cycle pulse signal. The pulse width of the first half of the single-cycle signal is narrower than the original unipolar pulse width. , so that the sampling aperture during sampling is reduced, which is beneficial to improve the resolution of the sampling signal and the bandwidth of the receiver. As the positive and negative capacitor pulses charge capacitors C ₂₁ and C ₂₂ respectively, the voltage of the right plate of C ₂₁ to the left plate decreases rapidly, and the voltage of the right plate of C ₂₂ to the left plate increases rapidly _{. 22} When the voltage of the right plate is lower than the conduction voltage of the diode bridge, the second-bridge tube bridge is turned off, and the sampling of the signal is terminated. During the second half of the single-cycle pulse signal, the diode bridge is reverse biased. When there is no pulse signal, the charge accumulated when the capacitors C ₂₁ and C ₂₂ are charged by the previous pulse cannot be released due to the cut-off of the diode bridge, so the diode bridge is also in the cut-off state. The reception is out of control due to the sampled signal amplitude being too large. The sampled signal is integrated, held and amplified to obtain the received signal.

In this embodiment, the UWB pulse radar receiving device is made of a TP2 microwave circuit board (dielectric constant of 10.2, thickness of 0.05 in, and loss angle of 0.0023) produced by Jiangsu Taixing Microwave Materials Factory. The diode bridge adopts HSMS286P produced by Agilent Company; the differential amplifier adopts THS4502 produced by TI Company, and the amplifier for amplifying the sampling signal adopts TL071 operational amplifier produced by TI Company.

Hereinafter, the performance of the receiver in the UWB pulse radar receiving apparatus in this embodiment will be tested by using the difference frequency receiving scheme. Assuming that the clock frequency of the received signal (transmitter control clock) is f ₁ , and the receiver sampling clock frequency (receiver control clock) is f ₂ , f ₁ and f ₂ satisfy the following relationship: f ₁ =N ₁ f ₂ + Δf

In the above formula, N ₁ is an integer, and Δf is the frequency offset between the clock frequency f ₁ and the clock frequency f ₂ . Similar to continuous wave mixing, the frequency of the down-converted signal obtained after sampling and holding is Δf.

FIG. 7 is a waveform of a receiver output signal when the clock frequency f ₁ =1GHz, the power is a sinusoidal signal of 0dBm, and the clock frequency f ₂ =0.9999MHz in this embodiment. FIG. 8 is a waveform of a receiver output signal when the clock frequency f ₁ =5GHz, the power is a sinusoidal signal of 0dBm, and the clock frequency f ₂ =0.9999MHz in this embodiment. FIG. 9 is a sampled short pulse signal with a clock frequency f ₁ =5 MHz in this embodiment. FIG. 10 is the waveform of the output signal of the receiver when the signal of FIG. 7 is sampled when the clock frequency f ₂ =4.9999 MHz in this embodiment. FIG. 11 is an A-scan radar signal obtained by the receiver sampling the receiving antenna signal when the clock frequency f ₁ =5 MHz and the clock frequency f ₂ =4.9999 MHz in this embodiment. FIG. 12 corresponds to the B-scan radar signal in this embodiment. Figure 13 Measured and calculated receiver conversion loss in this embodiment. FIG. 14 shows the corresponding relationship between the power of the baseband signal output by the receiver and the power of the sampled signal when the clock frequency f ₁ is 2 GHz in this embodiment. 7 to 14, it can be seen that the receiver in the ultra-wideband pulse radar receiving device in this embodiment can effectively receive the input high-speed signal, and can solve the time step bottleneck between reception and transmission when the delay device is used alone The problem is that the received signal has a wide frequency range.

The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims (6)

1. a difference frequency-delay type transceiver clock synchronization method for ultra-wideband pulse radar receiving device, it is characterized in that implementing step comprises: 1) For clock 1, divide the frequency by the N frequency divider to obtain clock 3, and for clock 2 by dividing the frequency by the N frequency divider to obtain clock 4; phase remains at zero; 2) The clock 3 is buffered and output to control the transmitter to transmit pulses; the clock 4 is buffered and output to control the receiver to receive radar echoes; In step 1), the timing is delayed by controlling clock 3 or clock 4 to keep the phase of clock 3 and clock 4 at zero. Specifically, it means that every elapsed time t ′ = N / Δf controls clock 3 or clock 4 to delay the clock. The phase of 3 and clock 4 remains zero, where N is the division multiple of the frequency divider and Δf is the clock frequency difference between clock 1 and clock 2. 2. a differential frequency-delay type transceiver clock synchronization circuit for the ultra-wideband pulse radar receiving device based on the differential frequency-delay type transceiver clock synchronization method for the ultra-wideband pulse radar receiving device according to claim 1, It is characterized in that it includes a transmit clock circuit unit, a receive clock circuit unit and a controller, the transmit clock circuit unit and the receive clock circuit unit all include a clock source, a frequency divider, and a buffer connected in sequence, and the transmit clock circuit unit . At least one of the two receiving clock circuit units is located between the frequency divider and the buffer, and a delay device is connected in series, and the control end of the delay device and the control end of the frequency divider are respectively connected to the controller. 3 . The differential frequency-delay type transceiver clock synchronization circuit for an ultra-wideband pulse radar receiving device according to claim 2 , wherein the clock source of the transmitting clock circuit unit is a temperature compensated crystal oscillator. 4 . 4. The differential frequency-delay type transceiver clock synchronization circuit for an ultra-wideband pulse radar receiving device according to claim 2, wherein the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator The control terminal of the voltage-controlled temperature-compensated crystal oscillator is connected with a digital module conversion controller, and the control terminal of the digital module conversion controller is connected with the control unit. 5. An ultra-wideband pulse radar receiving device, comprising a clock synchronization circuit, a transmitter and a receiver, wherein the clock synchronization circuit is used for receiving the ultra-wideband pulse radar according to any one of claims 2 to 4 The difference frequency-delay type transceiver clock synchronization circuit of the device, the output end of the transmitting clock circuit unit is connected with the clock input end of the transmitter, the output end of the receiving clock circuit unit is connected with the clock input end of the receiver, so The receiver includes a receiving antenna, a low noise amplifier, a symmetrical sampling gate pulse circuit, a sample and hold circuit, and a baseband signal filtering and amplifying circuit. The receiving antenna is connected to one input end of the symmetrical sampling gate pulse circuit through a low noise amplifier. The input end of the sampling gate pulse circuit is connected to the buffer, and the output end is connected to another input end of the sampling and holding circuit. The output end of the sampling and holding circuit outputs the received signal through the baseband signal filtering and amplifying circuit, and the symmetrical sampling gate pulse The circuit includes differential operational amplifier U ₁ , complementary broadband PNP microwave triode Q ₁ and NPN microwave triode Q ₂ , resistors R ₉ -R ₁₂ , resistors R _L1 -R _L2 , short-circuit lines T ₁ -T ₂ , and diode D ₂ ～D ₄ and capacitors C ₅ ～C ₈ , the differential operational amplifier U1 generates _a pair of differential signals at the non-inverting output terminal and the reverse output terminal under the driving of the input clock signal as the control signal Vs, and respectively outputs them to the PNP type microwave triode Q ₁ and NPN microwave triode Q ₂ , the emitters of PNP microwave triode Q ₁ and NPN microwave triode Q ₂ are connected to each other, and the collector of PNP microwave triode Q ₁ is connected to the negative power supply -Vcc through resistor R ₉ At the same time, the collector of the PNP microwave triode Q ₁ is also grounded through the capacitor C ₅ , the forward diode D ₃ , the capacitor C ₇ , and the resistor R _L1 in turn, and the intermediate point between the diode D ₃ and the capacitor C ₇ passes through the short circuit T ₂ is grounded, the intermediate point between the capacitor C ₅ and the diode D ₃ is connected to the negative power supply -Vcc through the resistor R ₁₁ , the collector of the NPN type microwave triode Q ₂ is connected to the positive power source + Vcc through the resistor R ₁₀ , while the NPN type microwave triode is connected to the positive power source +Vcc. The collector of Q ₂ is also grounded through capacitor C ₆ , reverse diode D ₄ , capacitor C ₈ , and resistor R _L2 in turn. The intermediate point between diode D ₄ and capacitor C ₈ is grounded through short-circuit line T ₁ , and capacitor C _{6 The} intermediate point between the diodes D4 is connected to the positive power supply ₊ Vcc through the resistor _R12 , and the intermediate point between the capacitor _C6 and the diode _D4 is also connected to the capacitor _C5 and the diode _D3 through the forward diode D2. the intermediate point. 6 . The ultra-wideband pulse radar receiving device according to claim 5 , wherein the sample and hold circuit comprises a diode bridge, a resistor Rs, a resistor R _t1 , a resistor R _t2 , a diode D ₂₁ , a diode D ₂₂ , and a capacitor C 6 . _21. Capacitor C ₂₂ , short-circuit line T ₂₁ , and short-circuit line T ₂₂ , one bridge arm of the diode bridge is used as an input end and is connected to the antenna through the resistor Rs, and the other bridge arm is used as the output end of the sample and hold circuit, the diode The bridge and the input terminal connected to the antenna through the resistor Rs are also _grounded through the resistor R _t1 and the resistor R _{t2 respectively} . It is connected to the anode of the diode bridge, and the reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is connected to the cathode of the diode bridge through the diode D ₂₂ and the capacitor C ₂₂ in turn, and between the diode D ₂₁ and the capacitor C ₂₁ The intermediate point between the diode D ₂₂ and the capacitor C ₂₂ is _grounded through the short-circuit line T ₂₁ .

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