CN111413677A - Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device - Google Patents

Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device Download PDF

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CN111413677A
CN111413677A CN202010124043.6A CN202010124043A CN111413677A CN 111413677 A CN111413677 A CN 111413677A CN 202010124043 A CN202010124043 A CN 202010124043A CN 111413677 A CN111413677 A CN 111413677A
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clock
circuit
diode
capacitor
frequency
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CN111413677B (en
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余慧敏
王玲
刘治平
刑先锋
杨国成
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Hunan Normal University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/285—Receivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/285—Receivers
    • G01S7/292—Extracting wanted echo-signals
    • G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The invention discloses a difference frequency-delay type receiving and sending clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device, wherein the method comprises the steps of obtaining a clock 3 by aiming at clock 1 frequency division and obtaining a clock 4 by aiming at clock 2 frequency division; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero; buffering the clock 3 and outputting to control the transmitter to transmit pulses; buffering the clock 4 and outputting to control a receiver to receive radar echo; the circuit comprises a transmitting clock circuit unit, a receiving clock circuit unit and a controller, wherein the transmitting clock circuit unit and the receiving clock circuit unit respectively comprise a clock source, a frequency divider and a buffer which are sequentially connected. The invention can solve the bottleneck problem of time stepping between receiving and transmitting when a delayer is independently adopted, is beneficial to improving the frequency of the receiver for receiving signals, and overcomes the defects of poor real-time performance, low signal refresh rate and data redundancy of differential frequency type receiving.

Description

Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device
Technical Field
The invention belongs to the technical field of ultra-wideband pulse receiving, and particularly relates to a difference frequency-delay type receiving and transmitting clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device.
Background
Ultra-wideband radars are gaining increasing attention in the fields of military, commerce, environmental protection and the like due to their high range resolution, strong penetration, low interception rate and strong interference resistance. The performance of ultra-wideband radar has reached a higher level with the development of wideband microwave devices and the enhancement of signal processing capability of software algorithms since the 90 s of the 20 th century. The ultra-wideband synthetic aperture radar of Swedish, America, Italy, Russia and other countries realizes multiple flight experiments and enters into the practical application stage. In the commercial ultra-wideband radar, the ultra-wideband through-wall radar, the ground penetrating radar and the life detection radar have wide application prospects. The through-wall radar is an ultra-wideband pulse radar and is mainly applied to the military and public safety fields of anti-terrorism warfare, disaster rescue, urban roadway battle and the like. By emitting the ultra-high frequency radar pulse and receiving the echo signal, the through-wall radar can penetrate through doors, brick walls, stone slabs and concrete walls, can comprehensively cover the internal space, can quickly estimate the conditions in a room, and can acquire the accurate position information of the hidden human body and the hidden moving object. Ground Penetrating Radar (also called Ground Penetrating Radar) and geological Radar. Is a nondestructive detection method for determining the distribution of underground media by using radio waves with the frequency of 106-109 Hz. The ground penetrating radar method is that high frequency electromagnetic wave is transmitted to underground through a transmitting antenna, the electromagnetic wave reflected back to the ground is received through a receiving antenna, the electromagnetic wave is reflected when encountering a boundary surface with electrical property difference when propagating in an underground medium, and the spatial position, the structure, the form and the burial depth of the underground medium are deduced according to the characteristics of the received electromagnetic wave, such as the waveform, the amplitude intensity, the time change and the like. The life detection radar is based on the principle of an ultra-wideband radar, and achieves the purposes of detecting, searching and rescuing survivors buried in ruins by using the human body micro-motion Doppler echo effect carried by nanosecond electromagnetic pulses. It can search the life information quickly and efficiently, and bring the hope of life to the trapped people. The life detection radar based on the ultra-wideband technology has the advantages of low radiation power, no influence on a human body, low system power consumption, convenient power supply, portability, strong capability of penetrating through an obstacle, capability of detecting life information of the human body after the obstacle, and strong anti-multipath and narrowband interference capability.
The typical ultra-wideband radar system consists of a transmitter, a receiver, a transmitting antenna, a receiving antenna, a radar master control system and a data acquisition, processing and display system. The ultra-wideband signal generated by the transmitter is converted into electromagnetic wave by the transmitting antenna to be radiated, and part of electromagnetic wave energy reflected and scattered by the target is captured by the receiving antenna and converted into a voltage signal for back-end processing. Due to the difference of the distance and the scattering characteristic of the target, the amplitude and the time delay of the echo signals corresponding to different targets received by the receiver also have difference, and the target can be detected by identifying the difference through processing the received data. However, since the clock pulses of the transmitter and the receiver are high-frequency pulses, it is very difficult to control the synchronization of the clock pulses of the transmitter and the receiver.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a difference frequency-delay type receiving and transmitting clock synchronization method, a circuit and an ultra-wideband pulse radar receiving device.
In order to solve the technical problems, the invention adopts the technical scheme that:
a difference frequency-delay type transceiving clock synchronization method for an ultra-wideband pulse radar receiving device comprises the following implementation steps:
1) dividing the frequency of the clock 1 by an N frequency divider to obtain a clock 3, and dividing the frequency of the clock 2 by the N frequency divider to obtain a clock 4; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero;
2) respectively buffering the clocks 3 and then outputting to control the transmitter to transmit pulses; and buffering the clock 4 and outputting to control the receiver to receive the radar echo.
Optionally, the timing in step 1) is delayed by controlling the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 at zero, specifically, the phase of the clock 3 and the clock 4 is kept at zero every time the clock 3 or the clock 4 is delayed by t' = N/Δ f, where N is a division multiple of the frequency divider, and Δ f is a clock frequency difference between the clock 1 and the clock 2.
In addition, the invention also provides a difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving device, which comprises a transmitting clock circuit unit, a receiving clock circuit unit and a controller, wherein the transmitting clock circuit unit and the receiving clock circuit unit respectively comprise a clock source, a frequency divider and a buffer which are sequentially connected, at least one of the transmitting clock circuit unit and the receiving clock circuit unit is positioned between the frequency divider and the buffer and is connected with the time delay in series, and the control end of the time delay and the control end of the frequency divider are respectively connected with the controller.
Optionally, the clock source of the transmission clock circuit unit is a temperature compensated crystal oscillator.
Optionally, the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator, a control end of the voltage-controlled temperature-compensated crystal oscillator is connected to a digital module conversion controller, and a control end of the digital module conversion controller is connected to the control unit.
In addition, the invention also provides an ultra-wideband pulse radar receiving device, which comprises a clock synchronization circuit, a buffer, a transmitter and a receiver, wherein the clock synchronization circuit is the difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving device, the output end of the transmitting clock circuit unit is connected with the clock input end of the transmitter through the buffer, and the output end of the receiving clock circuit unit is connected with the clock input end of the receiver through the buffer.
Optionally, the receiver includes a receiving antenna, a low noise amplifier, a symmetric sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit, the receiving antenna is connected to one input end of the symmetric sampling gate pulse circuit through the low noise amplifier, the input end of the symmetric sampling gate pulse circuit is connected to the buffer, the output end of the symmetric sampling gate pulse circuit is connected to the other input end of the sample-and-hold circuit, and the output end of the sample-and-hold circuit outputs the received signal through the baseband signal filtering and amplifying circuit.
Optionally, the symmetrical sampling gate pulse circuit comprises a differential operational amplifier U1PNP type microwave triode Q with complementary broadband1And NPN type microwave triode Q2Resistance R9～R12Resistance RL1～RL2Short circuit line T1～T2Diode D2～D4And a capacitor C5～C8Differential operational amplifier U1At the input of a clock signal as a control signal VsUnder the drive of the PNP type microwave triode Q, a pair of differential signals are generated at a non-inverting output end and an inverting output end and are respectively output to the PNP type microwave triode Q1And NPN type microwave triode Q2PNP type microwave triode Q1And NPN type microwave triode Q2The emitting electrodes of the two are mutually communicated, and the PNP type microwave triode Q1Collector through resistor R9PNP type microwave triode Q connected with negative power supply-Vcc1Is further passed through a capacitor C5Diode D in the forward direction3Capacitor C7Resistance RL1Ground, diode D3Capacitor C7The intermediate contact between the two is passed through a short circuit line T2Ground, capacitor C5Diode D3Intermediate contact between them is through resistance R11NPN type microwave triode Q connected with negative power supply-Vcc2Collector through resistor R10Is connected with a positive power supply + Vcc and is also provided with an NPN type microwave triode Q2Is further passed through a capacitor C6Diode D in the reverse direction4Capacitor C8Resistance RL2Ground, diode D4Capacitor C8The intermediate contact between the two is passed through a short circuit line T1Ground, capacitor C6Diode D4Intermediate contact between them is through resistance R12A capacitor C connected to the positive power supply + Vcc6Diode D4The intermediate junction between them also passing through a forward diode D2Connected to a capacitor C5Diode D3Intermediate junction between them.
Optionally, the sample-and-hold circuit comprises a diode bridge, a resistor Rs, a resistor Rt1Resistance Rt2Diode D21Diode D22Capacitor C21Capacitor C22Short circuit line T21Short circuit line T22One bridge arm of the diode bridge is used as an input end and connected with the antenna through a resistor Rs, the other bridge arm of the diode bridge is used as an output end of the sample hold circuit, and the input ends of the diode bridge and the antenna connected through the resistor Rs are respectively connected through a resistor Rt1Resistance Rt2The positive unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit sequentially passes through the diode D21Capacitor C21The reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is sequentially connected with the anode of the diode bridge22Capacitor C22Connected to the cathode of a diode bridge, a diode D21Capacitor C21The intermediate contact between the two is passed through a short circuit line T21Ground, diode D22Capacitor C22The intermediate contact between the two is passed through a short circuit line T22And (4) grounding.
Compared with the prior art, the invention has the following advantages:
1. the invention divides the frequency of the clock 1 by the N frequency divider to obtain the clock 3, divides the frequency of the clock 2 by the N frequency divider to obtain the clock 4, divides the frequency of the clock to generate controllable frequency difference, and equivalently samples the input high-speed signal, thereby solving the bottleneck problem of time stepping between receiving and transmitting when a delayer is independently adopted, and being beneficial to improving the frequency of the signal received by a receiver.
2. The invention keeps the phase of the clock 3 and the clock 4 to be zero by controlling the clock 3 or the clock 4 to carry out time delay at regular time, thereby overcoming the defects of poor real-time performance, low signal refreshing rate and data redundancy of differential frequency type receiving.
Drawings
Fig. 1 is a flowchart illustrating a method for synchronizing a transmit/receive clock according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a transceiver clock synchronization apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a specific implementation of the transceiver clock synchronization apparatus according to the embodiment of the present invention.
Fig. 4 is a schematic diagram of a basic structure of an ultra-wideband pulse radar receiving device according to an embodiment of the present invention.
FIG. 5 is a schematic circuit diagram of a symmetrical sampling gate pulse circuit according to an embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a sample-and-hold circuit according to an embodiment of the present invention.
Fig. 7 shows the sampling result of the 1GHz sinusoidal signal in the embodiment of the present invention.
Fig. 8 shows the sampling result of the 5GHz sinusoidal signal in the embodiment of the present invention.
Fig. 9 is a 500ps short pulse signal in an embodiment of the present invention.
Fig. 10 shows the results of sampling a 500ps short pulse in an embodiment of the present invention.
Fig. 11 shows a-scan radar signals received by an ultra-wideband pulse radar in an embodiment of the invention.
Fig. 12 is a B-scan radar signal received by an ultra-wideband pulse radar in an embodiment of the invention.
Fig. 13 is a receiver conversion loss in an embodiment of the present invention.
Fig. 14 shows the power of the baseband signal output from the receiver in the embodiment of the present invention.
Detailed Description
As shown in fig. 1, the implementation steps of the difference frequency-delay type transceiving clock synchronization method for the ultra-wideband pulse radar receiving apparatus of this embodiment include:
1) dividing the frequency of the clock 1 by an N frequency divider to obtain a clock 3, and dividing the frequency of the clock 2 by the N frequency divider to obtain a clock 4; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero;
2) respectively buffering the clocks 3 and then outputting to control the transmitter to transmit pulses; and buffering the clock 4 and outputting to control the receiver to receive the radar echo.
Suppose clock 1 has a clock frequency f0+ Δ f, clock 2 having a clock frequency f0And Δ f is the clock frequency difference between clock 1 and clock 2. If the clock 1 is directly adopted to control the transmitter to transmit pulses and the clock 2 controls the receiver to receive radar echoes, the time step length tau during sampling is as follows:
Figure BDA0002393867000000041
at this time, the time t required by the radar to obtain a piece of A-Scan data is as follows:
Figure BDA0002393867000000042
when f is0And when the frequency is 10MHz and the frequency is delta f =0.0001MHz, the time step is tau 1ps, and an A-Scan waveform is obtained every t =10 ms. Each waveform corresponds to a radar echo with an original time length of 100ns, and the maximum detection distance is about 15 m. However, since the clock pulses of the transmitter and the receiver are high-frequency pulses, it is very difficult to control the synchronization of the clock pulses of the transmitter and the receiver. In view of the above technical problems, in the present embodiment, a clock 3 is obtained by dividing a clock 1 by an N-divider, and a clock 4 is obtained by dividing a clock 2 by an N-divider, so that a controllable frequency difference can be generated between the clock 3 and the clock 4 by the frequency division, so as to perform equivalent sampling on an input high-speed signal. Assuming that the frequency divider is an N-frequency divider, the divided clock frequencies are respectively (f)0+ Δ f)/N and f0and/N. If the clock is adopted to respectively control the radar transmitter and the receiver, the sampling time step length is N times of the original sampling time step length. The time required for the radar to obtain an A-Scan waveform is also N times the original time. The time length of each waveform corresponding to the original radar echo is also N times of the original time length. For enhancing radarThe real-time performance is realized, redundant data is reduced, and the time of each A-Scan waveform is shortened in a delay compensation mode by delaying the frequency-divided clock through a cascade delayer behind a frequency divider.
In this embodiment, in the step 1), delaying the clock 3 or the clock 4 to keep the phase of the clock 3 and the clock 4 at zero by controlling the clock 3 or the clock 4 specifically means that the phase of the clock 3 and the clock 4 is kept at zero every time t' = N/Δ f elapses by controlling the clock 3 or the clock 4 to delay, where N is a division multiple of the frequency divider, and Δ f is a clock frequency difference between the clock 1 and the clock 2.
The particular choice in this embodiment is to control the clock 3 delay to keep the phase of clock 3 and clock 4 at zero. The frequency of clock 3 is (f) which is the clock divided by clock 10+ Δ f)/N; the clock obtained by dividing clock 2 is clock 4 with frequency f0At the time of/N. Every time the phases of the two clock signals of clock 3 and clock 4 are aligned once over time t' = N/Δ f: when the time t passes1If =1/Δ f, the phase of clock 3 advances relative to clock 4
Figure BDA0002393867000000051
Corresponding rising or falling edge time lead Δ t ═ 1/[ N (f)0+Δf0)]. At this time, the clock 3 is delayed by Δ t 1/[ N (f) by the programmable delay unit0+Δf0)]Then the phase difference between clock 3 and clock 4 will be zero. Similarly, when the time t passesN-1When the phase of clock 3 is advanced relative to clock 4 by (N-1)/Δ f
Figure BDA0002393867000000052
Corresponding rising or falling edge time lead Δ t ═ N-1/[ N (f)0+Δf0)]. At this time, if the clock 3 is delayed by Δ t by the programmable delay unit (N-1)/[ N (f)/]0+Δf0)]Then the phase difference between clock 3 and clock 4 will be restored to zero. When the time t passesNWhen N/Δ f, clock 3 is delayed back to 0, and the phase difference between clock 3 and clock 4 will be zero. Thus, the delay compensation is performed on the clock 3, so that the phase alignment of the two clocks is performed by changing the elapsed time to 1/N of the previous time. Similarly, each A-Scan radar signalThe length of the waveform is reduced to 1/N, thereby overcoming the defects of poor real-time performance, low signal refreshing rate and data redundancy of differential frequency type receiving. The bottleneck of time stepping between reception and transmission can be solved by using a delayer alone.
As shown in fig. 2, the present embodiment further provides a difference frequency-delay type transceiving clock synchronization circuit for an ultra-wideband pulse radar receiving apparatus, including a transmitting clock circuit unit, a receiving clock circuit unit, and a controller, where the transmitting clock circuit unit and the receiving clock circuit unit both include a clock source, a frequency divider, and a buffer, which are connected in sequence, at least one of the transmitting clock circuit unit and the receiving clock circuit unit is located between the frequency divider and the buffer, and is connected in series with the delay, and a control end of the delay and a control end of the frequency divider are connected with the controller respectively.
As shown in fig. 3, the clock source of the transmission clock circuit unit is a temperature compensated crystal oscillator, the output signal of the temperature compensated crystal oscillator in this embodiment is a 10MHz HCMOS type square wave, and the frequency stability of the output signal is within ± 1 PPM.
As shown in FIG. 3, the clock source of the receiving clock circuit unit is a voltage-controlled temperature compensation crystal oscillator, the control end of the voltage-controlled temperature compensation crystal oscillator is connected with a digital module conversion controller (DAC L TC2641), the control end of the digital module conversion controller (DAC L TC2641) is connected with the control unit, when the control voltage is the central voltage, the output signal of the voltage-controlled temperature compensation crystal oscillator is a 10MHz HCMOS type square wave, the voltage-controlled temperature compensation crystal oscillator can generate a frequency deviation of +/-3 PPM- +/-15 PPM within the control voltage range of 0.1 × VDD-0.9 × VDD, the control voltage of the voltage-controlled temperature compensation crystal oscillator is provided by the digital module conversion controller (DAC L TC2641), the analog voltage is adjusted by the digital module conversion controller (DAC L TC2641), so that the output signal of the voltage-controlled crystal oscillator generates the frequency deviation of-10 PPM, and the HCMOS type square wave with 9.9999MH is output.
As shown in fig. 3, in this embodiment, a CP L D chip with a model of XC95144 is used to integrate functions of a controller and a frequency dividing unit, where the frequency dividing unit includes two frequency dividers for performing N-frequency division on an output clock of a temperature compensated crystal oscillator and an output clock of a voltage controlled temperature compensated crystal oscillator, respectively.
As shown in FIG. 3, the delay unit in this embodiment adopts DS1023-200 programmable delay unit, DS1023-200 programmable delay unit performs delay compensation to the output clock of the frequency divider under the control of CP L D chip, the output clock after delay compensation is reversed by Schmidt inverter and used as the control clock of the transmitter and the receiver to drive the transmitter and the receiver respectively
As shown in fig. 3, the buffers of the transmitting clock circuit unit and the receiving clock circuit unit in this embodiment are implemented by a schmitt inverter with model number SN 74L VC-G14.
In addition, as shown in fig. 4, this embodiment further provides an ultra-wideband pulse radar receiving apparatus, which includes a clock synchronization circuit, a buffer, a transmitter, and a receiver, where the clock synchronization circuit is the difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving apparatus in this embodiment, an output end of the transmitting clock circuit unit is connected to a clock input end of the transmitter through the buffer, and an output end of the receiving clock circuit unit is connected to a clock input end of the receiver through the buffer.
The transmitter in this embodiment has the same structure as the conventional transmitter, and employs a nanosecond pulse generating circuit. On the basis, the embodiment also provides a circuit improvement of the receiver, which comprises a symmetrical sampling gate pulse circuit and a sample hold circuit. As shown in fig. 4, the receiver includes a receiving antenna, a low noise amplifier, a symmetric sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit, where the receiving antenna is connected to one input end of the symmetric sampling gate pulse circuit through the low noise amplifier, the input end of the symmetric sampling gate pulse circuit is connected to a buffer, the output end of the symmetric sampling gate pulse circuit is connected to the other input end of the sample-and-hold circuit, and the output end of the sample-and-hold circuit outputs a received signal through the baseband signal filtering and amplifying circuit.
As shown in FIG. 5, the symmetrical sampling gate pulse circuit includes a differential operational amplifier U1PNP type microwave triode Q with complementary broadband1And NPN type microwave triode Q2Resistance R9～R12Resistance RL1～RL2Short circuit line T1～T2Diode D2～D4And a capacitor C5～C8Differential operational amplifier U1At the input of a clock signal as a control signal VsUnder the drive of the PNP type microwave triode Q, a pair of differential signals are generated at a non-inverting output end and an inverting output end and are respectively output to the PNP type microwave triode Q1And NPN type microwave triode Q2PNP type microwave triode Q1And NPN type microwave triode Q2The emitting electrodes of the two are mutually communicated, and the PNP type microwave triode Q1Collector through resistor R9PNP type microwave triode Q connected with negative power supply-Vcc1Is further passed through a capacitor C5Diode D in the forward direction3Capacitor C7Resistance RL1Ground, diode D3Capacitor C7The intermediate contact between the two is passed through a short circuit line T2Ground, capacitor C5Diode D3Intermediate contact between them is through resistance R11NPN type microwave triode Q connected with negative power supply-Vcc2Collector through resistor R10Is connected with a positive power supply + Vcc and is also provided with an NPN type microwave triode Q2Is further passed through a capacitor C6Diode D in the reverse direction4Capacitor C8Resistance RL2Ground, diode D4Capacitor C8The intermediate contact between the two is passed through a short circuit line T1Ground, capacitor C6Diode D4Intermediate contact between them is through resistance R12A capacitor C connected to the positive power supply + Vcc6Diode D4The intermediate junction between them also passing through a forward diode D2Connected to a capacitor C5Diode D3Intermediate junction between them.
The symmetrical sampling gate pulse circuit can generate symmetrical narrow pulses (a pair of pulses with opposite positive and negative polarities). The generation process of the symmetrical pulse signal can be divided into generation of step signal, reverse conduction to reverse cut-off of step recovery diode, reverse cut-off of step diode, forward conduction of step diode, and Q of PNP type microwave triode1And NPN type microwave triode Q2The switching from on to off is performed in several stages. Differential operational amplifier U1In the control signal VsGenerates a pair of differential signals at the in-phase output terminal and the inverted output terminal. When the control signal VsAt the arrival of the rising edge of (2), at the differential operational amplifier U1The in-phase output end and the reverse output end respectively obtain a rising edge and a falling edge. Driven by the differential signal, PNP type microwave triode Q1And NPN type microwave triode Q2Meanwhile, the liquid crystal rapidly enters a saturation region from a cut-off region through an amplification region. Due to the symmetrical circuit structure, the PNP type microwave triode Q1Before the collector voltage is cut off by the triode, -VCCRapidly jumping to 0, and NPN type microwave triode Q2Before the collector voltage is cut off by the triodeCCRapidly dropping to 0. Thereby forming a PNP type microwave triode Q1And NPN type microwave triode Q2The collector of (a) obtains two rapidly symmetrical differential step signals.
In PNP type microwave triode Q1And NPN type microwave triode Q2Before conduction, the capacitor C5、C6The voltages of the left polar plate to earth are respectively power voltage-VCCAnd + VCCThe voltage to ground of the right plate is slightly lower and slightly higher than 0 respectively. When PNP type microwave triode Q1NPN type microwave triode Q2When turned on simultaneously, the capacitor C5And C6At the same time, the diode D starts to discharge through the discharge loop2By PNP type microwave triode Q1And NPN type microwave triode Q2Forward conduction before turn-off becomes reverse biased. Diode D2Is a step recovery diode, when diode D2The reverse bias does not cut off immediately, but completely after the storage time and the step time. From reverse bias to the end of the storage time, diode D2The impedance is small as when conducting in the forward direction. At this time, the capacitance C5And C6Mainly by PNP type microwave triode Q1NPN type microwave triode Q2Collector-emitter and diode D3The discharge circuit is configured to discharge. In the diode D2Storage period of (Q)1、Q2The transition from the cut-off region to the saturation region is through the amplification region. At this time, PNP type microwave triode Q1NPN type microwave triode Q2And a diode D and equivalent impedance between the collector and emitter of2Is much larger than the equivalent impedance of diode D2The voltage division obtained at both ends is very small, diode D3、D4Can not be conducted in the forward direction, and the output signal is almost zero. In the step period, the diode D3The reverse conduction is quickly changed into the reverse cut-off, and the impedance is quickly changed from small to large. At this time, for the capacitor C5、C6The two plates still store a large amount of charge, and the discharge continues, with diode D3Of the diode D3The reverse voltage across the terminals rises rapidly. When the voltage is higher than the diode D3And D4At the on-voltage of diode D3、D4Are conducted and respectively pass through the diode D3And D4And outputting a voltage signal which rapidly rises and rapidly falls. The rise and fall times of which are mainly determined by the diode D3Is determined. If a step recovery diode with the step time of less than 100ps is adopted, the rising edge or the falling edge of the output voltage signal can reach less than 100 ps. When diode D2If PNP type microwave triode Q is completely cut off1NPN type microwave triode Q2After deep saturation, the amplitude of the output voltage reaches a maximum. Due to the symmetrical circuit structure, the output signal amplitude is also symmetrical. When diode D3After complete cut-off, the capacitance C5And C6Mainly by PNP type microwave triode Q1NPN type microwave triode Q2Collector-emitter, diode D3、D4And a short circuit line T1Short circuit line T2Capacitor C7Capacitor C8Resistance RL1Resistance RL2The formed discharge loop discharges, and the discharge current of the capacitor decreases exponentially. At this time, via the diode D3The output voltage decreases exponentially through a diode D4The output voltage rises exponentially. When diode D2Voltage across lower than diode D3And a diode D4At the on-voltage of diode D3And a diode D4And when the circuit is cut off, the output signal is 0. Thus, respectively at D at the same time3The cathode of (2) obtains a positive pulse signal at D4The anode of (2) gets a negative pulse signal. Positive pulse signal to short circuit line T1And a resistance RL1Two-way propagation, negative pulse signal to short circuit line T2And a resistance RL1Propagating in two directions. The signal propagating in the direction of the short-circuit line is reflected at the short-circuit and then is reversed and then also flows to the resistor RL1And a resistance RL2The directional propagation and the previously arriving signal are combined to form a monocycle signal.
As shown in FIG. 6, the sample-and-hold circuit includes a diode bridge, a resistor Rs, and a resistor Rt1Resistance Rt2Diode D21Diode D22Capacitor C21Capacitor C22Short circuit line T21Short circuit line T22One bridge arm of the diode bridge is used as an input end and connected with the antenna through a resistor Rs, the other bridge arm is used as an output end of the sample hold circuit, and the input ends of the diode bridge and the antenna connected through the resistor Rs are respectively connected with the output end of the sample hold circuit through a resistor Rt1Resistance Rt2The output end of the positive unipolar pulse signal output by the symmetrical sampling gate pulse circuit is grounded and sequentially passes through the diode D21Capacitor C21The reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is connected with the anode of the diode bridge and sequentially passes through the diode D22Capacitor C22Connected to the cathode of a diode bridge, a diode D21Capacitor C21The intermediate contact between the two is passed through a short circuit line T21Ground, diode D22Capacitor C22The intermediate contact between the two is passed through a short circuit line T22And (4) grounding. The symmetrical unipolar pulse signal generated by the symmetrical pulse generating circuit passes through the Schottky diode D21And D22The rectified pulse width is further narrowed and the tail is reduced. Rectified pulse signal is sent to a capacitor C21、C22And short-circuit lines. To the capacitor C21、C22The directionally propagated pulse signal rapidly charges the left plate of the capacitor, D21、D22And (4) rapidly stopping. Capacitor C21、C22Combining with diode bridge to form high-pass filter, making the diode bridge quickly conduct by pulse signal coupled by capacitor, and making the sampled signal pass through diode bridge and capacitor CsCharging, and obtaining a signal which is proportional to the signal amplitude at the output end. The pulse signal transmitted to the short circuit line direction generates total reflection and phase inversion at a short position, the pulse signal returns along the transmission line after reflection and is superposed with the original pulse signal to generate a monocycle signal, and the pulse width of the front half part of the monocycle signal is narrowed relative to the original unipolar pulse width, so that the sampling aperture during sampling is reduced, and the resolution of the sampling signal and the bandwidth of a receiver are improved. Because the positive and negative pulses of the capacitor are respectively opposite to the capacitor C21And C22Charging, C21The voltage of the right plate to the left plate is rapidly reduced, C22The voltage of the right plate to the left plate rises rapidly when C21Right polar plate pair C22When the voltage of the right polar plate is lower than the conduction voltage of the diode bridge, the two bridge tube bridges are cut off, and the sampling of the signal is stopped. In the latter half period of the monocycle pulse signal, the diode bridge is in a reverse bias state. When there is no pulse signal, the capacitor C is coupled by the previous pulse21、C22The accumulated charges can not be released due to the cut-off of the diode bridge during charging, so that the diode bridge is also in a cut-off state, and the receiving runaway caused by the overlarge amplitude of the sampled signal in the absence of direct current reverse bias voltage is avoided. And integrating, holding and amplifying the sampling signal to obtain a receiving signal.
In the embodiment, the ultra-wideband pulse radar receiving device is manufactured by using a TP2 microwave circuit board (the dielectric constant is 10.2, the thickness is 0.05in, and the loss angle is 0.0023) produced by Jiangsu Taixing microwave material factory, a diode bridge adopts HSMS286P produced by Agilent company, a differential amplifier adopts THS4502 produced by TI company, and an amplifier for amplifying a sampling signal adopts T L071 operational amplifier produced by TI company.
The performance of the receiver in the ultra-wideband pulse radar receiving apparatus in this embodiment will be tested using a difference frequency receiving scheme. Assume that the clock frequency (transmitter control clock) of the received signal is f1ReceivingThe clock frequency of the machine sampling (receiver control clock) is f2，f1And f2The following relationship is satisfied: f. of1＝N1f2+Δf
In the above formula, N1Is an integer, Δ f is the clock frequency f1Clock frequency f2The frequency offset between. Similar to continuous wave mixing, the frequency of the down-converted signal obtained after sample and hold is Δ f.
FIG. 7 shows the clock frequency f in this embodiment1Sine signal of power 0dBm at 1GHz, clock frequency f2The receiver outputs a signal waveform when the frequency is 0.9999 MHz. FIG. 8 shows the clock frequency f in this embodiment1Sinusoidal signal with power of 0dBm at 5GHz, clock frequency f2The receiver outputs a signal waveform when the frequency is 0.9999 MHz. FIG. 9 shows the clock frequency f in this embodiment 15 MHz. FIG. 10 shows the clock frequency f in this embodiment2The receiver outputs a signal waveform when the signal of figure 7 is sampled at 4.9999 MHz. FIG. 11 shows the clock frequency f in this embodiment15MHz, clock frequency f2The receiver samples the a-scan radar signal obtained from the received antenna signal at 4.9999 MHz. Fig. 12 shows a corresponding B-scan radar signal in this embodiment. Fig. 13 shows the measured and calculated receiver conversion loss in this embodiment. FIG. 14 shows the clock frequency f in this embodiment1And when the frequency is 2GHz, the power of the baseband signal output by the receiver corresponds to the power of the sampled signal. As can be seen from fig. 7 to 14, in the receiving apparatus of the ultra-wideband pulse radar in this embodiment, the receiver can effectively receive an input high-speed signal, a bottleneck problem of time stepping between receiving and transmitting when a delay unit is separately used can be solved, and a frequency range of the received signal is wide.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims (9)

1. A difference frequency-delay type transceiving clock synchronization method for an ultra-wideband pulse radar receiving device is characterized by comprising the following implementation steps:
1) dividing the frequency of the clock 1 by an N frequency divider to obtain a clock 3, and dividing the frequency of the clock 2 by the N frequency divider to obtain a clock 4; timing is delayed by controlling a clock 3 or a clock 4 to keep the phase of the clock 3 and the clock 4 to be zero;
2) respectively buffering the clocks 3 and then outputting to control the transmitter to transmit pulses; and buffering the clock 4 and outputting to control the receiver to receive the radar echo.
2. The difference frequency-delay transceiving clock synchronization method for the ultra-wideband pulse radar receiving apparatus according to claim 1, wherein the timing in step 1) is delayed by controlling the clock 3 or the clock 4 to keep the phases of the clock 3 and the clock 4 at zero, specifically, t' = per elapsed time t =N/ΔfControlling clock 3 or clock 4 to delay to keep the phase of clock 3 and clock 4 at zero, whereinNIs the division multiple, Δ, of the frequency dividerfThe clock frequency difference between clock 1 and clock 2.
3. The utility model provides a difference frequency-time delay formula receiving and dispatching clock synchronization circuit for ultra wide band pulse radar receiving arrangement which characterized in that, includes transmission clock circuit unit, receiving clock circuit unit and controller, transmission clock circuit unit, receiving clock circuit unit all include consecutive clock source, frequency divider, buffer, transmission clock circuit unit, receiving clock circuit unit at least one of them is located and has concatenated the delay timer between frequency divider, the buffer, the control end of delay timer, the control end of frequency divider link to each other with the controller respectively.
4. The difference frequency-delay type transceiving clock synchronization circuit for an ultra-wideband pulse radar receiving apparatus according to claim 3, wherein a clock source of the transmitting clock circuit unit is a temperature compensated crystal oscillator.
5. The difference frequency-delay type transceiving clock synchronizing circuit for an ultra-wideband pulse radar receiving device according to claim 3, wherein the clock source of the receiving clock circuit unit is a voltage-controlled temperature-compensated crystal oscillator, the control end of the voltage-controlled temperature-compensated crystal oscillator is connected with a digital module conversion controller, and the control end of the digital module conversion controller is connected with the control unit.
6. An ultra-wideband pulse radar receiving device, comprising a clock synchronization circuit, a transmitter and a receiver, wherein the clock synchronization circuit is the difference frequency-delay type transceiving clock synchronization circuit for the ultra-wideband pulse radar receiving device according to any one of claims 3 to 5, an output end of the transmitting clock circuit unit is connected with a clock input end of the transmitter, and an output end of the receiving clock circuit unit is connected with a clock input end of the receiver.
7. The receiving device of claim 6, wherein the receiver comprises a receiving antenna, a low noise amplifier, a symmetrical sampling gate pulse circuit, a sample-and-hold circuit, and a baseband signal filtering and amplifying circuit, the receiving antenna is connected to one input end of the symmetrical sampling gate pulse circuit through the low noise amplifier, the input end of the symmetrical sampling gate pulse circuit is connected to the buffer, the output end of the symmetrical sampling gate pulse circuit is connected to the other input end of the sample-and-hold circuit, and the output end of the sample-and-hold circuit outputs the received signal through the baseband signal filtering and amplifying circuit.
8. The UWB pulse radar receiving device of claim 7 wherein the symmetrical sampling gate pulse circuit comprises a differential operational amplifier U1PNP type microwave triode Q with complementary broadband1And NPN type microwave triode Q2Resistance R9～R12Resistance RL1～RL2Short circuit line T1～T2Diode D2～D4And a capacitor C5～C8Differential operational amplifier U1At the input of a clock signal as a control signal VsUnder the drive of the PNP type microwave triode Q, a pair of differential signals are generated at a non-inverting output end and an inverting output end and are respectively output to the PNP type microwave triode Q1And NPN type microwave triode Q2PNP type microwave triode Q1And NPN type microwave triode Q2The emitting electrodes of the two are mutually communicated, and the PNP type microwave triode Q1Collector through resistor R9PNP type microwave triode Q connected with negative power supply-Vcc1Is further passed through a capacitor C5Diode D in the forward direction3Capacitor C7Resistance RL1Ground, diode D3Capacitor C7The intermediate contact between the two is passed through a short circuit line T2Ground, capacitor C5Diode D3Intermediate contact between them is through resistance R11NPN type microwave triode Q connected with negative power supply-Vcc2Collector through resistor R10Is connected with a positive power supply + Vcc and is also provided with an NPN type microwave triode Q2Is further passed through a capacitor C6Diode D in the reverse direction4Capacitor C8Resistance RL2Ground, diode D4Capacitor C8The intermediate contact between the two is passed through a short circuit line T1Ground, capacitor C6Diode D4Intermediate contact between them is through resistance R12A capacitor C connected to the positive power supply + Vcc6Diode D4The intermediate junction between them also passing through a forward diode D2Connected to a capacitor C5Diode D3Intermediate junction between them.
9. The UWB pulse radar reception device of claim 7 wherein the sample-and-hold circuit includes a diode bridge, a resistor Rs, a resistor Rt1Resistance Rt2Diode D21Diode D22Capacitor C21Capacitor C22Short circuit line T21Short circuit line T22One bridge arm of the diode bridge is used as an input end and connected with the antenna through a resistor Rs, the other bridge arm of the diode bridge is used as an output end of the sample hold circuit, and the input ends of the diode bridge and the antenna connected through the resistor Rs are respectively connected through a resistor Rt1Resistance Rt2The positive unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit sequentially passes through the diode D21Capacitor C21The reverse unipolar pulse signal output end output by the symmetrical sampling gate pulse circuit is sequentially connected with the anode of the diode bridge22Capacitor C22Connected to the cathode of a diode bridge, a diode D21Capacitor C21The intermediate contact between the two is passed through a short circuit line T21Ground, diode D22Capacitor C22The intermediate contact between the two is passed through a short circuit line T22And (4) grounding.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114167396A (en) * 2020-09-10 2022-03-11 Oppo广东移动通信有限公司 Control method based on ultra-wideband ranging and related device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1906499A (en) * 2004-10-14 2007-01-31 安立股份有限公司 Small and low power consumption short pulse radar having time lag between transmission and reception arbitrarily variable with high time resolution and its control method
US20070066262A1 (en) * 2005-09-16 2007-03-22 Chinmaya Mishra Frequency synthesizer architecture for multi-band ultra-wideband system
TW200814538A (en) * 2006-09-07 2008-03-16 Realtek Semiconductor Corp Multiloop phase locked loop circuit
CN102147460A (en) * 2010-02-10 2011-08-10 中国科学院电子学研究所 System and method for receiving ultra wide band pulsed radar
CN102360070A (en) * 2011-06-10 2012-02-22 中国科学技术大学 Receiving apparatus for ultra wideband impulse signal and ultra wideband impulse radar system
JP2017028656A (en) * 2015-07-28 2017-02-02 富士通株式会社 Impulse transmitter, impulse receiver and impulse radio communication system
CN109490866A (en) * 2018-12-18 2019-03-19 北京无线电计量测试研究所 A kind of impulse radar system, receives, receiving/transmission method signal transmitting
CN110166046A (en) * 2019-05-20 2019-08-23 电子科技大学 Sequential equivalent system based on phase delay
CN110350892A (en) * 2019-07-24 2019-10-18 中北大学 A kind of time-delay mechanism and method based on DDS clock phase shift technology
CN110426974A (en) * 2019-08-08 2019-11-08 南京邮电大学 A kind of equivalent sampling control circuit based on quadrature phase gating

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1906499A (en) * 2004-10-14 2007-01-31 安立股份有限公司 Small and low power consumption short pulse radar having time lag between transmission and reception arbitrarily variable with high time resolution and its control method
US20070066262A1 (en) * 2005-09-16 2007-03-22 Chinmaya Mishra Frequency synthesizer architecture for multi-band ultra-wideband system
TW200814538A (en) * 2006-09-07 2008-03-16 Realtek Semiconductor Corp Multiloop phase locked loop circuit
CN102147460A (en) * 2010-02-10 2011-08-10 中国科学院电子学研究所 System and method for receiving ultra wide band pulsed radar
CN102360070A (en) * 2011-06-10 2012-02-22 中国科学技术大学 Receiving apparatus for ultra wideband impulse signal and ultra wideband impulse radar system
JP2017028656A (en) * 2015-07-28 2017-02-02 富士通株式会社 Impulse transmitter, impulse receiver and impulse radio communication system
CN109490866A (en) * 2018-12-18 2019-03-19 北京无线电计量测试研究所 A kind of impulse radar system, receives, receiving/transmission method signal transmitting
CN110166046A (en) * 2019-05-20 2019-08-23 电子科技大学 Sequential equivalent system based on phase delay
CN110350892A (en) * 2019-07-24 2019-10-18 中北大学 A kind of time-delay mechanism and method based on DDS clock phase shift technology
CN110426974A (en) * 2019-08-08 2019-11-08 南京邮电大学 A kind of equivalent sampling control circuit based on quadrature phase gating

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BO PANG等: ""Development of Wilkinson Power Divider for UWB Application"", 《2018 CROSS STRAIT QUAD-REGIONAL RADIO SCIENCE AND WIRELESS TECHNOLOGY CONFERENCE (CSQRWC)》 *
CHIEN-CHIH LIN等: ""A regenerative semi-dynamic frequency divider for mode-1 MB-OFDM UWB hopping carrier generation"", 《ISSCC. 2005 IEEE INTERNATIONAL DIGEST OF TECHNICAL PAPERS. SOLID-STATE CIRCUITS CONFERENCE, 2005.》 *
YDB1358396458: "《CSDN》", 5 June 2019 *
刘博: ""微小型超宽带收发技术研究"", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114167396A (en) * 2020-09-10 2022-03-11 Oppo广东移动通信有限公司 Control method based on ultra-wideband ranging and related device

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