CN110350892A - A kind of time-delay mechanism and method based on DDS clock phase shift technology - Google Patents
A kind of time-delay mechanism and method based on DDS clock phase shift technology Download PDFInfo
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- CN110350892A CN110350892A CN201910671269.5A CN201910671269A CN110350892A CN 110350892 A CN110350892 A CN 110350892A CN 201910671269 A CN201910671269 A CN 201910671269A CN 110350892 A CN110350892 A CN 110350892A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
Abstract
The invention belongs to sampling oscilloscope technical fields, more particularly to a kind of time-delay mechanism and method based on DDS clock phase shift technology, including triggering input module, DDS module, FPGA module, delay pulse synchronization module and sample trigger pulse output module, the input terminal for triggering input module and DDS module is connected；The output end of frequency measurement module and DDS module in FPGA module connects；The communication interface of control communication module and DDS module in FPGA module connects；DDS module is connect with the data input pin of delay pulse synchronization module；The pulse signal generation module of FPGA module is connect with the input end of clock of delay pulse synchronization module；The output end of delay pulse synchronization module is connect with sample trigger pulse output module.This programme is applied in sampling oscilloscope, can solve that delay precision in sequential equivalent is low, the small problem of range.
Description
Technical field
The invention belongs to sampling oscilloscope technical fields, and in particular to a kind of delay dress based on DDS clock phase shift technology
It sets and method.
Background technique
Equivalent Sampling Technology is a kind of non real-time sampling technique, can be used the sample frequency far below original signal to the period
Signal carries out undistorted sampling.Sampling oscilloscope can by a kind of sampler " sampler " using sequential equivalent technology
Upper frequency limit is expanded into tens GHz.Synchronous triggering signal input oscillograph time-based unit, according to when base corresponding to amount of delay
Stepping delay is carried out to sampling pulse, sampling pulse controls difference of the sampler by several periods after measured signal starting point
Position is sampled, and finally shows the pulse width of measured signal.The equivalent sampling that sequential equivalent may be implemented
Rate depends primarily on the delay precision of time-based unit.Used high-precision time-delay method compares in engineering for dual oblique wave at present
Method and Special time delay chip method.
Dual oblique wave comparison method such as article entitled " design of time-domain reflectomer high-precision step delay system " is described.This method essence
The delay pulse that the exportable step value of highest is 8.6ps is spent, although improving capacitor charging inelastic region corresponds to step delay amount
Non-uniform problem, but speed oblique wave noise itself is larger, can not be applied to in the higher equivalent sampling system of required precision.
It can produce the stepping delay precision of 10ps using Special time delay chip, monolithic reference time delay 10ns equally exists delay precision
The not high and small disadvantage of reference time delay.The promotion of the Equivalent Sample Oscilloscope sample frequency upper limit of delay precision lower limit, it is above-mentioned
The equivalent sampling rate that method is up to is 110GSa/s, has been unable to meet in engineering and carries out to 22GHz or more high-frequency signal
Equivalent sampling.
Summary of the invention
In view of the above technical problems, the present invention provides a kind of time-delay mechanism and method based on DDS clock phase shift technology, can
To improve the delay precision in equivalent sampling.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows:
A kind of time-delay mechanism based on DDS clock phase shift technology, including triggering input module, DDS module, FPGA module,
The input terminal of delay pulse synchronization module and sample trigger pulse output module, the triggering input module and DDS module connects；
The output end of frequency measurement module and DDS module in FPGA module connects；Control communication module and DDS module in FPGA module
Communication interface connection；The DDS module is connect with the data input pin of delay pulse synchronization module；The pulse signal of FPGA module
Generation module is connect with the input end of clock of delay pulse synchronization module；The output end and sample trigger of delay pulse synchronization module
Pulse output module connection.
The DDS module uses DDS chip AD9914.
A kind of time-delay method based on DDS clock phase shift technology, comprising the following steps:
S1, delay parameter determine: FPGA module receives stepping amount of delay Δ t and phase shift step number N；Export periodic pulse signal
D；
S2, generate clock signal clk: external trigger signal inputs in DDS module, and DDS is divided with integer value, when output
Clock signal CLK；CLK signal inputs FPGA frequency measurement module, and FPGA obtains cycle T i.e. reference time delay to signal CLK frequency measurement；
S3, DDS phase control words calculate；
S4, step number N to the FPGA that stepping phase shift is transmitted according to host computer, the parameter of each phase shift are incremented by with Δ θ, complete N
Secondary phase shift, obtains N Δ t amount of delay, and system is finished.
In the S3: FPGA carries out the determination of phase pushing figure Δ θ according to the delay time Δ t received；Delay time
Δ t account for frequency dividing after synchronised clock CLK signal cycle T ratio and phase shift value Δ θ it is identical as total 2 π accounting of phase value, thus may be used
It obtains:
Phase pushing figure is converted to the phase control words POW of DDS, calculation formula are as follows:
Wherein m is the planet phasing resolution ratio digit of DDS；
By the DDS chip of phase control words POW write-in U2, a phase shift operation is completed, DDS exports CLK_1 signal.
Compared with prior art, the present invention having the beneficial effect that
By the way that CLK signal is carried out n times phase shift by step value of Δ θ, believed using the pulse that the synchronous FPGA of CLK signal is generated
Relative ranks delay can be realized in number D.Precision time delay is obtained indirectly using the conversion of phase and time, and phase shifting parameter Δ θ is by upper
The clock cycle T three of delay parameter Δ t, sampling number and signal CLK that position machine transmits determine jointly.This programme is applied to take
In sample oscillograph, when setting sampling number is more, the CLK signal period is smaller, when required reference time delay is greater than cycle T, passes through DDS
It is divided with integral multiple, clk cycle T is expanded into integral multiple, so that cycle T is greater than required traversal time window time, solution sequence etc.
Delay precision is low in effect sampling, the small problem of range.
Using DDS technology tune external trigger signal, delay stepsize can flexible choice, compared to Special time delay chip generate
The delay stepsize of 10ps integral multiple has more flexible application.The input of high frequency external trigger signal can be achieved, it is sufficiently low shaking
The case where can produce 1ps delay precision, using high phase resolution ratio DDS chip can realize delay precision be higher than Special time delay core
Piece can get the equivalent sampling rate of 1TS/s or more in equivalent sampling system, improve the upper frequency limit of equivalent sampling.Using
FPGA controls whole system, is more advantageous to debugging and extension.Circuit system integrated level is high, signal strong antijamming capability.
Detailed description of the invention
Fig. 1 is connection principle block diagram of the invention；
Fig. 2 is d type flip flop clock phase tuning delay schematic diagram of the invention；
Fig. 3 is the sampling schematic diagram that the present invention is applied in sequential equivalent；
Wherein: U1 is triggering input module, and U2 is DDS module, and U3 is FPGA module, and U4 is delay pulse synchronization module,
U5 is sample trigger pulse output module.
Specific embodiment
The following is a clear and complete description of the technical scheme in the embodiments of the invention, it is clear that described embodiment
Only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, the common skill in this field
Art personnel every other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
As illustrated in fig. 1 and 2, a kind of time-delay mechanism based on DDS clock phase shift technology comprising triggering input module U1,
DDS module U2, FPGA module U3, delay pulse synchronization module U4 and sample trigger pulse output module U5.Trigger input module
U1 is connect with the input of DDS module U2；Frequency measurement module and DDS module U2 output in FPGA module U3 connect；FPGA module U3
In control communication module connect with the communication interface of DDS module U2；DDS module U2 and delay pulse synchronization module U4 data are defeated
Enter end connection；The pulse signal generation module of FPGA module U3 is connect with delay pulse synchronization module U4 input end of clock；Delay
Impulsive synchronization module U4 output end is connect with sample trigger pulse output module U5.
In figure, signal D is the narrow periodic pulse that FPGA is generated, D in signal input time delay impulsive synchronization module U4
Flip-flop data input terminal；Signal CLK is that DDS module U2 frequency tuning exports the clock signal synchronous with external trigger signal,
D type flip flop input end of clock in input time delay impulsive synchronization module U4；Signal Q is that d type flip flop is same in the synchronous mould U4 of delay pulse
Walk the delay sample trigger pulse signal of output.
Above-mentioned each circuit module composition and Functional Design are as follows:
1. triggering input module U1
Triggering input module is used to receive the same frequency coaxially separated by measured signal or synchronizes outer touching with integral multiple frequency dividing
Analog signal is sent out, and single-ended transfer difference processing, U1 connection DDS module U2 are carried out to the signal.
2.DDS module U2
DDS module U2 includes DDS chip and its peripheral function circuit, output filter circuit.In the present invention, in order to realize height
The input of frequency outer triggering signal, realizes the delay of subpicosecond magnitude, selects internal clock speed 3.5GSPS, 16 planet phasings
Resolution ratio, 32 bit frequency control words and the DDS chip for being internally integrated 12 DAC.The DDS has fractional frequency division mode, frequency tune
Humorous precision can reach skin hertz magnitude, meet required precision of the present invention.The functions of modules is that external trigger signal is joined according to phase shift
Number carries out frequency dividing and phase shift operation, gives delay pulse synchronization module U4 for the signal after tuning as clock signal transmission.
3.FPGA module U3
FPGA module U3 mainly realizes three functions: carrying out frequency measurement to the signal CLK of DDS module U2 output；It receives
The retardation Δ t of host computer transmission, is calculated frequency, phase control words in conjunction with clk cycle T and DDS register is written；It generates
Fixed cycle low frequency pulse signal D inputs d type flip flop input terminal in U4.
4. delay pulse synchronization module U4
Delay pulse synchronization module U4 is made of d type flip flop circuit.The low frequency pulse signal D that FPGA is generated inputs this module
The data input pin of d type flip flop, the clock end of the signal CLK input d type flip flop of DDS tuning operation.It realizes and is delayed in this module
Signal output, it is sample trigger pulse signal that d type flip flop, which exports synchronization signal,.It is up to using input frequency in the present invention
The d type flip flop of 6GHz possesses extremely low propagation delay and phase noise.
5. sample trigger pulse output module U5
Sample trigger pulse output module U5 function provides driving force for the sample trigger pulse signal that U4 module generates, into
Narrow pulse signal is sent into after line level matching, circuit occurs, generate sample-pulse signal control sampler and be sampled.
As shown in figure 3, external trigger signal inputs DDS tuning operation synchronization signal CLK.The recurrent pulse letter generated through FPGA
Number input d type flip flop data terminal, CLK are used as clock signal input d type flip flop, synchronize rear output pulse signal Q failing edge correspondence
Sampling location is first point of measured signal.CLK signal phase shift is sampled after d type flip flop synchronizes by DDS in next step
Trigger pulse is Q_1, and failing edge samples to obtain second point in the failing edge compared with the failing edge delay Δ t of signal Q pulse,
2 Δ θ of CLK signal phase shift is similarly obtained into Q_2, failing edge is sampled compared with Q pulse signal failing edge 2 Δ t of delay in the failing edge
To third point.The waveform that complete time window can be traversed through n times phase shift operation realizes N Δ t delay, sequence arrangement sampling
Point can restore waveform.
For the more intuitive specific elaboration present invention, time-delay method of the present embodiment based on DDS clock phase shift technology, base
Inputting in external trigger signal is 800MHz, comprising the following steps:
S1, delay parameter is determined:
Retardation Δ t is set as 5ps, step value 1023 in FPGA；
FPGA output frequency is the recurrent pulse D of 40KHz.
S2, clock signal clk is generated:
As DDS in external trigger input U2, since DDS output frequency maximum value is the 40% of frequency input signal value,
8 divide operations are carried out to it, the frequency through DDS frequency tuning output clock signal clk is 100MHz.
CLK signal is inputted into d type flip flop clock end, while FPGA frequency measurement obtains its cycle T 1=10ns.
S3, DDS phase control words calculate:
Δ t is converted into phase offset parameter:
It is converted into phase control words:
Give up decimal place and be converted to hexadecimal and obtain POW=0020, inputs DDS chip operation register-bit.DDS output
The time delayed signal of one unit of phase shift completes a phase shift operation.
S4, transmission phase shift step number command N=1023, system need to 0.18 degree for step units complete 1023 phase shifts behaviour
Make.N-th phase shift parameter is incremented by Δ θN=1023 × Δ θ=184.14 degree, POW=82F1, in this delay parameter and phase shift
Reference time delay is 5.115ns in the case of step number, and system is finished.
This programme is applied in sampling oscilloscope, and when setting sampling number is more, the CLK signal period is smaller, required delay
It when range is greater than cycle T, is divided by DDS with integral multiple, clk cycle T is expanded into integral multiple, solve to prolong in sequential equivalent
Shi Jingdu is low, the small problem of range.
Only presently preferred embodiments of the present invention is explained in detail above, but the present invention is not limited to above-described embodiment,
Within the knowledge of a person skilled in the art, it can also make without departing from the purpose of the present invention each
Kind variation, various change should all be included in the protection scope of the present invention.
Claims (4)
1. a kind of time-delay mechanism based on DDS clock phase shift technology, it is characterised in that: including triggering input module, DDS module,
FPGA module, delay pulse synchronization module and sample trigger pulse output module, it is described triggering input module and DDS module it is defeated
Enter end connection；The output end of frequency measurement module and DDS module in FPGA module connects；Control communication module in FPGA module with
The communication interface of DDS module connects；The DDS module is connect with the data input pin of delay pulse synchronization module；FPGA module
Pulse signal generation module connect with the input end of clock of delay pulse synchronization module；The output end of delay pulse synchronization module
It is connect with sample trigger pulse output module.
2. a kind of time-delay mechanism based on DDS clock phase shift technology according to claim 1, it is characterised in that: the DDS
Module uses DDS chip AD9914.
3. a kind of time-delay method based on DDS clock phase shift technology, which comprises the following steps:
S1, delay parameter determine: FPGA module receives stepping amount of delay Δ t and phase shift step number N；Export periodic pulse signal D；
S2, generate clock signal clk: external trigger signal inputs in DDS module, and DDS is divided with integer value, output clock letter
Number CLK；CLK signal inputs FPGA frequency measurement module, and FPGA obtains cycle T i.e. reference time delay to signal CLK frequency measurement；
S3, DDS phase control words calculate；
S4, step number N to the FPGA that stepping phase shift is transmitted according to host computer, the parameter of each phase shift are incremented by with Δ θ, are completed n times and are moved
Phase, obtains N Δ t amount of delay, and system is finished.
4. a kind of time-delay method based on DDS clock phase shift technology according to claim 3, which is characterized in that the S3
In:
FPGA carries out the determination of phase pushing figure Δ θ according to the delay time Δ t received；Delay time Δ t is accounted for after frequency dividing together
Ratio and the phase shift value Δ θ for walking the cycle T of CLK signal are identical as total 2 π accounting of phase value, this makes it possible to obtain:
Phase pushing figure is converted to the phase control words POW of DDS, calculation formula are as follows:
Wherein m is the planet phasing resolution ratio digit of DDS；
By the DDS chip of phase control words POW write-in U2, a phase shift operation is completed, DDS exports CLK_1 signal.
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Cited By (4)
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| CN111413677A (en) * | 2020-02-27 | 2020-07-14 | 湖南师范大学 | Difference frequency-delay type receiving and transmitting clock synchronization method, circuit and ultra-wideband pulse radar receiving device |
| CN112436825A (en) * | 2020-10-15 | 2021-03-02 | 中北大学 | High-precision combined delay system and method based on FPGA and delay chip |
| CN113009201A (en) * | 2021-02-24 | 2021-06-22 | 普源精电科技股份有限公司 | Electric signal sampling device |
| CN113064213A (en) * | 2021-03-10 | 2021-07-02 | 欧姆龙(上海)有限公司 | Light receiving device and photoelectric sensor |
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| CN112436825A (en) * | 2020-10-15 | 2021-03-02 | 中北大学 | High-precision combined delay system and method based on FPGA and delay chip |
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