CN202663383U

CN202663383U - S-band coherence multi-frequency signal source

Info

Publication number: CN202663383U
Application number: CN 201220296740
Authority: CN
Inventors: 陈泽宗; 陈曦; 李雨钟; 赵晨
Original assignee: Wuhan University WHU
Current assignee: Wuhan University WHU
Priority date: 2012-06-25
Filing date: 2012-06-25
Publication date: 2013-01-09
Anticipated expiration: 2022-06-25

Abstract

The utility model provides an S-band coherence multi-frequency signal source, which comprises a crystal oscillator, a clock allocation circuit, a direct digital frequency synthesizer and a phase-locked loop; the clock allocation circuit comprises a single-end clock allocation chip, a single-end input rotary differential output clock buffering chip, a differential clock allocation electric chip and a clock frequency divider; the crystal oscillator is connected with the single-end clock allocation chip; the single-end clock allocation chip is respectively connected with the clock frequency divider and the single-end input rotary differential output clock buffering chip; the differential clock allocation chip and the single-end input rotary differential output clock buffering chip are respectively connected with the direct digital frequency synthesizer; and the clock frequency divider is connected with the phase-locked loop. By adopting an all-digital-control way, convenience, flexibility, stability and precision are achieved; a composite-type clock allocation circuit is adopted, so that the interference resistance of the circuit is strong; and a shield enclosure is adopted for isolating signals, so that the signal is pure.

Description

A kind of S-band multiple-frequency signal source of being concerned with

Technical field

The utility model relates to the relevant multiple-frequency signal source of a kind of S-band.

Background technology

At present, the main method that produces signal source has direct oscillator, frequency-doubling method, based on frequency synthesizer method, Direct Digital Frequency Synthesizers and the Direct Digital Frequency Synthesizers of phase-locked loop and the method for phase-locked loop combination; Wherein direct oscillator adopts magnetron, directly produces needed frequency signal, and the signal frequency stability that the method produces is low, and the coherence is poor, is difficult to adjust frequency of oscillation; Frequency-doubling method is the signal that produces first lower frequency with the high-precision crystal oscillator, passes through afterwards the several times frequency multiplication on required frequency range, and the method is simple, and stability is high, but output frequency can only be the integral multiple of crystal oscillation frequency; Can produce the signal of required frequency based on the frequency synthesizer method of phase-locked loop, its shortcoming is that phase noise is larger, has reduced the coherence of system; Direct Digital Frequency Synthesizers can produce the less signal of phase noise, exports spuious letter few, little and control flexibly, its shortcoming is the restriction that the highest frequency of output signal is subject to clock signal frequency, can't directly produce at present the signal of S-band; The basic principle of the method for Direct Digital Frequency Synthesizers and phase-locked loop combination is, produce first the signal of certain frequency with Direct Digital Frequency Synthesizers, generate again the signal of higher frequency by phase-locked loop, the method can produce the signal of assigned frequency, its shortcoming is that phase noise is larger, device is more, complex circuit.

The utility model content

For the problem that background technology exists, the utility model provides a kind of S-band multiple-frequency signal source of being concerned with.

For solving the problems of the technologies described above, the utility model adopts following technical scheme.

A kind of S-band multiple-frequency signal source of being concerned with comprises crystal oscillator, clock distribution circuit, Direct Digital Frequency Synthesizers, phase-locked loop; Clock distribution circuit comprises that single-ended clock distribution chip, single-ended input slip divide output clock buffer chip, differential clocks to divide distribution chip, Clock dividers; Crystal oscillator is connected with single-ended clock distribution chip; Single-ended clock distribution chip respectively with Clock dividers be connected the input slip and divide the output clock buffer chip to be connected; Differential clocks divides distribution chip, single-ended input slip to divide the output clock buffer chip to link to each other with Direct Digital Frequency Synthesizers respectively; Clock dividers links to each other with phase-locked loop.

Described Direct Digital Frequency Synthesizers, phase-locked loop are respectively arranged with independently radome.

Described Direct Digital Frequency Synthesizers model is AD9910, the phase-locked loop model is PLL400, the crystal oscillator model is SDH4005C-2, single-ended clock distribution chip model is ICS524, it is NB6L11 that single-ended input slip divides output clock buffer chip model, it is NB6N11 that differential clocks distributes the chip model, and the Clock dividers model is ICS558.

Comprise two Direct Digital Frequency Synthesizers and two phase-locked loops.

During use, Direct Digital Frequency Synthesizers and phase-locked loop all are connected with the host computer interface, by the parameter of PC control signal source, and Direct Digital Frequency Synthesizers and phase-locked loop all adopt Surface Acoustic Wave Filter to carry out filtering, adopts the SMA radio frequency (RF) coaxial connector to carry out output signal.

Compared with prior art, the utlity model has following advantage and beneficial effect:

1, the utility model adopts the mode of digital control, and the parameter of signal source can be changed by the host computer remote control, can produce simultaneously 4 road signals, and is convenient, flexible, accurately stable.

2, the utility model adopts the combined type clock distribution circuit, strengthens signal quality and the antijamming capability of clock signal, guarantees the coherence of signal source emission FM signal, local oscillator FM signal, local oscillator frequency-fixed signal.

3, the utility model employing Surface Acoustic Wave Filter and radome carry out the isolation between each signal, make signal pure, and Spurious Free Dynamic Range is up to 80dBc.

Description of drawings

Fig. 1 is simple structure schematic diagram of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with embodiment shown in the drawings.

As shown in drawings, the utility model comprises crystal oscillator, clock distribution circuit, Direct Digital Frequency Synthesizers, phase-locked loop; Clock distribution circuit comprises that single-ended clock distribution chip, single-ended input slip divide output clock buffer chip, differential clocks to divide distribution chip, Clock dividers; Crystal oscillator is connected with single-ended clock distribution chip; The output of single-ended clock distribution chip respectively with Clock dividers be connected the input slip and divide the input of output clock buffer chip to be connected; Differential clocks divides the output of distribution chip to divide the output of output clock buffer chip to link to each other with Direct Digital Frequency Synthesizers respectively with single-ended input slip; The output of Clock dividers links to each other with phase-locked loop.

Direct Digital Frequency Synthesizers and phase-locked loop are respectively arranged with independently radome; Comprise two Direct Digital Frequency Synthesizers and two phase-locked loops in the present embodiment; The Direct Digital Frequency Synthesizers model is AD9910, the phase-locked loop model is PLL400, the crystal oscillator model is SDH4005C-2, single-ended clock distribution chip model is ICS524, it is NB6L11 that single-ended input slip divides output clock buffer chip model, it is NB6N11 that differential clocks distributes the chip model, and the Clock dividers model is ICS558; Direct Digital Frequency Synthesizers and phase-locked loop all are connected with the host computer interface, parameter by the PC control signal source, and Direct Digital Frequency Synthesizers and phase-locked loop all adopt Surface Acoustic Wave Filter to carry out filtering, adopt the SMA radio frequency (RF) coaxial connector to carry out output signal.

The clock of crystal oscillator output produces the synchronous clock signal of two-way through single-ended clock distribution chip and inputs to respectively single-ended input slip and divide output clock buffer chip and Clock dividers in the present embodiment, single-ended input slip divides the output clock buffer chip that input signal is changed into the two-way differential clock signal to access respectively two Direct Digital Frequency Synthesizers, for it provides work clock; Clock dividers changes into the synchronous sub-frequency clock signal of two-way with input signal and accesses respectively two phase-locked loops, for it provides work clock; Therefore, the work clock of two Direct Digital Frequency Synthesizers and two phase-locked loops remains the Phase synchronization relation.

In the present embodiment, the synchronous output pin access differential of the multi-disc of Direct Digital Frequency Synthesizers clock distribution chip, divide distribution chip to produce the synchronous differential clock signal of two-way by differential clocks and access respectively two Direct Digital Frequency Synthesizers, by above-mentioned connection, can open the multi-disc synchronizing function of Direct Digital Frequency Synthesizers, realize synchronous working between the sheet of two Direct Digital frequency frequency synthesizers, make synchronization accuracy reach picosecond.

Claims

1. the relevant multiple-frequency signal source of a S-band is characterized in that: comprise crystal oscillator, clock distribution circuit,

Direct Digital Frequency Synthesizers, phase-locked loop; Clock distribution circuit comprises that single-ended clock distribution chip, single-ended input slip divide output clock buffer chip, differential clocks to divide distribution chip, Clock dividers;

Crystal oscillator is connected with single-ended clock distribution chip; Single-ended clock distribution chip respectively with Clock dividers

Be connected the input slip and divide the output clock buffer chip to connect; Differential clocks divides distribution chip, single-ended input slip to divide the output clock buffer chip to link to each other with Direct Digital Frequency Synthesizers respectively; Clock dividers links to each other with phase-locked loop.

2. the relevant multiple-frequency signal source of a kind of S-band according to claim 1, it is characterized in that: described Direct Digital Frequency Synthesizers, phase-locked loop are respectively arranged with independently radome.

3. the relevant multiple-frequency signal source of a kind of S-band according to claim 1, it is characterized in that: described Direct Digital Frequency Synthesizers model is AD9910, the phase-locked loop model is PLL400, the crystal oscillator model is SDH4005C-2, single-ended clock distribution chip model is ICS524, it is NB6L11 that single-ended input slip divides output clock buffer chip model, and it is NB6N11 that differential clocks distributes the chip model, and the Clock dividers model is ICS558.

4. the relevant multiple-frequency signal source of a kind of S-band according to claim 1 is characterized in that: comprise two Direct Digital Frequency Synthesizers and two phase-locked loops.