CN115250215B - Multi-interface time baseband chip - Google Patents
Multi-interface time baseband chip Download PDFInfo
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- CN115250215B CN115250215B CN202210724833.7A CN202210724833A CN115250215B CN 115250215 B CN115250215 B CN 115250215B CN 202210724833 A CN202210724833 A CN 202210724833A CN 115250215 B CN115250215 B CN 115250215B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
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Abstract
The application relates to the technical field of baseband chips, in particular to a multi-interface time baseband chip which comprises an interface module, a link processing module, a phase-locked loop module, a processor module and a T domain module, wherein the interface module, the phase-locked loop module, the processor module and the T domain module are respectively connected with the link processing module, and the processor module and the phase-locked loop module are respectively connected with the T domain module; the interface module comprises an atomic clock frequency interface, a military current time input/output interface, a multi-compatible B-code time input/output interface and a high-precision second pulse input/output interface. The time baseband chip can receive and process various signal sources in different forms, and particularly can be adapted to various time-frequency devices on the basis of being compatible with military current time codes and multi-compatible B codes, so that the applicability of the time baseband chip is greatly improved.
Description
Technical Field
The application relates to the technical field of baseband chips, in particular to a multi-interface time baseband chip.
Background
Baseband refers to the frequency band inherent to the original electrical signal that is sent by the source without modulation, called the baseband for short. The baseband chip is used to synthesize the baseband signal to be transmitted or decode the received baseband signal.
With respect to the related art in the above, the inventors consider that there are the following technical drawbacks: a Time baseband chip generally can only perform codec processing on a specific signal source, in other words, if a plurality Of different signal sources need to be processed, for example, if a military TOD code (TOD, time Of Day, current Time), a multi-compatible B code (irig_b code), a high-speed 1PPS, and other signal sources Of different forms need to be processed, different Time baseband chips need to be equipped, which results in poor applicability Of one Time baseband chip, and thus needs to be further improved.
Disclosure of Invention
In order to improve applicability of the time baseband chip, the application provides a multi-interface time baseband chip.
The multi-interface time baseband chip provided by the application adopts the following technical scheme:
the multi-interface time baseband chip comprises an interface module, a link processing module, a phase-locked loop module, a processor module and a T domain module, wherein:
the interface module, the phase-locked loop module, the processor module and the T domain module are respectively connected with the link processing module, and the processor module and the phase-locked loop module are respectively connected with the T domain module;
the interface module comprises a military current time input/output interface, a multi-compatible B code time input/output interface and a high-precision second pulse input/output interface, different forms of signal sources are input and output through the interface module, the link processing module is used for receiving the corresponding signal sources input by the interface module according to IO information sent by the processor module, processing the signal sources into time information meeting the standard required by the T domain module and sending the time information to the T domain module, the phase-locked loop module is used for generating a global clock, and the T domain module generates time difference information based on the global clock and sends the time difference information to the processor module.
By adopting the technical scheme, the time baseband chip can receive and process signal sources in various different forms, and particularly can be adapted to various time-frequency devices on the basis of being compatible with military current time codes and multi-compatible B codes, so that the applicability of the time baseband chip is greatly improved.
Optionally, the interface module further includes an atomic clock frequency interface, where the atomic clock frequency interface is configured to receive an atomic clock frequency signal and send the atomic clock frequency signal to the link processing module, and process, by using the link processing module, the atomic clock frequency signal into single-ended frequency information that meets a standard required by the phase-locked loop module and send the single-ended frequency information to the phase-locked loop module.
By adopting the technical scheme, the frequency accuracy of the global clock generated by the phase-locked loop module can be improved, so that the working reliability of the multi-interface time baseband chip is improved.
Optionally, the interface module is connected with the link processing module through a link bus, and a signal source corresponding to the IO information sent by the processor module is sent to the link processing module through the link bus.
By adopting the technical scheme, the link processing module can selectively receive and process the target signal source by setting the link bus, thereby being beneficial to ensuring the parallel processing capability of the time baseband chip.
Optionally, the phase-locked loop module includes a voltage-controlled oscillator, a counter, a filter, and a phase shifter that are connected to each other.
Optionally, the system further comprises an ethernet interface module, wherein the ethernet interface module is connected with the processor module, and the ethernet interface module is used for accessing ethernet services.
Optionally, the system further comprises a peripheral controller module, wherein the peripheral controller module is connected with the processor module and is used for accessing control equipment.
Optionally, the peripheral controller module includes a USB interface, a keyboard interface, and a mouse interface.
Optionally, the system further comprises a Beidou link module, wherein the Beidou link module is connected with the T domain module and is used for time service of the T domain module.
Optionally, the system further comprises a state information module, wherein the state information module is connected with the T domain module and is used for displaying the working state of the time baseband chip.
Optionally, the processor module comprises an APU dual core processor.
From the above, the beneficial technical effects of the present application include: the time baseband chip can receive and process various signal sources in different forms, and particularly can be adapted to various time-frequency devices on the basis of being compatible with the military current time code and the multi-compatible B code, so that the applicability of the time baseband chip is greatly improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
Fig. 1 is a schematic block diagram of a multi-interface time baseband chip disclosed for embodiments of the present application.
Reference numerals illustrate: 100. an interface module; 200. a link processing module; 300. a processor module; 400. a phase-locked loop module; 500. a T domain module; 510. the Beidou link module; 520. the Beidou information receiving port; 530. a status information module; 600. an Ethernet interface module; 700. and a peripheral controller module.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
Referring to fig. 1, a schematic block diagram of a multi-interface time baseband chip disclosed in an embodiment of the present application, where the multi-interface time baseband chip includes an interface module 100, a link processing module 200, a phase-locked loop module 400, a processor module 300, and a T-domain module 500, where: the interface module 100, the phase-locked loop module 400, the processor module 300 and the T-domain module 500 are respectively connected with the link processing module 200, and the processor module 300 and the phase-locked loop module 400 are respectively connected with the T-domain module 500;
specifically, the interface module 100 includes a military current time input output interface (i.e. the TOD interface shown in fig. 1), a multi-compatible B-code time input output interface (i.e. the IRIGB interface shown in fig. 1), and a high-precision pulse per second input output interface (i.e. the 1PPS interface shown in fig. 1), different forms of signal sources are input and output through the interface module 100, the link processing module 200 is configured to receive the signal sources input by the corresponding interface module 100 according to the IO information sent by the processor module 300, process the signal sources into time information meeting the standard required by the T-domain module 500, send the time information to the T-domain module 500, the phase-locked loop module 400 is configured to generate a global clock, and the T-domain module 500 generates time difference information based on the global clock and sends the time difference information to the processor module 300.
The IO information refers to a type of a signal source to be received and processed, for example, if the signal source to be received and processed is a military current time input by the interface module 100, the IO information corresponds to the military current time, and if the signal source to be received and processed is required to simultaneously receive and process a multi-compatible B-code time and a military current time, the IO information corresponds to the multi-compatible B-code time and the military current time.
By adopting the technical scheme, the interface module 100 can simultaneously receive a plurality of signal sources in different forms, the link processing module 200 can selectively receive and process one or more than two signal sources, and under the combined action of the interface module 100, the link processing module 200, the phase-locked loop module 400, the processor module 300 and the T domain module 500, the encoding and decoding processes of the plurality of signal sources are realized, so that the applicability of the time baseband chip is greatly improved.
Specifically, in some embodiments, the interface module 100 is connected to the link processing module 200 through a link bus, and a signal source corresponding to the IO information sent by the processor module 300 is sent to the link processing module 200 through the link bus.
The link bus includes an external link distributor, and a signal source corresponding to the IO information sent by the processor module 300 is sent to the link processing module 200 through the external link distributor.
Further, in some embodiments, the interface module 100 further includes an atomic clock frequency interface (i.e. the frq_10m interface in fig. 1), where the atomic clock frequency interface is configured to receive an atomic clock frequency signal and send the atomic clock frequency signal to the link processing module 200, and process the atomic clock frequency signal by the link processing module 200 to be single-ended frequency information meeting the standard required by the phase-locked loop module 400, and send the single-ended frequency information to the phase-locked loop module 400, so as to improve the frequency accuracy of the global clock generated by the phase-locked loop module 400, thereby improving the operational reliability of the multi-interface time baseband chip.
The atomic clock frequency interface is compatible with various electrical standards such as LVCOM33, LVCMOS25, LVTTL33, LVDS, sinusoidal signals, and the like.
Specifically, in some embodiments, the phase-locked loop module 400 includes a voltage-controlled oscillator, a counter, a filter, and a phase shifter that are connected to each other. Specifically, the counter in the embodiment of the application includes a plurality of fractional counters and a plurality of fractional counters, the filter adopts a low-pass filter, and a global clock of the multi-interface time baseband chip is generated under the combined action of the voltage-controlled oscillator, the counter, the filter and the phase shifter.
Further, in some embodiments, the multi-interface time baseband chip further includes an ethernet interface module 600, where the ethernet interface module 600 is connected to the processor module 300, and the ethernet interface module 600 is used for accessing ethernet services, and meanwhile, connection between the multi-interface time baseband chip and the host computer can be achieved through ethernet.
Further, in some embodiments, the multi-interface time baseband chip further includes a peripheral controller module 700, where the peripheral controller module 700 is connected to the processor module 300, and the peripheral controller module 700 is used for accessing a control device. The control device is accessed through the peripheral controller module 700 so that a user can perform a custom operation through the control device.
For example, in some embodiments, the peripheral controller module 700 may include a USB interface, a keyboard interface, and a mouse interface, where the connection between the external USB device and the multi-interface time baseband chip is implemented through the USB interface, the connection between the external keyboard device and the time baseband chip is implemented through the keyboard interface, and the connection between the external mouse device and the time baseband chip is implemented through the mouse interface.
Further, in some embodiments, the multi-interface time baseband chip further includes a beidou link module 510, where the beidou link module 510 is connected with the T-domain module 500, and the beidou link module 510 receives, through the beidou information receiving port 520, beidou information sent by the beidou receiver so as to time service the T-domain module 500.
Further, in some embodiments, the multi-interface time baseband chip further includes a status information module 530, where the status information module 530 is connected to the T-domain module 500, and the status information module 530 is configured to display an operating status of the time baseband chip. Specifically, the status information module 530 may be configured as an LED array controller, which controls the blinking of each LED to indicate the operating status of the time baseband chip based on the system status information provided by the T-domain module 500.
Further, in some embodiments, the processor module 300 described above comprises an APU dual core processor. Specifically, to ensure good performance of the time baseband chip, the processor module 300 in the embodiment of the present application employs an APU dual-core processor with a maximum main frequency of 866 MHz.
The implementation principle of the multi-interface time baseband chip in the embodiment of the application is as follows: the interface module 100 receives one or more different types of signal sources, a user can define IO information of the processor module 300 through the peripheral controller module 700, the link bus selects a corresponding signal source according to the IO information provided by the processor module 300 and sends the signal source to the link processing module 200, the link processing module 200 processes the signal source and sends a processing result to the T domain module 500 or the phase-locked loop module 400, the corresponding time difference information is obtained through the T domain module 500 and sent to the processor module 300, and the processor module 300 sends the time difference information to the upper computer through the ethernet interface module 600 for statistical analysis.
The signal sources input from the multi-compatible B-code time input/output interface, the military current time input/output interface or the high-precision second pulse input/output interface are routed to the link processing module 200 through the link bus, the link processing module 200 performs protocol processing on the signal sources and sends the processing result to the T domain module 500, the T domain module 500 obtains corresponding time difference information, the T domain module 500 sends the time difference information to the processor module 300, and the processor module 300 sends the time difference information to the upper computer through the ethernet interface module 600 for statistical analysis.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, and, for example, the division of the units or modules is merely a logical function division, and there may be additional divisions when actually implemented, and, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (9)
1. The multi-interface time baseband chip is characterized by comprising an interface module, a link processing module, a phase-locked loop module, a processor module and a T domain module, wherein:
the interface module, the phase-locked loop module, the processor module and the T domain module are respectively connected with the link processing module, and the processor module and the phase-locked loop module are respectively connected with the T domain module;
the interface module comprises a military current time input/output interface, a multi-compatible B code time input/output interface and a high-precision second pulse input/output interface, different forms of signal sources are input and output through the interface module, the link processing module is used for receiving the corresponding signal sources input by the interface module according to IO information sent by the processor module, processing the signal sources into time information meeting the standard required by the T domain module and sending the time information to the T domain module, the phase-locked loop module is used for generating a global clock, and the T domain module generates time difference information based on the global clock and sends the time difference information to the processor module;
the interface module further comprises an atomic clock frequency interface, wherein the atomic clock frequency interface is used for receiving an atomic clock frequency signal and sending the atomic clock frequency signal to the link processing module, and the atomic clock frequency signal is processed into single-ended frequency information meeting the standard required by the phase-locked loop module through the link processing module and sent to the phase-locked loop module.
2. The multi-interface time baseband chip of claim 1, wherein the interface module is connected to the link processing module through a link bus, and a signal source corresponding to the IO information sent by the processor module is sent to the link processing module through the link bus.
3. The multi-interface time baseband chip of claim 1, wherein the phase-locked loop module comprises a voltage-controlled oscillator, a counter, a filter, and a phase shifter connected to each other.
4. The multi-interface time baseband chip of claim 1, further comprising an ethernet interface module, the ethernet interface module coupled to the processor module, the ethernet interface module configured to access ethernet services.
5. The multi-interface time baseband chip of claim 1, further comprising a peripheral controller module coupled to the processor module, the peripheral controller module configured to access a control device.
6. The multi-interface time baseband chip of claim 5, wherein the peripheral controller module comprises a USB interface, a keyboard interface, and a mouse interface.
7. The multi-interface time baseband chip of claim 1, further comprising a beidou link module, wherein the beidou link module is connected with the T-domain module, and the beidou link module is configured to time the T-domain module.
8. The multi-interface time baseband chip of claim 1, further comprising a status information module, wherein the status information module is connected to the T-domain module, and the status information module is configured to display an operating status of the time baseband chip.
9. The multi-interface time baseband chip of claim 1, wherein the processor module comprises an APU dual core processor.
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| CN202210724833.7A CN115250215B (en) | 2022-06-23 | 2022-06-23 | Multi-interface time baseband chip |
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| CN202210724833.7A CN115250215B (en) | 2022-06-23 | 2022-06-23 | Multi-interface time baseband chip |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5586308A (en) * | 1994-10-19 | 1996-12-17 | Advanced Micro Devices, Inc. | Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto |
| CN202663383U (en) * | 2012-06-25 | 2013-01-09 | 武汉大学 | S-band coherence multi-frequency signal source |
| CN105681703A (en) * | 2016-01-19 | 2016-06-15 | 浪潮集团有限公司 | OSD chip compatible with multiple interfaces |
| CN106301749A (en) * | 2016-07-21 | 2017-01-04 | 芜湖航飞科技股份有限公司 | A kind of time synchronization device for electrical power system based on dipper system |
| CN113114240A (en) * | 2021-04-12 | 2021-07-13 | 湖南师范大学 | Pilot frequency high-precision rubidium atomic frequency standard generation system based on Beidou satellite signals |
| CN214427928U (en) * | 2021-05-08 | 2021-10-19 | 北京六合联珩科技有限公司 | Multichannel data acquisition circuit board and have its data acquisition synchronization system |
| CN114488203A (en) * | 2022-01-28 | 2022-05-13 | 航天恒星空间技术应用有限公司 | High-precision time keeping and network time service system and method based on Beidou signals |
-
2022
- 2022-06-23 CN CN202210724833.7A patent/CN115250215B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5586308A (en) * | 1994-10-19 | 1996-12-17 | Advanced Micro Devices, Inc. | Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto |
| CN202663383U (en) * | 2012-06-25 | 2013-01-09 | 武汉大学 | S-band coherence multi-frequency signal source |
| CN105681703A (en) * | 2016-01-19 | 2016-06-15 | 浪潮集团有限公司 | OSD chip compatible with multiple interfaces |
| CN106301749A (en) * | 2016-07-21 | 2017-01-04 | 芜湖航飞科技股份有限公司 | A kind of time synchronization device for electrical power system based on dipper system |
| CN113114240A (en) * | 2021-04-12 | 2021-07-13 | 湖南师范大学 | Pilot frequency high-precision rubidium atomic frequency standard generation system based on Beidou satellite signals |
| CN214427928U (en) * | 2021-05-08 | 2021-10-19 | 北京六合联珩科技有限公司 | Multichannel data acquisition circuit board and have its data acquisition synchronization system |
| CN114488203A (en) * | 2022-01-28 | 2022-05-13 | 航天恒星空间技术应用有限公司 | High-precision time keeping and network time service system and method based on Beidou signals |
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