CN111313869B - Clock switching circuit of gigabit Ethernet transceiver - Google Patents
Clock switching circuit of gigabit Ethernet transceiver Download PDFInfo
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- CN111313869B CN111313869B CN202010066228.6A CN202010066228A CN111313869B CN 111313869 B CN111313869 B CN 111313869B CN 202010066228 A CN202010066228 A CN 202010066228A CN 111313869 B CN111313869 B CN 111313869B
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- H03—ELECTRONIC CIRCUITRY
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Abstract
The invention provides a clock switching circuit of a gigabit Ethernet transceiver, which realizes smooth switching of different clock domains through a three-level synchronization and interlocking mechanism, avoids the risk of generating burrs and metastable states during clock switching across the clock domains, ensures the correctness of the circuit function, can provide a correct output clock during reset, and ensures the logic function of a chip during reset.
Description
Technical Field
The invention belongs to the field of computer communication and network, relates to a clock switching circuit of a gigabit Ethernet transceiver, and is particularly suitable for the fields of Ethernet controllers, network servers, computer data storage systems and the like. Such as data service centers, large switches, etc. The method is suitable for circuit design with high integration level and low overhead.
Background
The gigabit Ethernet supports two transceivers of gphy and serdes, and the gphy supports three rates of 10/100/1000 Mbps; when the mobile terminal works, a user can select between the gphy and the servers according to the requirement, and the communication speed of the gphy can be switched among 10M, 100M and 1000M. However, selecting different transceivers and different communication rates involves dynamic switching of clocks across clock domains, and how to realize correct switching of clocks across clock domains while avoiding metastability or clock glitches is a key problem to be solved since 3 switching clocks and control signals come from different clock domains.
In the prior art, a MUX selection circuit is generally selected, and the method is generally applied to a circuit with relaxed requirements on a clock system; however, due to the difference in the frequency and phase of the input clock and the asynchronism between the switching signal and the clock, glitches are easily generated in the output clock during the switching process.
Patent document "a glitch-free switching circuit supporting N-way clocks (CN 201610008589.9)" discloses a clock switching scheme, but the number N of clocks to be switched must be 2 powers, and when N is an odd number, the scheme cannot be used.
Patent documents "a clock switching circuit (ZL 200710098961.0)", "a clock switching circuit (ZL 200810067535.5)", "a clock switching circuit (ZL 200810068164.2)" and "a clock switching method and a clock switching device (ZL 201010560049.4)" all disclose glitch-free clock switching schemes, but the above various schemes only support dynamic switching of two clocks.
Patent document "a clock switching device (ZL 201410310730.1)" proposes a glitch-free switching scheme supporting multiple clocks, but this scheme only allows sequential switching of the clock frequency from high to low or from low to high, and does not support a jump-type clock switching.
None of the above prior art techniques is able to generate the correct output clock based on the functional requirements of the gigabit ethernet circuit during reset.
Disclosure of Invention
The invention aims to effectively solve the risk that clock switching of different clock domains can generate metastable state or burr when gigabit Ethernet is dynamically switched at two transceivers of gphy and serdes and three rates of 10/100/1000 Mbps; the circuit realizes smooth switching of different clock domains through a three-level synchronization and interlocking mechanism, avoids the risk of generating burrs and metastable states during clock switching of clock domains, ensures the correctness of circuit functions, can provide correct output clocks during reset, and ensures the logic function of a chip during reset.
The invention is realized by the following technical scheme:
a clock switching circuit of a gigabit Ethernet transceiver comprises an MXT2_1 switching module, an MXT2_2 switching module, an MXT2_3 switching module, a NOR3 three-input NOR module and an OAI2 three-input NOR module; the MXT2_1 switching module and the MXT2_2 switching module respectively comprise a nandb0 two-input NAND module, an inv 0-inv 5 negation module, a nand 0-nand 3 two-input NAND module, a dffr 0-dffr 2 reset register module and a dffs 0-dffs 2 set register module;
the MXT2_1 switching module is used for realizing clock switching when the transceivers serdes and gphy work at 1000M;
the MXT2_2 switching module is used for realizing clock switching when the transceivers serdes and gphy work at 10/100M:
the MXT2_3 switching module is used for realizing clock switching of the transceivers serdes;
the NOR3 module is used for judging the working rates of the transceivers serdes and the gphy, and the output is used for controlling the MXT2_1 switching module;
the OAI2 module is used for judging the working rates of the transceivers serdes and gphy and outputting the working rates for controlling the MXT2_2 switching module;
the nandb0 two-input NAND module is used for realizing AND logic inversion of two inputs;
the inv 0-inv 5 negation module is used for negating the input end;
dffr 0-dffr 2 are 3 reset registers, wherein the clock of the dffr2 register is the inverted clock of the dffr0 and the dffr1, and is used for realizing three-level synchronization of effective switching control signals, and the output is 0 during the reset period;
the nand modules of nand 0-nand 3 are used for realizing the logical negation of the two inputs;
dffs 0-dffs 2 are 3 setting registers, wherein the clock of the dffs2 register is the inverted clock of dffs0 and dffs1, so that three-level synchronization of effective switching control signals is realized, and the output during setting is 1.
Preferably, the switching process of the MXT2_1 switching module is as follows:
when transceiver servers are enabled, regardless of the gphy operating rate; serdes _ en _ i is 1, N5 is 0, the module is switched from sys _125m _ _oclock at B to N22 clock at a, and there is dynamic switching after reset;
when the transceivers are not enabled, the gphy operating rate is 1000M; the mac _ speed _ sel _ i signal is 0, serdes _en _iis 0, N5 is 1, and the module always outputs the sys _125m _clk _oclock at the B end;
when the transceivers servers are not enabled, the gphy operating rate is 10/100M; the mac _ speed _ sel _ i signal is 1, the serdes _en _iis 0, N5 is 0, the module is switched from the sys _125m _clk _oclock at the B terminal to the N22 clock at the A terminal, and there is dynamic switching after reset.
Preferably, the switching process of the MXT2_2 switching module is as follows:
when transceiver servers are enabled, regardless of the gphy operating rate; serdes _ en _ i is 1, N4 is 0, the module is switched from the gphy _ mac _ clk _ i _ s clock of the B terminal to the N21 clock of the a terminal, and there is dynamic switching after reset;
when the transceivers are not enabled, the gphy operating rate is 1000M; the mac _ speed _ sel _ i signal is 0, the servers _ en _iis 0, N4 is 0, the module is switched to the N21 clock of the A end by the gps _ mac _ clk _ i _ s clock of the B end, and dynamic switching exists after reset;
when the transceivers serdes are not enabled, the gphy operating rate is 10/100M; mac _ speed _ sel _ i signal is 1, serdes _, en _, is 0, N4 is 1, the module always outputs the gphy _ mac _ clk _ i _ s clock at the B terminal.
Preferably, the switching process of the MXT2_3 switching module is as follows:
when the transceiver serdes is enabled, serdes _ en _ i is 1, and the module always outputs sys _125m _clk _oclock at the B terminal;
when the transceiver serdes is not enabled, serdes _ en _ i is 0, the module is switched to 0 of the A end by sys _125m _clko clock of the B end, and there is no dynamic switching of different clock domains after reset.
Preferably, the input signal serdes _ en _ i of the NOR3 module is 1 when the transceiver serdes is enabled, otherwise it is 0; the input signal scan _ mode is 1 in the test mode and0 in the functional mode; the input signal mac _ speed _ sel _ i is 0 when the gphy works at 1000M and is 0 when the input signal is 10/100M; when the transceiver serdes is enabled or the transceiver gphy operates at 10/100M, the module output is 0, otherwise it is 1.
Preferably, the input signal serdes _ en _ i of the OAI2 module is 1 when the transceiver serdes is enabled, otherwise it is 0; the input signal scan _ mode is 1 in the test mode and0 in the functional mode; the input signal mac _ speed _ sel _ i is 0 when the gphy works at 1000M and is 0 when the input signal is 10/100M; when the transceiver serdes is enabled or the transceiver gphy operates at 1000M, the module output is 0, otherwise it is 1.
Preferably, nandb0 is a two-input nand module, and when the clock is switched, the output of the nand module is 1, otherwise, the output of the nand module is 0.
Compared with the prior art, the invention has the following beneficial technical effects:
the clock of the dffr2 register is the reverse clock of the dffr0 and the dffr1, so that three-stage synchronization of effective switching control signals is realized, and the output is 0 during reset, thereby avoiding the influence of metastable state and burr. The clock of the dffs2 register is the inverse clock of dffs0 and dffs1, three-level synchronization of effective switching control signals is realized, the output during the setting period is 1, and the output of the clock during the resetting period is ensured. The invention realizes smooth switching of different clock domains through a three-level synchronization and interlocking mechanism, thereby not only avoiding the risk of generating burrs and metastable states, but also ensuring the correctness of circuit functions; and according to the needs of the gigabit Ethernet, a correct output clock can be provided during the reset period, so that the correctness of the logic function of the chip during the reset period is ensured. By performing function simulation on the invention, no matter the two transceivers are in gphy and serdes, or the dynamic switching is performed at three rates of 10M, 100M and 1000M, the generation of glitches and metastable states can be avoided, and simultaneously, a correct output clock can be generated in the reset period according to the function requirement.
Drawings
FIG. 1 is a block diagram of an overall structure of a gigabit Ethernet clock switching circuit;
FIG. 2 is a block diagram of a switching module;
fig. 3 is a timing diagram of output clocks switching between different transceivers and rates.
Reference numbers in the figures: 1 is MXT2_1 switching modules, and the number of the switching modules is 1. The clock switching of the transceivers serdes and 1000M gphy is mainly realized.
And 2 are MXT2_2 switching modules, and the number of the MXT2_2 switching modules is 1. Mainly realizes the clock switching of the transceivers serdes and 10/100M gphy.
And3 are MXT2_3 switching modules, and the number of the switching modules is 1. Mainly realizes the clock switching of the transceivers serdes.
4 are NOR3 modules, the number of which is 1. The judgment of the working rates of the transceivers serdes and the gphy is mainly realized, and the output is used for controlling the 1 switching module.
5 are OAI2 modules, the number of which is 1. The judgment of the working rates of the transceivers serdes and the gphy is mainly realized, and the output is used for controlling the 2 switching module.
And 6 are nandb0 modules, and the number of the nandb0 modules is 1. The inversion of the two-input AND logic is mainly realized.
7 are inv modules, the number of which is 6. The inversion of the input end is mainly realized.
And 8 are dffr modules, and the number of the dffr modules is 3. Three-level synchronization of effective switching control signals is mainly realized, and the output is 0 during reset, so that the influence of metastable state and burr is avoided.
And 9 are nand modules, and the number of the nand modules is 4. The AND logic inversion of the two inputs is mainly realized.
10 are dffs blocks, the number of which is 3. Three-stage synchronization of effective switching control signals is mainly realized, the output is 1 during setting, and the output of the clock is ensured during resetting.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
The invention relates to a clock switching circuit of a gigabit Ethernet transceiver, which mainly comprises MXT2_ 1-MXT 2_3 switching modules, a NOR3 three-input NOR module, an OAI2 three-input NOR module, a nandb0 two-input NAND module, an inv 0-inv 5 negation module, a nand 0-nand 3 two-input NAND module, a dffr 0-dffr 2 reset register module and a dffs 0-dffs 2 set register module.
The general structure block diagram is shown in fig. 1, and the detailed description is as follows:
1. the MXT2_1 switching module (reference numeral 1) mainly has the functions of realizing clock switching when the transceivers serdes and gphy work at 1000M, and the logic expression of the MXT2_1 switching module is Y = ((-S0). A + S0. B); in the default mode, the clock sys _125m _clk _oat the B end is output, and the clock is the 125MHz operating clock of the system, and the switching process is as follows:
when transceiver servers are enabled, regardless of the gphy operating rate; serdes _ en _ i is 1, N5 is 0, the module is switched from sys _125m _clk _oclock at the B end to N22 clock at the a end, the two clocks belong to different clock domains, and there is dynamic switching after reset, the switching module is as shown in fig. 2;
when the transceivers servers are not enabled, the gphy operating rate is 1000M; mac _ speed _ sel _ i signal 0, serdes _, en _, 0, N5 1, the module always outputs sys _125m _clk _oclock of the B end, and no clock switching exists;
when the transceivers serdes are not enabled, the gphy operating rate is 10/100M; the mac _ speed _ sel _ i signal is 1, the servers _ en _iis 0, the N5 is 0, the module is switched from the sys _125m _ clk _oclock at the B terminal to the N22 clock at the a terminal, the two clocks belong to different clock domains, and there is dynamic switching after reset, and the switching module is as shown in fig. 2.
2. The MXT2_2 switching module (label 2) mainly has the functions of realizing clock switching when the transceivers serdes and gphy work at 10/100M, and the logic expression is Y = ((-S0). A + S0. B); the output clock of B terminal gphy _ mac _ clk _ i _ s in default mode is 2.5MHz at 10M rate and 25MHz at 100M rate, and the switching process is as follows:
when transceiver servers are enabled, regardless of the gphy operating rate; the stages _ en _ i is 1, N4 is 0, the module is switched from the gphy _ mac _ clk _ i _ s clock at the B end to the N21 clock at the a end, the two clocks belong to different clock domains, and there is dynamic switching after reset, and the switching module is as shown in fig. 2;
when the transceivers servers are not enabled, the gphy operating rate is 1000M; the mac _ speed _ sel _ i signal is 0, the servers _ en _isignal is 0, N4 is 0, the module is switched from the gps _ mac _ clk _ i _ s clock at the B terminal to the N21 clock at the A terminal, the two clocks belong to different clock domains, and dynamic switching exists after resetting, and the switching module is shown in FIG. 2;
when the transceivers serdes are not enabled, the gphy operating rate is 10/100M; the mac _ speed _ sel _ i signal is 1, serdes _ en _iis 0, the number N4 is 1, and the content, the module always outputs the gphy _ mac _ clk _ i _ s clock at the B end, and no clock switching exists.
3. The MXT2_3 switching module (reference numeral 3) mainly has the function of realizing clock switching of the transceivers serdes, and the logic expression of the MXT2_3 switching module is Y = ((-S0) · A + S0 · B); in the default mode, the clock sys _125m _ clk _oat B end, which is the output clock of the transceiver serdes, is output, and the switching process is as follows:
when the transceiver serdes is enabled, serdes _ en _ i is 1, and the module always outputs sys _125m _clk _oclock of the B end, and no clock switching exists;
when the transceiver serdes is not enabled, serdes _ en _ i is 0, the module is switched from sys _125m _clk _oclock at the B side to 0 at the a side, there is no dynamic switching of different clock domains after reset.
4. The NOR3 module (labeled 4) mainly has the functions of judging the working rates of the transceivers serdes and gphy, and outputting the working rates to control the MXT2_1 switching module, wherein the logical expression of the switching module is Y = - (A + B + C); when the transceiver serdes is enabled, its input signal serdes _ en _ i is 1, otherwise it is 0; the input signal scan _ mode is 1 in the test mode and0 in the functional mode, and the invention is always defaulted to the functional mode; the input signal mac _ speed _ sel _ i is 0 when the gphy works at 1000M and is 0 when the input signal is 10/100M; when the transceiver serdes is enabled or the transceiver gphy operates at 10/100M, the module output is 0, otherwise it is 1.
5. The OAI2 module (reference number 5) mainly has the functions of judging the working rates of the transceivers serdes and gphy, and outputting the working rates for controlling the MXT2_2 switching module, wherein the logic expression of the OAI2 module is Y = - (A0 + (-A1N)). B; when the transceiver serdes is enabled, its input signal serdes _ en _ i is 1, otherwise it is 0; the input signal scan _ mode is 1 in the test mode and0 in the functional mode, and the invention is always defaulted to the functional mode; the input signal mac _ speed _ sel _ i is 0 when the gphy works at 1000M and is 0 when the gphy works at 10/100M; when the transceiver serdes is enabled or the transceiver gphy operates at 1000M, the module output is 0, otherwise it is 1.
The switching module shown in fig. 2 is illustrated as follows:
6. nandb0 two-input nand module (label 6) realizes the logical inversion of the two-input and, the logical expression is Y = (AN · B); when the clock is switched, the output of the module is 1, otherwise, the output is 0.
7. The inv 0-inv 5 negation modules (reference numeral 7 (1), reference numeral 7 (2), reference numeral 7 (3), reference numeral 7 (4), reference numeral 7 (5) and reference numeral 7 (6)) implement negation on of the input end, and the logical expressions are Y = -A.
8. dffr0 to dffr2 (reference numerals 8 (1), 8 (2), and 8 (3)) are 3 reset registers, wherein the clock of the dffr2 register is the inverted clock of the dffr0 and the dffr1, three-level synchronization of effective switching control signals is realized, and the output during reset is 0, thereby avoiding the influence of metastable state and burr.
9. The nand modules (9 (1), 9 (2), 9 (3) and 9 (4)) between nand0 and nand3 realize the logical inversion of the and between the nand inputs, and the logical expression is Y = (a · B).
10. dffs0 to dffs2 (reference numeral 10 (1), reference numeral 10 (2), and reference numeral 10 (3)) are 3 setting registers, wherein the clock of the dffs2 register is the inverted clock of the dffs0 and dffs1, three-stage synchronization of effective switching control signals is realized, the output during the setting period is 1, and the output of the clock during the resetting period is ensured.
The core idea of the invention is to realize smooth switching of different clock domains by a three-level synchronization and interlocking mechanism, thereby not only avoiding the risk of generating burrs and metastable states, but also ensuring the correctness of circuit functions; and according to the needs of the gigabit Ethernet, a correct output clock can be provided during the reset period, so that the correctness of the logic function of the chip during the reset period is ensured.
According to the scheme, the logic design of each module in the invention is described by using verilog language, and the logic design is verified with other equipment in the network equipment at a system level. The verification result shows that the invention realizes the design function and the performance meets the expectation. The simulation result is shown in fig. 3. The phy _ MAC _ clk _ i _ s is an output clock of a transceiver transmission path at a rate of 10M or 100M, the sys _125m _ clk _ o is a system clock used for enabling the transceiver servers or when phy operates at 1000M, the MAC _ speed _ sel _ i is a rate switching signal generated according to an auto-negotiation result, and the MAC _ clk _ tx _ o is an operating clock output to the MAC transmission path at different transceiver and communication rates. It can be seen from the figure that when the mac _ speed _ sel _ i signal jumps, the output clock mac _ clk _ tx _ o is switched between two clocks, and the clocks before and after switching keep three complete clock cycles, and then the clocks are switched, so that the integrity of the clock cycles before and after switching is ensured, and the influence of a metastable state and a burr during the switching process is avoided.
Claims (7)
1. A clock switching circuit of a gigabit Ethernet transceiver is characterized by comprising an MXT2_1 switching module, an MXT2_2 switching module, an MXT2_3 switching module, a NOR3 three-input NOR module and an OAI2 three-input NOR module; the MXT2_1 switching module and the MXT2_2 switching module respectively comprise a nandb0 two-input NAND module, an inv 0-inv 5 negation module, a nand 0-nand 3 two-input NAND module, a dffr 0-dffr 2 reset register module and a dffs 0-dffs 2 set register module;
the MXT2_1 switching module is used for realizing clock switching when the transceivers serdes and gphy work at 1000M;
the MXT2_2 switching module is used for realizing clock switching when the transceivers serdes and gphy work at 10/100M:
the MXT2_3 switching module is used for realizing clock switching of the transceivers serdes;
the NOR3 module is used for judging the working rates of the transceivers serdes and the gphy, and the output is used for controlling the MXT2_1 switching module;
the OAI2 module is used for judging the working rates of the transceivers serdes and the gphy, and the output is used for controlling the MXT2_2 switching module;
the nandb0 two-input NAND module is used for realizing AND logic inversion of two inputs;
the inv 0-inv 5 negation module is used for negating the input end;
dffr 0-dffr 2 are 3 reset registers, wherein the clock of the dffr2 register is the inverted clock of the dffr0 and the dffr1, and is used for realizing three-level synchronization of effective switching control signals, and the output is 0 during the reset period;
the nand modules of nand0 to nand3 are used for implementing the logical and inversion of the two inputs;
dffs 0-dffs 2 are 3 set registers, wherein the clock of the dffs2 register is the inverted clock of the dffs0 and the dffs1, so that three-level synchronization of effective switching control signals is realized, and the output during setting is 1.
2. The clock switching circuit of gigabit ethernet transceiver according to claim 1, wherein the MXT2_1 switching module is switched as follows:
when transceiver servers are enabled, regardless of the gphy operating rate; serdes _ en _ i is 1, N5 is 0, the module is switched from sys _125m _ _oclock at B to N22 clock at a, and there is dynamic switching after reset;
when the transceivers are not enabled, the gphy operating rate is 1000M; the mac _ speed _ sel _ i signal is 0, serdes _en _iis 0, N5 is 1, and the module always outputs the sys _125m _clk _oclock at the B end;
when the transceivers servers are not enabled, the gphy operating rate is 10/100M; the mac _ speed _ sel _ i signal is 1, the serdes _en _iis 0, N5 is 0, the module is switched from the sys _125m _clk _oclock at the B terminal to the N22 clock at the A terminal, and there is dynamic switching after reset.
3. The clock switching circuit of gigabit ethernet transceiver according to claim 1, wherein the switching process of the MXT2_2 switching module is as follows:
when transceiver servers are enabled, regardless of the gphy operating rate; the stages _ en _ i is 1, N4 is 0, the module is switched from the gphy _ mac _ clk _ i _ s clock of the B terminal to the N21 clock of the A terminal, and dynamic switching exists after reset;
when the transceivers servers are not enabled, the gphy operating rate is 1000M; the mac _ speed _ sel _ i signal is 0, the servers _ en _iis 0, N4 is 0, the module is switched to the N21 clock of the A end by the gps _ mac _ clk _ i _ s clock of the B end, and dynamic switching exists after reset;
when the transceivers serdes are not enabled, the gphy operating rate is 10/100M; the mac _ speed _ sel _ i signal is 1, the servers _ en _ i signal is 0, N4 is 1, and the module always outputs the gphy _ mac _ clk _ i _ s clock at the B end.
4. The clock switching circuit of gigabit ethernet transceiver according to claim 1, wherein the MXT2_3 switching module is switched as follows:
when the transceiver serdes is enabled, serdes _ en _ i is 1, and the module always outputs sys _125m_clk _oclock at the B terminal;
when the transceiver serdes is not enabled, serdes _ en _ i is 0, the module is switched from sys _125m _clk _oclock at the B side to 0 at the a side, there is no dynamic switching of different clock domains after reset.
5. The clock switching circuit of gigabit ethernet transceiver according to claim 1, wherein the input signal serdes en _ i of NOR3 module is 1 when the transceiver serdes is enabled, and is 0 otherwise; the input signal scan _ mode is 1 in the test mode and0 in the functional mode; the input signal mac _ speed _ sel _ i is 0 when the gphy works at 1000M and is 0 when the gphy works at 10/100M; when the transceiver servers are enabled or the transceiver gphy is operating at 10/100M, the module output is 0, otherwise it is 1.
6. The clock switching circuit of a gigabit ethernet transceiver according to claim 1, wherein the input signal serdes en _ i of the OAI2 module is 1 when the transceiver serdes is enabled, and is 0 otherwise; the input signal scan _ mode is 1 in the test mode and0 in the functional mode; the input signal mac _ speed _ sel _ i is 0 when the gphy works at 1000M and is 0 when the gphy works at 10/100M; when the transceiver serdes is enabled or the transceiver gphy operates at 1000M, the module output is 0, otherwise it is 1.
7. The clock switching circuit of claim 1, wherein nandb0 nand module has a1 output when clocked and a0 output otherwise.
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