CN110932838B

CN110932838B - Synchronous redundant BTMs

Info

Publication number: CN110932838B
Application number: CN201911299026.XA
Authority: CN
Inventors: 王耀辉; 寇永砺; 监雄; 孙达根
Original assignee: Beijing Jiaoda Signal Technology Co Ltd
Current assignee: Beijing Jiaoda Signal Technology Co Ltd
Priority date: 2019-12-14
Filing date: 2019-12-14
Publication date: 2022-03-29
Anticipated expiration: 2039-12-14
Also published as: CN110932838A

Abstract

The synchronous redundant BTM is characterized in that an A/B system processor is connected with 2 responder information channels in a cross mode, the A/B systems are connected through a redundant communication bus, the A/B system processor receives responder information at a responder information channel interface and receives the other system of responder information containing timestamp information through the redundant communication bus, and the A/B system processor can share the responder information received by the A/B system processor through the redundant communication bus; a multiprocessor single-link technology is adopted between the ATP and the BTM, and information sent to the ATP is guaranteed to be consistent through interaction of internal redundant communication buses. The invention brings the following technical effects: when the first BTM fails to send a fault when communicating with the ATP or when the first BTM fails to complete normal functions, the BTM can automatically switch to the other system to work and ensure that the sequence of receiving information is correct.

Description

Synchronous redundant BTMs

Technical Field

The invention relates to the field of train control in the railway industry, in particular to a method for improving the reliability and the availability of a BTM digital part for transponder information processing and ensuring the consistency and the synchronism of user messages externally output by a plurality of circuit boards.

Background

With the rapid development of domestic rail transit, the BTM is taken as an important part of vehicle-mounted equipment, plays a key role in positioning trains, and has a high proportion of the problem of system unavailability caused by BTM reliability. Improving the reliability and availability of BTMs has become a source of effort for equipment vendors.

The A/B of conventional BTMs are independent of each other and communicate with the ATP/VOBC through respective communication interfaces. This structure of BTMs has two disadvantages.

1) BTMs have no synchronization relationship between the A/B lines and are independent of each other. Because the two BTMs are independent and respectively establish communication links with the ATP, the basic guarantee of synchronization depends on the natural synchronization of the two uplink information receiving channels. When there is interference in the environment, decoding fails, or the decoding time of the two lines differs greatly, and CPU threads differ greatly, the possibility of inconsistency of data sent to ATP in the same cycle between the two lines of BTMs increases. At this time, if the ATP switches the BTM working system, the availability of the system is greatly reduced.

2) The A/B system of the BTM does not perform redundancy processing on the received data of the responder information channels of the two paths of untrusted channels, and actually reduces the redundancy effect of 2 physical channels.

Disclosure of Invention

The invention provides a novel BTM (Business card management) architecture scheme, which solves the problem that BTM two-system communication asynchronization and responder uplink receiving channel information have no redundancy.

The invention provides a synchronous redundant BTM, wherein a redundant communication bus is newly added in the BTM, and an A/B system processor and 2 responder information channels of the BTM are connected in a cross way;

the A/B processor is connected with the 2 responder information channels in a cross way, the A/B processor respectively receives the information of the responder information channel 1 and the responder information channel 2 at the same time, and when a single-channel fault occurs, the A/B processor can also be ensured to reliably receive the responder information;

the A/B systems are connected through the redundant communication bus to share data, the data content transmitted by each bus is the same, the buses are physically independent, and when the buses are in single fault, the overall function is not influenced;

the A/B processor receives the responder information at a responder information channel interface and receives the other responder information containing the timestamp information through a redundant communication bus, and the A/B processor processes all the information according to a certain principle to obtain a real responder information sequence;

even if the physical redundancy of the information channel fails and any one of the A/B processors fails to decode due to various reasons, the A/B processors can still share the information of the responder received by the A/B processors through the redundant communication bus, thereby improving the redundant processing of information reception;

a multi-processor single-link technology is adopted between the ATP and the BTMs, namely, a plurality of BTM processors respectively generate communication information sent to the ATP in the same communication cycle, and before the communication information is sent to the ATP, the information sent to the ATP is ensured to be consistent through internal redundant communication buses in an interactive mode.

The invention brings the following technical effects: when the first BTM fails to send a fault when communicating with the ATP or when the first BTM fails to complete normal functions, the BTM can automatically switch to the other system to work and ensure that the sequence of receiving information is correct.

Drawings

FIG. 1 is a logical block diagram of the novel BTM architecture of the present invention;

FIG. 2 is a diagram of the transponder information data flow and main function processing modules of the synchronous redundancy mechanism of the present invention;

fig. 3 is a simplified diagram of data flow synchronization of transponder information (for the main part of a single processor module).

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

The problem that the receiving channel information of the transponder uplink has no redundancy mainly means that when a train passes through a ground transponder, the A/B of the BTM can be successfully decoded and the A/B of the BTM can be failed to decode; the asynchronous communication problem mainly refers to the inconsistency of communication between the A/B system of the BTM and the ATP (vehicle-mounted train control host unit) caused by various problems.

The novel BTM architecture of the application has a newly added redundant communication bus and is cross-connected with processors of A/B system (each system of processors is also a single processor module and is represented as processor boards 1 and 2) and 2 responder information channels, as shown in FIG. 1.

The novel BTM synchronous redundancy mechanism is established on the basis of communication, data sharing is carried out between A/B systems through a redundant synchronous bus, redundant communication bus connection is adopted, the data content transmitted by each bus is the same, the physical independence is realized, and the whole function is not influenced when the bus has single fault.

The transponder information data flow of the synchronous redundancy mechanism to the main functional processing module is shown in fig. 2.

The processor boards of each family (i.e., processor modules of the A/B family) in FIG. 2 include a transponder information processing module, an internal synchronization module, a FIFO management module, and an external synchronization module, containing only one internal synchronization module and one external synchronization module for a single BTM. The transponder information processing module acquires and decodes uplink signals, after decoding succeeds, the decoding results are mutually notified to the other processor module through the internal synchronization module, after information comparison processing (including local transponder information and transponder information acquired by a synchronization bus), the transponder information is stored in FIFO (first in first out), namely the internal synchronization module compares and sorts the local transponder information and the synchronous transponder information of a different-place board card (from another system) according to the message content and the generation time of a transponder, filters the same message, and adjusts the sequence of different messages entering the FIFO; and the external synchronization module reads the transponder information from the FIFO and frames the transponder information to the vehicle-mounted column control host unit according to the communication condition with the vehicle-mounted column control host unit, and the operation of synchronously reading the FIFO is mainly realized in a synchronous communication mode.

In fig. 3, a data flow synchronization diagram of transponder information is shown, which mainly includes a single processor module (i.e., a single system processor board), where there are two main sources of transponder information of the single processor module: the antenna equipment of the BTM activates a ground responder through an energy signal, the responder transmits original code source information of the responder in an FSK form through an uplink, and the block processor module carries out filtering demodulation and decoding on the FSK information and analyzes the original code information into user message information; alternatively, the decoded result may be sent to the bus when the other processor module decodes successfully, so that the other source of the processor module transponder information is the bus.

The switching logic (referring to synchronous output) in fig. 3 mainly determines which information is legal based on its own decoding condition and the transponder information obtained from the bus; the logical overview is as follows:

A. if the message contents are the same, adopting a local decoding result;

B. and if the message contents are different, sequencing the time of the responder information according to the timestamp.

In addition, in the present invention, a single BTM can interface two different vehicle-mounted train control host units (not shown in specific examples), for example, two processor boards (belonging to a processor module in a family a, for example) are connected with ATP/VOBC, and the other two boards (belonging to a family B) are connected with LKJ (i.e. ATP is schematic in fig. 2 and can represent VOBC/LKJ), so that the expansibility and universality of the BTM device are enhanced; the transponder information among the 4 processor modules is redundantly shared through a synchronous bus, and one source of the transponder information is added to each processor module. The internal synchronization module ensures the consistency and synchronization of the output of the response device information of the ATP/VOBC and LKJ by the BTM, and the external synchronization module can be configured according to different requirements of the ATP/VOBC, the LKJ and the like, so that the processing logics are basically consistent.

The salient advantages of the architecture of the present invention are described in detail below.

1. Transponder information redundancy function (internal synchronization module):

1) physical redundancy:

the cross-connection of the A/B family processor and 2 transponder information channels is added. The A/B processor receives the information of the transponder information channel 1 and the transponder information channel 2 respectively and simultaneously.

Under the structure, single-channel faults occur in 2 transponder information channels, and the fact that the A/B processor can reliably receive the transponder information can also be guaranteed. This architecture is a physical redundancy of the transponder information channel.

2) Logical redundancy:

the A/B processors are connected through a redundant communication bus (such as a CAN bus), and the single bus fault does not affect the availability of the system.

The A/B system processor synchronizes the clocks of the two through the redundant communication bus.

When the A/B processor receives any link channel information, the A/B processor marks the information with a time stamp and sends the information of the responder carrying the time stamp information to the opposite side through a redundant communication bus besides the use of the A/B processor.

The A/B processor receives the responder information at the responder information channel interface and receives the other responder information containing the time stamp information through the redundant communication bus. The A/B processor processes all information according to a certain principle to obtain a real transponder information sequence.

Even if the physical redundancy of the information channel fails and any one of the A/B processors fails to decode due to various reasons, the A/B processors can still share the information of the transponders received by the A/B processors through the redundant communication bus, thereby improving the redundant processing of information reception to the maximum extent.

2. BTM dual (multi) processor single link communication techniques

The invention adopts a multiprocessor single-link technology between the ATP and the BTM in order to simplify the complexity of the ATP processing on multiple information channels (links).

For the receiver ATP (which may be multiple, such as VOBC/LKJ), although there are 2 or more physical channels for communication, with this technique, the ATP just communicates with a single BTM core (single link, which may be understood as being for the FIFO management module), thus avoiding the complexity of processing multilink channel information, i.e. the ATP needs to be configured by an external synchronization module, and does not need to perform complex processing on multichannel information itself.

For BTM implementations, multiple processors (modules) of the BTM are capable of receiving ATP information received by different communication interfaces, either through internal redundant communication buses or physical redundancy of external communication buses, at each BTM processor module. The single BTM integrates the communication information obtained by each physical channel, filters out redundant communication information, and logically corresponds to the fact that the information sent by the same ATP brain (processed by an external synchronization module and then sent to the FIFO) is received.

On the other hand, the multiple BTM processors generate communication information to be sent to the ATP respectively in the same communication cycle, and before sending to the ATP, the information sent to the ATP is guaranteed to be consistent through internal redundant communication bus interaction (internal synchronization module), and then the information is sent to each ATP through each physical communication interface, so that each ATP feels like receiving information from the same BTM brain, and different communication interfaces are only physical redundant channels of information.

The technical scheme of the invention brings the following technical effects:

the direct effect is to realize the redundancy and synchronization of the responder information between the A/B systems of the BTM; the transponder information redundancy is mainly embodied by adding a source of transponder information for one processor module and logically collecting and communicating decoding information of the other processor module when necessary; the communication synchronization is mainly reflected in the synchronism of the A/B system of the BTM to the output of the responder information of the ATP unit, and the condition that communication interfaces of the BTM are inconsistent due to the asynchronization between systems is avoided.

The above description is only a preferred embodiment of the present novel scheme, and is not intended to limit the scope of the present novel scheme. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the new scheme shall be included in the protection scope of the new scheme.

Claims

1. A synchronous redundant BTM, newly add the redundant communication bus in said BTM, and cross-connect A/B processor and 2 pieces of responder information channels of BTM;

2. The BTM of claim 1, wherein the A/B family processor synchronizes clocks of both through a redundant communication bus; when the A/B processor receives any link channel information, the A/B processor not only uses the A/B processor, but also marks the information with a time stamp and sends the responder information carrying the time stamp information to the other side through a redundant communication bus.

3. The BTM of claim 2, wherein the transponder information redundancy is embodied by adding a source of transponder information to one family of processors and logically collecting decoded information from another family of processors.

4. The BTM of claim 3, wherein the monolithic processor of the BTM has two sources of transponder information: the antenna equipment of the BTM activates a ground responder through an energy signal, the responder transmits original code source information of the responder in an FSK form through an uplink, and a processor of the BTM analyzes the original code information into user message information by filtering and demodulating the FSK information and decoding the FSK information; another source is a redundant communication bus that sends the decoded result to the bus when another processor decodes successfully.

5. The BTM of claim 1, wherein multiple processors of the BTM are physically redundant via an internal redundant communication bus or an external communication bus, each BTM processor being capable of receiving ATP information received via a different communication interface, wherein a single BTM integrates the communications from the various physical channels, filters out redundant communications, and logically corresponds to receiving information sent from the same ATP.

6. The BTM of claim 1, wherein communication synchronization is embodied in synchronization of the A/B family of the BTM with the output of the responder message of the ATP unit, thereby avoiding inconsistencies in the communication interface of the BTM that result from inter-family asynchrony.

7. The BTM of claim 1, wherein the processor of each line of BTMs includes a responder information processing module, an internal synchronization module, a FIFO management module, and an external synchronization module;

the responder information processing module acquires and decodes the uplink signal, informs the other processor of the decoding result through the internal synchronization module after the decoding is successful, and stores the responder information into the FIFO management module after the information comparison processing; the information of the comparison processing comprises local responder information and responder information acquired by the synchronous bus.

8. The BTM of claim 7, wherein the internal synchronization module of the BTM compares and sorts the local transponder information and the synchronized transponder information of another system board card according to the message content and generation time of the transponder, filters out the same messages, and adjusts the order of different messages entering the FIFO.

9. The BTM of claim 7, wherein the external synchronization module of the BTM synchronizes reading of the FIFO by means of synchronous communication based on communication with the on-board column control host unit, reading of the transponder information from the FIFO and framing of the transponder information to the on-board column control host unit.