CN115982070A - Signal generating device - Google Patents
Signal generating device Download PDFInfo
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- CN115982070A CN115982070A CN202211569474.9A CN202211569474A CN115982070A CN 115982070 A CN115982070 A CN 115982070A CN 202211569474 A CN202211569474 A CN 202211569474A CN 115982070 A CN115982070 A CN 115982070A
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Abstract
The embodiment of the invention relates to a signal generating device, which comprises: the device comprises a communication module, a main control module, a first external interface module, a power supply control back plate and a functional module. By adding the communication module and the main control module, FC bus signals received from the outside are transmitted to the main control module through the communication module, and the bus signals are transmitted to the functional module through the power supply control back plate, so that radio frequency continuous wave signals and broadband vector modulation signals are generated. This achieves the technical effects of high-speed data transmission and signal generation by the FC bus.
Description
Technical Field
The embodiment of the invention relates to the technical field of signal processing, in particular to a signal generating device.
Background
With the development of communication technology, data transmission modes are well enriched, transmission modes using optical fibers as media are widely applied, and FC (fiber Channel) buses are regarded by various industries due to the advantages of high bandwidth, light weight, strong anti-interference capability and the like.
However, the existing FC bus-based products already include devices such as a terminal network card, a switch, a video transmission device, a network analyzer, and a fault injection card, but there is no FC bus-based signal generation device, and a relatively close product is an LXI bus microwave device, which cannot meet the requirement of high-speed data transmission of a host.
Disclosure of Invention
In view of this, in order to solve the technical problem that the FC bus cannot meet the technical requirements in the field of signal processing, an embodiment of the present invention provides a signal generating device.
In a first aspect, an embodiment of the present invention provides a signal generating apparatus, including:
the system comprises a communication module, a main control module, a first external interface module, a power supply control back plate and a functional module;
an Ethernet port physical layer and a first FPGA chip are arranged in the communication module, the input end of the Ethernet port physical layer is electrically connected with the first output end of the first external interface module, and the output end of the Ethernet port physical layer is electrically connected with the first input end of the main control module;
the input end of the first FPGA chip is electrically connected with the second output end of the first external interface module, the first output end of the first FPGA chip is electrically connected with the second input end of the main control module, and the second output end of the first FPGA chip is electrically connected with the first input end of the power supply control back plate;
the third output end of the first external interface module is electrically connected with the third input end of the main control module;
the second input end of the power supply control back plate is electrically connected with the output end of the main control module, and the plurality of output ends of the power supply control back plate are electrically connected with the plurality of input ends of the functional modules in sequence.
In one possible embodiment, the first FPGA chip includes:
PCle interface IP, ethernet IP and synchronous logic unit;
the output end of the PCle interface IP is electrically connected with the second input end of the main control module;
the input end of the Ethernet IP is electrically connected with the second output end of the first external interface module;
the first input end of the synchronous logic unit is electrically connected with the fourth output end of the first external interface module, the second input end of the synchronous logic unit is electrically connected with the fifth output end of the first external interface module, and the output end of the synchronous logic unit is electrically connected with the first input end of the power supply control back plate.
In one possible implementation, the functional module includes:
the system comprises a baseband signal generation sub-module, a radio frequency up-conversion sub-module, a local oscillator sub-module and a switch attenuation sub-module;
the input end of the baseband signal generation submodule is electrically connected with the first output end of the power supply control back plate, the first output end of the baseband signal generation submodule is electrically connected with the first input end of the radio frequency up-conversion submodule, and the second output end of the baseband signal generation submodule is electrically connected with the first input end of the local oscillator submodule;
a second input end of the local oscillator submodule is electrically connected with a second output end of the power supply control back plate, and an output end of the local oscillator submodule is electrically connected with a second input end of the radio frequency up-conversion submodule;
a third input end of the radio frequency up-conversion sub-module is electrically connected with a third output end of the power supply control back plate, and an output end of the radio frequency up-conversion sub-module is electrically connected with a first input end of the switch attenuation sub-module;
and a second input end of the switch attenuation submodule is electrically connected with a fourth output end of the power supply control back plate, and an output end of the switch attenuation submodule is connected to an output interface.
In one possible embodiment, the baseband signal generation sub-module includes:
the device comprises a second FPGA chip, a DA acquisition unit, a first clock unit and a conditioning unit;
the input end of the second FPGA chip is electrically connected with the first output end of the power supply control back plate, and the output end of the second FPGA chip is electrically connected with the input end of the DA acquisition unit;
the DA acquisition unit comprises a broadband DA acquisition subunit and a calibration DA acquisition subunit, the input end of the broadband DA acquisition subunit is electrically connected with the first output end of the second FPGA chip, the output end of the broadband DA acquisition subunit is electrically connected with the input end of the conditioning unit and the output end of the calibration DA acquisition subunit, and the input end of the calibration DA acquisition subunit is electrically connected with the second output end of the second FPGA chip;
the output end of the first clock unit is electrically connected with the second input end of the local oscillator submodule;
the output end of the conditioning unit is electrically connected with the first input end of the radio frequency up-conversion submodule.
In one possible implementation, the local oscillation sub-module includes:
the second clock unit, the frequency multiplication unit, the broadband low-phase noise frequency sweeping unit and the point frequency source unit;
the input end of the second clock unit is electrically connected with the second output end of the baseband signal generation submodule, and the output end of the second clock unit is electrically connected with the input end of the frequency doubling unit, the first input end of the broadband low-phase noise frequency sweeping unit and the point frequency source unit respectively;
the output end of the frequency doubling unit is electrically connected with the second input end of the broadband low-phase noise frequency sweeping unit;
the output end of the broadband low-phase-noise frequency sweeping unit is electrically connected with the second input end of the radio frequency up-conversion submodule;
the local oscillator submodule further comprises a first power supply control unit, an input end of the first power supply control unit is electrically connected with a second output end of the power supply control back plate, and an output end of the first power supply control unit is electrically connected with the other input end of the second clock unit, the other input end of the frequency doubling unit, a third input end of the broadband low-phase noise frequency sweeping unit and the other input end of the point frequency source unit respectively.
In one possible implementation, the radio frequency up-conversion sub-module includes:
the device comprises an IQ modulation unit, a filtering unit, a low-frequency signal generating unit and a gain conditioning unit;
a first input end of the IQ modulation unit is electrically connected with a first output end of the baseband signal generation submodule, a second input end of the IQ modulation unit is electrically connected with an output end of the local oscillation submodule, a first output end of the IQ modulation unit is electrically connected with an input end of the low-frequency signal generation unit, and a second output end of the IQ modulation unit is electrically connected with an input end of the filtering unit;
the output end of the low-frequency signal generating unit is electrically connected with the first input end of the gain conditioning unit;
the output end of the filtering unit is electrically connected with the second input end of the gain conditioning unit;
the output end of the gain conditioning unit is electrically connected with the second input end of the switch attenuation submodule;
the radio frequency up-conversion sub-module further comprises a second power control unit, an input end of the second power control unit is electrically connected with a third output end of the power supply control back plate, and an output end of the second power control unit is electrically connected with a third input end of the IQ modulation unit, a second input end of the filtering unit, a second input end of the low-frequency signal generation unit and a third input end of the gain conditioning unit respectively.
In one possible embodiment, the switch attenuation submodule includes:
a program-controlled attenuation unit and a third power supply control unit;
the first input end of the program-controlled attenuation unit is electrically connected with the output end of the radio frequency up-conversion sub-module, the second input end of the program-controlled attenuation unit is electrically connected with the output end of the third power supply control unit, and the output end of the program-controlled attenuation unit is connected to an output interface;
the input end of the third power supply control unit is electrically connected with the fourth output end of the power supply control back plate.
In one possible embodiment, the first external interface module comprises:
the system comprises a debugging interface, a display control interface, an FC optical fiber interface, an SMB second pulse interface and a trigger signal interface;
the output end of the debugging interface is electrically connected with the first input end of the communication module;
the output end of the display control interface is electrically connected with the second input end of the communication module;
the output end of the FC optical fiber interface is electrically connected with the third input end of the communication module;
the output end of the SMB second pulse interface is electrically connected with the fourth input end of the communication module;
the output end of the trigger signal interface is electrically connected with the fifth input end of the communication module.
In one possible embodiment, the apparatus further comprises a second external interface module;
and the input end of the second external interface module is electrically connected with the baseband signal generation sub-modules in the functional module in sequence.
In one possible embodiment, the second external interface module includes: the system comprises a four-channel external modulation interface, a reference interface and a trigger interface;
the output end of the four-channel external modulation interface is electrically connected with the other input end of the modulation unit;
the reference interface is electrically connected with the first clock unit;
the trigger interface is electrically connected with the second FPGA chip.
In one possible embodiment, the apparatus further comprises a power source;
the power supply is electrically connected with the power supply control back plate through an alternating current-direct current converter.
The signal generating device provided by the embodiment of the invention is characterized in that a communication module, a main control module, a first external interface module, a power supply control back plate and a functional module are arranged; an Ethernet port physical layer and a first FPGA chip are arranged in the communication module, the input end of the port physical layer is electrically connected with the first output end of the first external interface module, and the output end of the port physical layer is electrically connected with the first input end of the main control module; the input end of the first FPGA chip is electrically connected with the second output end of the first external interface module, the first output end of the first FPGA chip is electrically connected with the second input end of the main control module, and the second output end of the first FPGA chip is electrically connected with the first input end of the power supply control back plate; the third output end of the first external interface module is electrically connected with the third input end of the main control module; the second input end of the power supply control back plate is electrically connected with the output end of the main control module, and the plurality of output ends of the power supply control back plate are electrically connected with the plurality of input ends of the functional modules in sequence. The communication module and the master control module are additionally arranged to be connected with the power supply control back plate, FC bus signals received from the outside are transmitted to the master control module through the communication module, and the bus signals are transmitted to the function module through the power supply control back plate, so that radio frequency continuous wave signals and broadband vector modulation signals are generated. By the scheme, the technical effects of high-speed data transmission and signal generation based on the FC bus can be achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of a signal generating device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another signal generating device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an FPGA chip in a communication module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another signal generating device according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another signal generating apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an external interface of a signal generating apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprising" and "having" in the embodiments of the present invention are used to mean open-ended inclusion, and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects. Further, the different elements and regions in the drawings are only schematically shown, and thus the present invention is not limited to the dimensions or distances shown in the drawings.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained with reference to specific embodiments, which are not to be construed as limiting the embodiments of the present invention.
Fibre Channel (FC), at its high speed and high reliability, is one of the interconnect standards in complex avionics systems. The method supports upper layer protocols such as FC-AE-ASM and FC-FS, and the link rate can be configured to be a plurality of transmission rates such as 1Gbps, 2Gbps and 4 Gb/s. The system can simulate the functions of a main manager and a common terminal, support the functions of data customization receiving and sending of short messages and long messages, simulation verification of a time server and a client, simulation of a network management function and the like, and realize the tests of functions, performance, protocols, pressure and the like on a connected switch and a connected terminal.
Fig. 1 is a schematic structural diagram of a signal generating device according to an embodiment of the present invention. With reference to the diagram provided in fig. 1, the signal generating device comprises in particular:
the system comprises a communication module 10, a main control module 20, a first external interface module 30, a power supply control back panel 40 and a functional module 50.
According to the diagram provided in fig. 1, the internal structure of the signal generating device specifically comprises:
the communication module 10 is provided with an ethernet port physical layer 11 and a first FPGA chip 12, an input end of the ethernet port physical layer 11 is electrically connected to a first output end of the first external interface module 30, and an output end of the ethernet port physical layer 11 is electrically connected to a first input end of the main control module 20;
the input end of the first FPGA chip 12 is electrically connected to the second output end of the first external interface module 30, the first output end is electrically connected to the second input end of the main control module 20, and the second output end is electrically connected to the first input end of the power supply control backplane 40;
a third output terminal of the first external interface module 30 is electrically connected to a third input terminal of the main control module 20;
the second input terminal of the power supply control backplane 40 is electrically connected to the output terminal of the main control module 20, and a plurality of output terminals of the power supply control backplane 40 are electrically connected to a plurality of input terminals of the functional module 50 in sequence.
The main control module 20 is configured to run an operating system, a protocol stack, and device application services, and implement access control, data processing, and transmission of devices.
According to the diagram provided in fig. 1, the optical fiber signal is input into the communication module 10 through the first external interface module 30, converted into a bandwidth vector modulation signal through the ethernet port physical layer 11 and the first FPGA chip 12, and then input into the main control module 20 and the power supply control backplane 40, and a synchronous clock and a timing trigger signal are output through the selected communication protocol in the main control module 20; and sending the synchronous clock and the timing trigger signal to the power supply control back panel 40, transmitting the broadband vector modulation signal and the synchronous clock and the timing trigger signal to the functional module 50 through the power supply control back panel 40, performing signal generation and frequency conversion processing through the functional module 50, outputting a final radio frequency continuous wave signal, and outputting through an output interface to complete the generation of the radio frequency continuous wave signal and the frequency conversion signal, thereby realizing the signal generation based on the FC bus and achieving the technical effect of high-speed data transmission.
According to the signal generating device provided by the embodiment of the invention, the communication module, the main control module, the first external interface module, the power supply control back plate and the function module are arranged, the communication module is internally provided with the Ethernet port physical layer and the first FPGA chip, the input end of the port physical layer is electrically connected with the first output end of the first external interface module, and the output end of the port physical layer is electrically connected with the first input end of the main control module; the input end of the first FPGA chip is electrically connected with the second output end of the first external interface module, the first output end is electrically connected with the second input end of the main control module, and the second output end is electrically connected with the first input end of the power supply control back plate; the third output end of the first external interface module is electrically connected with the third input end of the main control module; the second input end of the power supply control back plate is electrically connected with the output end of the main control module, and the plurality of output ends of the power supply control back plate are electrically connected with the plurality of input ends of the functional modules in sequence. The communication module and the master control module are additionally arranged to be connected with the power supply control back plate, FC bus signals received from the outside are transmitted to the master control module through the communication module, and the bus signals are transmitted to the function module through the power supply control back plate, so that radio frequency continuous wave signals and broadband vector modulation signals are generated. By the scheme, the technical effects of high-speed data transmission and signal generation based on the FC bus can be achieved.
In an alternative aspect of the embodiments of the present invention, the first FPGA chip includes: PCle interface IP, ethernet IP and synchronous logic unit; the output end of the PCle interface IP is electrically connected with the second input end of the main control module; the input end of the Ethernet IP is electrically connected with the second output end of the first external interface module; the first input end of the synchronous logic unit is electrically connected with the fourth output end of the first external interface module, the second input end of the synchronous logic unit is electrically connected with the fifth output end of the first external interface module, and the output end of the synchronous logic unit is electrically connected with the first input end of the power supply control back plate.
In an alternative of the embodiment of the present invention, the function module includes: the system comprises a baseband signal generation sub-module, a radio frequency up-conversion sub-module, a local oscillator sub-module and a switch attenuation sub-module; the input end of the baseband signal generation submodule is electrically connected with the first output end of the power supply control back plate, the first output end of the baseband signal generation submodule is electrically connected with the first input end of the radio frequency up-conversion submodule, and the second output end of the baseband signal generation submodule is electrically connected with the first input end of the local oscillator submodule; the second input end of the local oscillator submodule is electrically connected with the second output end of the power supply control back plate, and the output end of the local oscillator submodule is electrically connected with the second input end of the radio frequency up-conversion submodule; the third input end of the radio frequency up-conversion sub-module is electrically connected with the third output end of the power supply control back plate, and the output end of the radio frequency up-conversion sub-module is electrically connected with the first input end of the switch attenuation sub-module; the second input end of the switch attenuation submodule is electrically connected with the fourth output end of the power supply control back plate, and the output end of the switch attenuation submodule is connected to the output interface.
In an alternative of the embodiments of the present invention, the baseband signal generation sub-module includes: the second FPGA chip, the DA acquisition unit, the first clock unit and the conditioning unit; the input end of the second FPGA chip is electrically connected with the first output end of the power supply control back plate, and the output end of the second FPGA chip is electrically connected with the input end of the DA acquisition unit; the DA acquisition unit comprises a broadband DA acquisition subunit and a calibration DA acquisition subunit, the input end of the broadband DA acquisition subunit is electrically connected with the first output end of the second FPGA chip, the output end of the broadband DA acquisition subunit is electrically connected with the input end of the conditioning unit and the output end of the calibration DA acquisition subunit, and the input end of the calibration DA acquisition subunit is electrically connected with the second output end of the second FPGA chip; the output end of the first clock unit is electrically connected with the second input end of the local oscillator submodule; the output end of the conditioning unit is electrically connected with the first input end of the radio frequency up-conversion submodule.
In an alternative of the embodiment of the present invention, the local oscillation submodule includes: the second clock unit, the frequency multiplication unit, the broadband low-phase noise frequency sweeping unit and the point frequency source unit; the input end of the second clock unit is electrically connected with the second output end of the baseband signal generation submodule, and the output end of the second clock unit is electrically connected with the input end of the frequency doubling unit, the first input end of the broadband low-phase noise frequency sweeping unit and the point frequency source unit respectively; the output end of the frequency doubling unit is electrically connected with the second input end of the broadband low-phase-noise frequency sweeping unit; the output end of the broadband low-phase-noise frequency sweeping unit is electrically connected with the second input end of the radio frequency up-conversion submodule; the local oscillator submodule further comprises a first power supply control unit, the input end of the first power supply control unit is electrically connected with the second output end of the power supply control back plate, and the output end of the first power supply control unit is electrically connected with the other input end of the second clock unit, the other input end of the frequency doubling unit, the third input end of the broadband low-phase noise frequency sweeping unit and the other input end of the point frequency source unit respectively.
In an alternative of the embodiment of the present invention, the radio frequency up-conversion sub-module includes: the device comprises an IQ modulation unit, a filtering unit, a low-frequency signal generation unit and a gain conditioning unit; a first input end of the IQ modulation unit is electrically connected with a first output end of the baseband signal generation submodule, a second input end of the IQ modulation unit is electrically connected with an output end of the local oscillation submodule, a first output end of the IQ modulation unit is electrically connected with an input end of the low-frequency signal generation unit, and a second output end of the IQ modulation unit is electrically connected with an input end of the filtering unit; the output end of the low-frequency signal generating unit is electrically connected with the first input end of the gain conditioning unit; the output end of the filtering unit is electrically connected with the second input end of the gain conditioning unit; the output end of the gain conditioning unit is electrically connected with the second input end of the switch attenuation submodule; the radio frequency up-conversion sub-module further comprises a second power control unit, an input end of the second power control unit is electrically connected with a third output end of the power supply control back plate, and an output end of the second power control unit is electrically connected with a third input end of the IQ modulation unit, a second input end of the filtering unit, a second input end of the low-frequency signal generation unit and a third input end of the gain conditioning unit respectively.
In an alternative aspect of the embodiments of the present invention, the switch attenuation submodule includes: the program-controlled attenuation unit and the third power supply control unit; the first input end of the program-controlled attenuation unit is electrically connected with the output end of the radio frequency up-conversion sub-module, the second input end of the program-controlled attenuation unit is electrically connected with the output end of the third power supply control unit, and the output end of the program-controlled attenuation unit is connected to the output interface; the input end of the third power supply control unit is electrically connected with the fourth output end of the power supply control back plate.
In an alternative of the embodiments of the present invention, the first external interface module includes: the system comprises a debugging interface, a display control interface, an FC optical fiber interface, an SMB second pulse interface and a trigger signal interface; the output end of the debugging interface is electrically connected with the first input end of the communication module; the output end of the display control interface is electrically connected with the second input end of the communication module; the output end of the FC optical fiber interface is electrically connected with the third input end of the communication module; the output end of the SMB second pulse interface is electrically connected with the fourth input end of the communication module; the output end of the trigger signal interface is electrically connected with the fifth input end of the communication module.
In an alternative of the embodiments of the present invention, the apparatus further comprises a second external interface module; and the input end of the second external interface module is electrically connected with the baseband signal generation sub-modules in the functional module in sequence.
In an alternative of the embodiment of the present invention, the second external interface module includes: the system comprises a four-channel external modulation interface, a reference interface and a trigger interface; the output end of the four-channel external modulation interface is electrically connected with the other input end of the modulation unit; the reference interface is electrically connected with the first clock unit; the trigger interface is electrically connected with the second FPGA chip.
In an alternative of the embodiments of the present invention, the apparatus further comprises a power supply; the power supply is electrically connected with the power supply control back plate through the AC-DC converter.
In the following, the first FPGA chip includes: PCle interface IP, ethernet IP and synchronous logic unit, power supply control backplate, first external interface module includes: debugging interface, apparent accuse interface, FC fiber interface, SMB second pulse interface and trigger signal interface, functional module includes: the baseband signal generation sub-module, the radio frequency up-conversion sub-module, the local oscillator sub-module, the switch attenuation sub-module, the second external interface module, and the power supply are described as examples. Referring to fig. 2, a schematic structural diagram of another signal generating apparatus provided in the embodiment of the present invention is shown. The signal generating device is explained on the basis of the above signal generating device. As shown in fig. 2, the signal generating device further includes:
the system comprises a communication module 10, a main control module 20, a first external interface module 30, a power supply control back panel 40 and a functional module 50.
The communication module 10 is provided with an ethernet port physical layer 11 and a first FPGA chip 12.
According to the diagram provided in fig. 2, the first FPGA chip 12 specifically includes:
a PCle interface IP13, an ethernet IP14 and a synchronization logic unit 15.
The output end of the PCle interface IP13 is electrically connected with the second input end of the main control module 20; the input end of the ethernet IP14 is electrically connected to the second output end of the first external interface module 30; the first input terminal of the synchronous logic unit 15 is electrically connected to the fourth output terminal of the first external interface module, the second input terminal is electrically connected to the fifth output terminal of the first external interface module, and the output terminal is electrically connected to the first input terminal of the power supply control backplane.
According to the diagram provided in fig. 2, the communication module 10 uses a large-capacity first FPGA chip 12 as a core, and uses an ethernet IP14, which is an internal logic Internet Protocol (IP) core of the first FPGA chip 12, to implement Media Access Control (MAC) and Physical Layer 11 (PHY) functions of an ethernet port, and meanwhile, cooperates with a processor to run synchronization and trigger logic of a precision clock synchronization Protocol standard (IEEE 1588) synchronization logic unit 15 of a network measurement and Control system, and outputs a synchronization clock, a timing trigger and a 1PPS second pulse synchronization function.
Further, fig. 3 is a schematic structural diagram of an FPGA chip in a communication module according to an embodiment of the present invention. According to the diagram provided in fig. 3, PCIe interface IP13 is used to implement PCIe2.0x4 link interface, and is responsible for interacting with master control module 20; the Ethernet IP14 realizes the functions of gigabit Ethernet MAC and PHY, wherein the gigabit Ethernet MAC is responsible for message transceiving and caching, and performs functional processing such as frame gap, lead code, CRC, timestamp, statistics and the like on the message; a Process Control Systems (PCS) of the ten-gigabit network is responsible for coding and decoding; the high-speed transceiver realizes the interconnection function with the photoelectric conversion module. The IEEE1588 synchronization logic in the synchronization logic unit 15 is used to implement a high-precision network synchronization protocol based on a gigabit network, and provides a pulse-per-second signal, a synchronization clock, and a trigger signal.
Optionally, the main control module 20 uses a CPU as an embedded processor to run an operating system, an IEEE1588V2 protocol stack, and device application services. On one hand, the optical fiber interface of an external gigabit Ethernet FC is realized as a communication interface and a data processing unit of the equipment, the instruction and the data of a main control computer are received, and distributed time synchronization is realized through an IEEE1588V2 protocol (PTP); on the other hand, the inner pair communicates with each PCIe functional module through a PCIe bus, and outputs a synchronous clock and a timing trigger signal through a PTP protocol, thereby realizing synchronous trigger of the front-end conditioning circuit.
As shown in fig. 2, the first external interface module 30 specifically includes:
the device comprises a debugging interface, a display control interface, an FC optical fiber interface, an SMB second pulse interface and a trigger signal interface.
The output end of the debugging interface is electrically connected with the first input end of the communication module; the output end of the display control interface is electrically connected with the second input end of the communication module; the output end of the FC optical fiber interface is electrically connected with the third input end of the communication module; the output end of the SMB second pulse interface is electrically connected with the fourth input end of the communication module; the output end of the trigger signal interface is electrically connected with the fifth input end of the communication module.
Referring to the diagram provided by fig. 2, the signal generating device is in optical fiber communication with an external FC bus through an FC optical fiber interface, so as to realize remote communication; network synchronization with the communication module is realized through an SMB second pulse interface; the trigger signal interface is used for realizing the trigger control of a synchronous logic unit in the communication module and triggering the synchronization and the logic of an IEEE1588 protocol; the debugging interface is generally an IQ external modulation interface and is used for realizing the input of external I +, I-, Q + and Q-four-channel modulation signals; the display control interface is used as an auxiliary interface and is used for being connected with the main control module in an auxiliary mode and controlling the main control module to display the display function of the generated signal parameters or realize the input and output interface of the keyboard and the mouse.
Optionally, the power supply control module 40 is configured to supply power to the communication module 10, the main control module 20, and the function module 50, and the interface is designed to adopt a PCIe gen2.0 x4 link, so as to implement bus communication and expansion, monitor and control the power supply and the temperature of the control platform, and control the operation of the cooling fans installed on the two sides of the device.
Referring to the diagram provided in fig. 2, the functional module 50 specifically includes:
a baseband signal generation sub-module 51, a radio frequency up-conversion sub-module 52, a local oscillator sub-module 53 and a switch attenuation sub-module 54;
optionally, an output interface 55 is disposed outside the device and electrically connected to the functional module in the device.
The input end of the baseband signal generation submodule 51 is electrically connected to the first output end of the power supply control backplane 40, the first output end is electrically connected to the first input end of the radio frequency up-conversion submodule 52, and the second output end is electrically connected to the first input end of the local oscillation submodule 53.
A second input end of the local oscillator submodule 53 is electrically connected to a second output end of the power supply control backplane 40, and an output end of the local oscillator submodule is electrically connected to a second input end of the radio frequency up-conversion submodule 52.
A third input terminal of the rf up-conversion sub-module 52 is electrically connected to a third output terminal of the power supply control backplane 40, and an output terminal thereof is electrically connected to a first input terminal of the switch attenuation sub-module 54.
A second input terminal of the switch attenuation submodule 54 is electrically connected to a fourth output terminal of the power supply control backplane 40, and an output terminal thereof is connected to the output interface 55.
According to the diagram provided in fig. 2, the baseband signal generation sub-module 51 receives the signal provided by the power supply control backplane, and performs the baseband signal processing and storing functions. Meanwhile, the generated signal is transmitted to the rf up-conversion sub-module 52, and the baseband signal is subjected to frequency conversion processing of different frequency bands, gain adjustment is performed, and then output to the switch attenuation sub-module 54. The local oscillation submodule 53 receives the logic control of the synchronous clock of the baseband signal generation submodule and provides a broadband small-step local oscillation signal for the radio frequency up-conversion submodule 52. The switch attenuation submodule 54 performs attenuation processing on the received gain signal to output a high-power dynamic range signal, and outputs the signal through an output interface.
Referring to the illustration provided in fig. 2, a second external interface module 60 is also included in the signal generating device.
The input terminal of the second external interface module 60 is electrically connected to the baseband signal generating sub-module 51 of the functional module 50 in sequence.
Referring to the illustration provided in fig. 2, a power supply is also included in the signal generating device.
The power supply outputs a stable direct current voltage through a 220V power supply and an AC-DC converter, and is electrically connected with the power supply control back plate 40.
For signal transmission with the functional module, a power supply is installed inside the device to supply power to the device by using the second external interface module 60.
The embodiment of the invention provides a signal generating device, which is characterized in that a communication module, a main control module, a first external interface module, a power supply control back plate and a function module are arranged, an Ethernet port physical layer and a first FPGA chip are arranged in the communication module, signals received by a plurality of external interfaces are transmitted to the main control module and the power supply control module through the Ethernet port physical layer and the first FPGA chip, bus signals are transmitted to a baseband signal generating submodule in the function module through the power supply control back plate, generated frequency conversion signals are output to a radio frequency up-conversion submodule and a local oscillator submodule through signal processing, the frequency conversion signals are output to a switch attenuation submodule through the processing of the radio frequency up-conversion submodule, meanwhile, the baseband signal generating submodule keeps clock synchronization with the local oscillator submodule through synchronous clock signals, the control submodule outputs the signals to the radio frequency up-conversion submodule, and finally output signals are output through an output interface after being processed by the switch attenuation submodule, so that the generation of radio frequency continuous wave signals and broadband vector modulation signals is completed. By the scheme, the technical effects of high-speed data transmission and signal generation based on the FC bus can be achieved.
The following communication module, the main control module, the first external interface module, the power supply control backplane, and the baseband signal generation sub-module include: second FPGA chip, DA acquisition unit, first clock unit and conditioning unit, the local oscillator submodule piece includes: second clock unit, frequency multiplication unit, broadband low phase noise sweep frequency unit and dot frequency source unit, the radio frequency up-conversion submodule includes: IQ modulation unit, filtering unit, low frequency signal generation unit and gain conditioning unit, the switch attenuation submodule includes: programme-controlled decay unit and third power control unit, second external interface module includes: the four-channel external modulation interface, the reference interface, the trigger interface and the power supply are taken as examples for description. Referring to fig. 4, a schematic structural diagram of another signal generating apparatus provided in the embodiment of the present invention is shown. The signal generating device is explained on the basis of the first signal generating device. As shown in fig. 4, the signal generating device further includes:
the system comprises a communication module 10, a main control module 20, a first external interface module 30, a power supply control back plate 40, a baseband signal generation sub-module 51, a radio frequency up-conversion sub-module 52, a local oscillator sub-module 53, a switch attenuation sub-module 54, a second external interface module 60 and a power supply.
Optionally, the communication module and the main control module are combined to form a controller, an optical fiber interface is used for realizing an FC bus communication function, and meanwhile, the controller is used as a server for receiving remote commands, controlling each function module and realizing instrument functions of the device; a synthesizer framework is adopted inside, vector signal generation is divided into functional modules such as a baseband signal generation sub-module, a radio frequency up-conversion sub-module, a local oscillator sub-module and a switch attenuation sub-module, and signal generation and frequency conversion are achieved; the internal backboard bus in the peripheral assembly adopts PCIe bus, and the connection between the controller and each functional module adopts bus slot type design.
Referring to the diagram provided in fig. 4, the baseband signal generation sub-module 51 specifically includes:
the device comprises a second FPGA chip, a DA acquisition unit, a first clock unit and a conditioning unit.
The input end of the second FPGA chip is electrically connected with the first output end of the power supply control back plate, and the output end of the second FPGA chip is electrically connected with the input end of the DA acquisition unit; the DA acquisition unit comprises a broadband DA acquisition subunit and a calibration DA acquisition subunit, the input end of the broadband DA acquisition subunit is electrically connected with the first output end of the second FPGA chip, the output end of the broadband DA acquisition subunit is electrically connected with the input end of the conditioning unit and the output end of the calibration DA acquisition subunit, and the input end of the calibration DA acquisition subunit is electrically connected with the second output end of the second FPGA chip; the output end of the first clock unit is electrically connected with the second input end of the local oscillator submodule; the output end of the conditioning unit is electrically connected with the first input end of the radio frequency up-conversion submodule.
According to the diagram provided by fig. 4, the DA acquisition unit may include a wideband DAC and a calibration DAC, and the functions of data transmission and communication with the control backplane bus, algorithm generation of baseband IQ signal waveforms, and the like are completed by the second FPGA chip included in the baseband signal generation sub-module, and the DA acquisition unit realizes the function of fine tuning the common-mode voltage of the four-way quadrature differential baseband signal input.
Optionally, a power control processing circuit is disposed in the baseband signal generation sub-module 51, the local oscillator sub-module 53, and the radio frequency up-conversion sub-module 52, so as to provide power for each sub-module.
Referring to the diagram provided in fig. 4, the local oscillation submodule 53 specifically includes:
the second clock unit, the frequency multiplication unit, the broadband low-phase noise frequency sweeping unit and the point frequency source unit;
the input end of the second clock unit is electrically connected with the second output end of the baseband signal generation submodule, and the output end of the second clock unit is electrically connected with the input end of the frequency doubling unit, the first input end of the broadband low-phase noise frequency sweeping unit and the point frequency source unit respectively; the output end of the frequency doubling unit is electrically connected with the second input end of the broadband low-phase noise frequency sweeping unit; the output end of the broadband low-phase-noise frequency sweeping unit is electrically connected with the second input end of the radio frequency up-conversion submodule; the local oscillator submodule further comprises a first power supply control unit, the input end of the first power supply control unit is electrically connected with the second output end of the power supply control back plate, and the output end of the first power supply control unit is electrically connected with the other input end of the second clock unit, the other input end of the frequency doubling unit, the third input end of the broadband low-phase noise frequency sweeping unit and the other input end of the point frequency source unit respectively.
According to the diagram provided in fig. 4, the clock unit, the frequency multiplication unit, the broadband low-phase noise sweep unit, and the point frequency source unit in the local oscillation submodule 53. A multi-ring phase-locking scheme is adopted to generate 1 path of broadband microwave signals of 100 MHz-20 GHz and 3 paths of broadband microwave signals of 3 GHz-20 GHz, and local oscillation signals required by signal frequency conversion are provided for a radio frequency up-conversion submodule.
Referring to the diagram provided in fig. 4, the radio frequency up-conversion sub-module 52 specifically includes:
the device comprises an IQ modulation unit, a filtering unit, a low-frequency signal generating unit and a gain conditioning unit.
A first input end of the IQ modulation unit is electrically connected with a first output end of the baseband signal generation submodule, a second input end of the IQ modulation unit is electrically connected with an output end of the local oscillation submodule, a first output end of the IQ modulation unit is electrically connected with an input end of the low-frequency signal generation unit, and a second output end of the IQ modulation unit is electrically connected with an input end of the filtering unit; the output end of the low-frequency signal generating unit is electrically connected with the first input end of the gain conditioning unit; the output end of the filtering unit is electrically connected with the second input end of the gain conditioning unit; the output end of the gain conditioning unit is electrically connected with the second input end of the switch attenuation submodule; the radio frequency up-conversion sub-module further comprises a second power supply control unit, an input end of the second power supply control unit is electrically connected with a third output end of the power supply control back plate, and an output end of the second power supply control unit is electrically connected with a third input end of the IQ modulation unit, a second input end of the filtering unit, a second input end of the low-frequency signal generation unit and a third input end of the gain conditioning unit respectively.
According to the diagram provided in fig. 4, the rf up-conversion sub-module includes an IQ modulation unit, a low frequency signal generation unit, a filtering unit, and a gain conditioning unit. The radio frequency up-conversion is realized by combining two channels of 1 MHz-6 GHz and 6 GHz-20 GHz, and the two channels are respectively sent to a switch attenuation submodule after multi-stage frequency conversion, filtering, amplification and conditioning.
Referring to the diagram provided in fig. 4, the switch attenuation submodule 54 includes, in particular:
a program-controlled attenuation unit and a third power supply control unit.
The first input end of the program-controlled attenuation unit is electrically connected with the output end of the radio frequency up-conversion sub-module, the second input end of the program-controlled attenuation unit is electrically connected with the output end of the third power supply control unit, and the output end of the program-controlled attenuation unit is connected to the output interface; the input end of the third power control unit is electrically connected with the fourth output end of the power supply control backboard.
According to the diagram provided in fig. 4, the switch attenuation submodule includes a programmable attenuator and a power control processing circuit. The combination of signals of two frequency bands of 1 MHz-6 GHz and 6 GHz-20 GHz is realized by the switch combination, and then the signals with small power and large dynamic range are output uniformly through the programmable attenuator.
Referring to the diagram provided in fig. 4, the second external interface module 60 specifically includes:
the device comprises a four-channel external modulation interface, a reference interface and a trigger interface.
The output end of the four-channel external modulation interface is electrically connected with the other input end of the modulation unit; the reference interface is electrically connected with the first clock unit; the trigger interface is electrically connected with the second FPGA chip.
The four-channel external modulation interface in the second external interface module 60 is used to implement the output of the external four-channel modulation signal according to the diagram provided in fig. 4. The reference interface and the trigger interface user output a synchronous logic signal and a synchronous clock signal.
According to the signal generating device provided by the embodiment of the invention, the main control module and the communication module are arranged, synchronous and logic signals are provided for the first FPGA chip through the FC bus interface, the signals are transmitted to the power supply control back plate through the main control module, and the signals are transmitted to each functional submodule of the baseband signal generating submodule and then frequency conversion signals and synchronous clock signals are output. The local oscillator submodule is connected under the control of the synchronous clock signal, the signal is output to the radio frequency up-conversion submodule and then the radio frequency continuous wave signal output and the broadband vector modulation signal are output, and the high-precision radio frequency continuous wave signal and the broadband vector modulation signal which are finally obtained are output through an output interface after attenuation processing. Therefore, the technical effects of high-speed transmission and signal generation based on the FC bus can be achieved.
Fig. 5 is a schematic structural diagram of another signal generating device according to an embodiment of the present invention. Fig. 5 is introduced on the basis of a first signal generating device. According to the diagram provided in fig. 5, the signal generating device specifically comprises:
the controller comprises a controller 100, a power supply 200, a PCIe back plate 40, a functional module 50, a baseband signal generation sub-module 51, a radio frequency up-conversion sub-module 52, a local oscillator sub-module 53 and a switch attenuation sub-module 54.
Corresponding to the communication module 10 and the main control chip 20 in the signal generating device in fig. 1 as components of the controller 100, the controller 100 is inserted in the PCIe backplane 40 in a plug-in card manner. The power supply 200 described herein corresponds to the power supply and AC-DC combined module of the signal generating apparatus provided in FIG. 1. The PCIe backplane 40 is the corresponding power control backplane 40 in fig. 1. Referring to the diagram provided in fig. 5, the baseband signal generation sub-module 51, the rf up-conversion sub-module 52, the local oscillator sub-module 53, and the switch attenuation sub-module 54 are independent functional modules 50 respectively, and are inserted into the PCIe backplane 40 in a card-insertion manner.
Optionally, the signal generating device further comprises a fan 300 disposed inside the signal generating device.
Optionally, the device further comprises, outside the front panel:
radio frequency output interface 600, status display lamp 700 and cabinet switch 800.
The device output interface 600 is used to implement signal output in accordance with the diagram provided in fig. 5. The status display lamp 700 is used to display the operating status of the device, and the lamp is turned on to indicate a normal operating status. The case switch 800 is used to control the on/off of the power supply of the device. The device can output radio frequency continuous wave signals in the range of 1MHz to 20GHz and broadband vector modulation signals through the signal generating device, and the device realizes the communication transmission rate of 12.5Gbps through an FC type optical fiber interface.
The signal generating device provided by the embodiment of the invention is characterized in that a controller is formed by combining a gigabit network communication module and a main control module, an FC bus communication function is realized by using an optical fiber interface, and meanwhile, the controller is used as a server for receiving a remote command to control each functional module and realize the instrument function of the device; a synthesizer framework is adopted inside, vector signal generation is divided into functional modules such as a baseband signal generation sub-module, a radio frequency up-conversion sub-module, a local oscillator sub-module and a switch attenuation sub-module, and frequency conversion and generation of signals are achieved; the internal backboard bus in the peripheral assembly adopts PCIe bus, the controller and each functional module are connected by bus slot type design, and the technical effects of high-speed data transmission and signal generation based on FC bus can be realized.
Fig. 6 is a schematic structural diagram of an external interface of a signal generating device according to an embodiment of the present invention. Fig. 6 is introduced on the basis of a first signal generating device. According to the diagram provided in fig. 6, the external interface of the signal generating device specifically includes:
1-power supply, 2-reference input and output, 3-trigger input and output, 4-trigger signal interface, 5-second pulse, 6-2 FC interface, 7-2 network interface, 2 USB and 8-IQ external modulation.
According to the diagram provided in fig. 6, 1-power supply is used to enable device powering. The 2-reference input output is used to achieve reference synchronization of the clock. And the 3-trigger input and output comprises a trigger input and a trigger output interface which are used for realizing signal trigger input and output. The 4-trigger signal interface is used for realizing 1588 trigger. A 5-second pulse is used to achieve network synchronization. And 6-2 FC interfaces are used for FC bus optical fiber communication. 7-2 network ports and 2 USB ports, wherein the network ports are used for realizing debugging of the device under the gigabit network; USB is used to implement a keyboard and mouse interface or a storage interface. 8-IQ external modulation is used to achieve input of an external four-channel modulation signal.
In a possible example scenario, the FC bus-based signal generation device may be installed in a 19-inch cabinet, and connected to a remote control computer through an optical fiber to complete remote data transmission and signal generation, where the IEEE1588 protocol supports high-precision synchronization among different FC bus instruments. User interaction is achieved through a remote control computer. The signal generating device provided by the embodiment of the invention can provide the output of a standard signal source for frequency range measurement, bandwidth measurement, power measurement, sensitivity measurement, anti-interference characteristic test, radio station equipment comprehensive test and the like, and realizes the technical effects of high-speed data transmission and signal generation based on the FC bus.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (11)
1. A signal generating device, comprising:
the system comprises a communication module, a main control module, a first external interface module, a power supply control back plate and a functional module;
an Ethernet port physical layer and a first FPGA chip are arranged in the communication module, the input end of the Ethernet port physical layer is electrically connected with the first output end of the first external interface module, and the output end of the Ethernet port physical layer is electrically connected with the first input end of the main control module;
the input end of the first FPGA chip is electrically connected with the second output end of the first external interface module, the first output end of the first FPGA chip is electrically connected with the second input end of the main control module, and the second output end of the first FPGA chip is electrically connected with the first input end of the power supply control back plate;
the third output end of the first external interface module is electrically connected with the third input end of the main control module;
the second input end of the power supply control back plate is electrically connected with the output end of the main control module, and the plurality of output ends of the power supply control back plate are electrically connected with the plurality of input ends of the functional modules in sequence.
2. The apparatus of claim 1, wherein the first FPGA chip comprises:
PCle interface IP, ethernet IP and synchronous logic unit;
the output end of the PCle interface IP is electrically connected with the second input end of the main control module;
the input end of the Ethernet IP is electrically connected with the second output end of the first external interface module;
the first input end of the synchronous logic unit is electrically connected with the fourth output end of the first external interface module, the second input end of the synchronous logic unit is electrically connected with the fifth output end of the first external interface module, and the output end of the synchronous logic unit is electrically connected with the first input end of the power supply control back plate.
3. The apparatus of claim 1, wherein the functional module comprises:
the system comprises a baseband signal generation sub-module, a radio frequency up-conversion sub-module, a local oscillator sub-module and a switch attenuation sub-module;
the input end of the baseband signal generation submodule is electrically connected with the first output end of the power supply control back plate, the first output end of the baseband signal generation submodule is electrically connected with the first input end of the radio frequency up-conversion submodule, and the second output end of the baseband signal generation submodule is electrically connected with the first input end of the local oscillator submodule;
a second input end of the local oscillator submodule is electrically connected with a second output end of the power supply control back plate, and an output end of the local oscillator submodule is electrically connected with a second input end of the radio frequency up-conversion submodule;
a third input end of the radio frequency up-conversion sub-module is electrically connected with a third output end of the power supply control back plate, and an output end of the radio frequency up-conversion sub-module is electrically connected with a first input end of the switch attenuation sub-module;
and a second input end of the switch attenuation submodule is electrically connected with a fourth output end of the power supply control back plate, and an output end of the switch attenuation submodule is connected to an output interface.
4. The apparatus of claim 3, wherein the baseband signal generation sub-module comprises:
the device comprises a second FPGA chip, a DA acquisition unit, a first clock unit and a conditioning unit;
the input end of the second FPGA chip is electrically connected with the first output end of the power supply control back plate, and the output end of the second FPGA chip is electrically connected with the input end of the DA acquisition unit;
the DA acquisition unit comprises a broadband DA acquisition subunit and a calibration DA acquisition subunit, the input end of the broadband DA acquisition subunit is electrically connected with the first output end of the second FPGA chip, the output end of the broadband DA acquisition subunit is electrically connected with the input end of the conditioning unit and the output end of the calibration DA acquisition subunit, and the input end of the calibration DA acquisition subunit is electrically connected with the second output end of the second FPGA chip;
the output end of the first clock unit is electrically connected with the second input end of the local oscillator submodule;
the output end of the conditioning unit is electrically connected with the first input end of the radio frequency up-conversion submodule.
5. The apparatus of claim 3, wherein the local oscillation submodule comprises:
the second clock unit, the frequency multiplication unit, the broadband low-phase noise frequency sweeping unit and the point frequency source unit;
the input end of the second clock unit is electrically connected with the second output end of the baseband signal generation submodule, and the output end of the second clock unit is electrically connected with the input end of the frequency doubling unit, the first input end of the broadband low-phase noise frequency sweeping unit and the point frequency source unit respectively;
the output end of the frequency doubling unit is electrically connected with the second input end of the broadband low-phase noise frequency sweeping unit;
the output end of the broadband low-phase-noise frequency sweeping unit is electrically connected with the second input end of the radio frequency up-conversion submodule;
the local oscillator submodule also comprises a first power supply control unit, the input end of the first power supply control unit is electrically connected with the second output end of the power supply control backboard, and the output end of the first power supply control unit is respectively electrically connected with the other input end of the second clock unit, the other input end of the frequency doubling unit, the third input end of the broadband low-phase noise frequency sweeping unit and the other input end of the point frequency source unit.
6. The apparatus of claim 3, wherein the radio frequency up-conversion sub-module comprises:
the device comprises an IQ modulation unit, a filtering unit, a low-frequency signal generating unit and a gain conditioning unit;
a first input end of the IQ modulation unit is electrically connected with a first output end of the baseband signal generation submodule, a second input end of the IQ modulation unit is electrically connected with an output end of the local oscillation submodule, a first output end of the IQ modulation unit is electrically connected with an input end of the low-frequency signal generation unit, and a second output end of the IQ modulation unit is electrically connected with an input end of the filtering unit;
the output end of the low-frequency signal generating unit is electrically connected with the first input end of the gain conditioning unit;
the output end of the filtering unit is electrically connected with the second input end of the gain conditioning unit;
the output end of the gain conditioning unit is electrically connected with the second input end of the switch attenuation submodule;
the radio frequency up-conversion sub-module further comprises a second power control unit, an input end of the second power control unit is electrically connected with a third output end of the power supply control back plate, and an output end of the second power control unit is electrically connected with a third input end of the IQ modulation unit, a second input end of the filtering unit, a second input end of the low-frequency signal generation unit and a third input end of the gain conditioning unit respectively.
7. The apparatus of claim 3, wherein the switch attenuation submodule comprises:
a program-controlled attenuation unit and a third power supply control unit;
the first input end of the program-controlled attenuation unit is electrically connected with the output end of the radio frequency up-conversion sub-module, the second input end of the program-controlled attenuation unit is electrically connected with the output end of the third power supply control unit, and the output end of the program-controlled attenuation unit is connected to an output interface;
the input end of the third power supply control unit is electrically connected with the fourth output end of the power supply control back plate.
8. The apparatus of claim 1, wherein the first external interface module comprises:
the system comprises a debugging interface, a display control interface, an FC optical fiber interface, an SMB second pulse interface and a trigger signal interface;
the output end of the debugging interface is electrically connected with the first input end of the communication module;
the output end of the display control interface is electrically connected with the second input end of the communication module;
the output end of the FC optical fiber interface is electrically connected with the third input end of the communication module;
the output end of the SMB second pulse interface is electrically connected with the fourth input end of the communication module;
the output end of the trigger signal interface is electrically connected with the fifth input end of the communication module.
9. The apparatus of claim 6, further comprising a second external interface module;
and the input end of the second external interface module is electrically connected with the baseband signal generation sub-modules in the functional module in sequence.
10. The apparatus of claim 9, wherein the second external interface module comprises: the system comprises a four-channel external modulation interface, a reference interface and a trigger interface;
the output end of the four-channel external modulation interface is electrically connected with the other input end of the modulation unit;
the reference interface is electrically connected with the first clock unit;
the trigger interface is electrically connected with the second FPGA chip.
11. The device of claim 1, further comprising a power source;
the power supply is electrically connected with the power supply control back plate through an alternating current-direct current converter.
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