CN107247252A - Produce the device of multichannel coherent analog signal - Google Patents
Produce the device of multichannel coherent analog signal Download PDFInfo
- Publication number
- CN107247252A CN107247252A CN201710522651.0A CN201710522651A CN107247252A CN 107247252 A CN107247252 A CN 107247252A CN 201710522651 A CN201710522651 A CN 201710522651A CN 107247252 A CN107247252 A CN 107247252A
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- signal
- qduc
- circuit
- power splitter
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4004—Means for monitoring or calibrating of parts of a radar system
- G01S7/4008—Means for monitoring or calibrating of parts of a radar system of transmitters
Abstract
The invention discloses a kind of device for producing multichannel coherent analog signal, mainly solution prior art generation signal kinds are single, and frequency band is narrow, the drawbacks of being difficult to expand.It includes outside source (1), simulation power splitter (2), 960M frequency sources, signal generator (4) and digital power splitter (5), outside source (1) is connected with simulation power splitter (2), produce the sine wave that two-way frequency is 16MHz, 960M frequency sources (3) are wherein sent to all the way, to produce the frequency of ten road coherents as 960MHz reference signal；Signal generator is sent on another road, is completed to the register configuration in signal generator；Digital power splitter (5) is bi-directionally connected with signal generator (4), completes the transmission of synchronizing signal；Signal generator receives the cardinal data that external equipment is provided, the analog signal of output multi-channel coherent.It is of the invention can output multi-channel frequency band range is wide, the analog signal more than signal kinds, available for radar transmitter.
Description
Technical field
The invention belongs to Radar Signal Processing Technology field, more particularly to a kind of dress for producing multichannel coherent analog signal
Put, available for radar transmitter.
Background technology
Coherent refers to there is fixed phase relation between two or more signals, in some radar test applications
In, generally require to produce the radio frequency or microwave signal of multi-channel Time synchronization or phase coherent.Traditional multichannel coherent signal is produced
Method has following two：
1st, a system is built using many high performance signal sources, wherein there is provided same as main equipment for a signal source
Clock and trigger signal are walked, other signal sources receive the synchronised clock and trigger signal of main equipment generation and produced as slave unit
The raw clock signal synchronous with main equipment.The deficiency that the method for this system built using many signal sources is present is, per many
Coherent signal all the way is produced, then needs many signal sources, when needing to produce tens tunnels even hundreds of road coherent signal, the party
Method can not be applicable.
2nd, based on if sampling theorem, using the side of the High-Speed Signal-Generator of multi-path digital-control oscillator NCO concurrent workings
Case, completes high-speed digital signal using on-site programmable gate array FPGA and produces part, complete using high-performance analog-digital chip
Into simulation output part.FPGA produces synchronizing signal and data, and multichannel coherent just can be produced after multiple analog-digital chips
Analog signal.According to sampling thheorem, the signal frequency of this method output is limited to FPGA internal clock frequencies, therefore the party
Method is applied to situation of the frequency analog signal of generation within tens megahertzs, when desired signal frequency is up to a hundred megahertzs
During situation, this method just can not meet requirement.
The patent application " multichannel coherent signal frequency synthesizer " that Sichuan Chengdu Lian Bang microwave communication projects Co., Ltd carries
(the publication number CN 202679346B of patent application CN 201220383269.9) discloses multichannel coherent signal frequency synthesizer.Should
Multichannel coherent frequency synthesizer disclosed in patent application includes PC, motherboard, control circuit, direct digital synthesizer DDS
Circuit, crystal oscillator, phase-locked loop pll, No. 16 frequency mixers and delay circuit, the control circuit include a master controller and three from
Controller, main DDS and three of the DDS circuit bag one is from DDS, wherein main DDS is connected with master controller, three from DDS with
Three are connected from controller, obtain the control signal of control circuit output, the PLL produces two kinds of signals, respectively as 16 tunnels
The local oscillation signal and intermediate-freuqncy signal of frequency mixer, main DDS and master controller control the clock from DDS simultaneously, so that four 4 tunnels
DDS produces high-resolution, Low phase noise, amplitude-phase uniformity signal, and control circuit obtains the control signal of PC by motherboard,
Compensate the phase of each passage, Magnitude Difference in DDS circuit.
The deficiency of multichannel coherent signal frequency controller presence is disclosed in the patent, first, the DDS cores that this method is selected
Piece is only capable of realizing the agile on waveform frequency, and output waveform is single, it is impossible to suitable for output nonlinear FM signal, noise signal
Deng the situation of complicated wave form；Secondly, the DDS chip AD9959 internal sampling frequencies that this method is used are only up to 500MHz, defeated
Go out that waveform frequency resolution ratio is relatively low, frequency band is narrow；Finally, the coherent technology that this method is used is controlled respectively using four block controllers
Four road DDS chips, control circuit is complicated and expansion is not strong.
The content of the invention
It is an object of the invention to the deficiency for above-mentioned prior art, a kind of generation multichannel coherent analog signal is proposed
Device, to increase the species of output signal, improves the frequency bandwidth of output signal, expands the application of signal simulator.
To achieve the above object, the present invention produces the device of multichannel coherent analog signal, including outside source, simulation work(
Divide device, 960M frequency sources, signal generator and digital power splitter, it is characterised in that：
The signal generator includes：Base band data generation circuit, control circuit, the quadrature DUC being sequentially connected
QDUC circuits and filter circuit；
Digital power splitter is connected across between control circuit and QDUC circuits, forms the feedback circuit of synchronizing signal；
Simulation power splitter is with controlling the input of circuit to be connected, for receiving configurable clock generator；
960M frequency sources are connected with the input of QDUC circuits, for receiving reference clock.
Said apparatus, it is characterised in that digital power splitter includes power-devided circuit and power circuit；
The power-devided circuit, its input is connected with QDUC circuits, for producing Multi-path synchronous signal；Its output end and control
Circuit processed is connected, the synchronizing signal for sending coherent；
The power circuit, its power-devided circuit is connected, for providing operating voltage for power-devided circuit.
Above-mentioned device, it is characterised in that base band data generation circuit includes 1 the first programmable logic array FPGA1,1
Individual DDR3 memories, 1 the first fiber optic receiver and 10 fiber optic transmitters；
The FPGA1 and DDR3 is bi-directionally connected, for the storage and reading for caching the data for receiving and sending, controlling DDR3
With the reception and transmission of control data；
First fiber optic receiver is connected with FPGA, the base band data for receiving external equipment transmission；
10 fiber optic transmitters are connected with FPGA, the data for sending DDR3 storages.
Above-mentioned device, it is characterised in that control circuit includes 1 the second programmable logic array FPGA2,2 four work(point
Device and 1 the second fiber optic receiver；
The FPGA2 is bi-directionally connected with the second fiber optical transceiver, the transmission for receiving base band data and control data；
2 four power splitters, its input with QDUC circuits is connected, for providing reference clock for QDUC circuits
And synchronizing signal.
Above-mentioned device, it is characterised in that quadrature DUC QDUC circuits include a main QDUC chip and three from
QDUC chips；
The main QDUC chips are connected with the input of digital power splitter, for sending synchronizing signal；
The main QDUC chips and three be connecteds from QDCU chips with control circuit, for receiving base band data, controlling
Signal and synchronizing signal.
Above-mentioned device, it is characterised in that filter circuit includes 4 low pass filter LPF, its respectively with QDUC circuits
4 QDUC chips correspondence connect, the pure signal for obtaining.
Above-mentioned device, it is characterised in that 960M frequency sources include：The frequency multiplier circuit that is sequentially connected, power amplification circuit and
Bandwidth-limited circuit, is the sinusoidal signal that 960MHz, power are 17dbm for producing frequency.
Above-mentioned device, it is characterised in that the outside source is connected with simulating the input of power splitter, for producing
Two-way frequency is that 16MHz, power are the sine wave that 10dBm, first phase are 0.
The present invention has the following advantages compared with prior art：
First, the present invention use quadrature DUC chip QDUC chips, not only can with output linearity FM signal, just
The signal of the rule such as string signal, and can the irregular signal, output signal kind such as output nonlinear FM signal, noise signal
Class is more, and frequency band range is wide；
Second, the present invention provides coherent using simulation power splitter, digital power splitter and 960M frequency sources for multi-disc QDUC
Reference clock and synchronizing signal, can be achieved the analog signal of output multi-channel coherent, and autgmentability is extremely strong.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the overall structure block diagram of the embodiment of the present invention；
Fig. 2 is the structured flowchart of signal generator during the present invention is implemented；
Fig. 3 is the structured flowchart of 960M frequency sources in the embodiment of the present invention；
Fig. 4 is the overall theory structure block diagram of the embodiment of the present invention；
Fig. 5 is the base band data form schematic diagram of signal generator in the embodiment of the present invention.
Embodiment：
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the present invention is further described.
Referring to Fig. 1, the device of the multichannel coherent analog signal of the present embodiment, including outside source 1, simulation power splitter 2,
960M frequency sources 3, signal generator 4 and digital power splitter 5, the outside source 1 is connected with simulation power splitter 2, for producing
Raw two-way frequency is that 16MHz, power are the sine wave that 10dBm, first phase are 0, wherein 960M frequency sources 3 are sent to all the way, to produce
The frequency of ten road coherents is that 960MHz, power are the sine wave signal that 1dbm, first phase are 0；Signal generator 4 is sent on another road,
Complete to the register configuration in signal generator 4.The digital power splitter 5 is bi-directionally connected with signal generator 4, signal production
Raw device 4 inputs synchronizing signal all the way to data power splitter 5, and data power splitter 5 exports ten tunnel synchronizing signals after work(point, and this ten
Any multichannel analog signals for being sent to signal generator 4 all the way, being exported for sync generator 4 in the synchronizing signal of road.
Referring to Fig. 2 and Fig. 4, described signal generator 4 includes base band data generation circuit 41, control circuit 42, orthogonal
Digital Up Convert QDUC circuits 43 and filter circuit 44, these circuits are sequentially connected, the simulation for realizing output multi-channel coherent
Signal.Wherein：
The base band data generation circuit 41 include the first programmable logic array FPGA1, memory DDR3, one
First fiber optic receiver and ten fiber optic transmitters, wherein the first fiber optic receiver receives the base band number that external equipment is sended over
According to, by the first programmable logic array FPGA1 caching after, deposit DDR3 memories in, when DDR3 receive transmission data refer to
When making, DDR3 data are divided into the duplicate base band data in ten roads respectively by ten by the first programmable logic array FPGA1
Individual fiber optical transceiver delivers to control circuit 42.As described in Figure 5, it includes frame head, message, data and postamble four to the base band data
Part, the frame head and trailer sections are the binary number of 8 16, and message is the binary number of 24 16, data division
For the binary number of 16, data volume N and the numerical value represented by the 18th bit in message of data division are consistent.
The quadrature DUC QDUC circuits 43 include a main QDUC chip and three from QDUC chips, the master
QDUC chips are connected with digital power splitter, the synchronizing signal for exporting ten road coherents, and this 3 receive synchronous letter from QDUC chips
Number, for realizing that multi-disc QDUC chips export coherent analog signal.
The control circuit 42 includes a second programmable logic array FPGA2, two four power splitters and one second
Fiber optic receiver, second fiber optic receiver is connected with any one in ten fiber optic transmitters of base band generation circuit 41,
The second programmable logic array FPGA2 is sent to for receiving base band data, and base band data；In two four power splitters
One power splitter A of power splitter four is used to reference clock be divided into four tunnels, and quadrature DUC QDUC circuits 43 are sent to respectively
Four QDUC chips, the reference clock of coherent is provided for four QDUC chips, second work(in two four power splitters point
The power splitter B of device four is used to synchronizing signal be divided into four tunnels, and four QDUC of quadrature DUC QDUC circuits 43 are sent to respectively
Chip, the synchronised clock of coherent is provided for four QDUC chips；Second programmable logic array FPGA2 is selected
EP4CGX30CF23I7 models, preamble detecting, message decoding, packet and postamble are carried out to the base band data received successively
Detection process, when detecting frame head and postamble is completely correct, represents that the frame base band data transmission is correct, and simultaneously to four
QDUC chips synchronize configuration, when detection frame head or postamble stagger the time, represent that the frame data are invalid, and abandon the frame number simultaneously
According to.Control to bridge digital power splitter 5 between circuit 42 and QDUC circuits 43, form the feedback circuit of synchronizing signal；
The filter circuit 44 includes four duplicate low pass filter LPF, respectively with main QDUC chips and 3 from
QDUC chips are connected, for filtering out high frequency spurs signal, the performance of analog signal needed for lifting.
Referring to Fig. 3, described 960M frequency sources 3 include frequency multiplier circuit 31, work(point amplifying circuit 32 and bandwidth-limited circuit
33, these circuits are sequentially connected, and are the sinusoidal signal that 960MHz, power are 1dbm, the ten roads signal for producing ten tunnel frequencies
In it is any be sent to signal generator 4 all the way, be used as the reference clock of four QDUC chips in signal generator 4.
Reference picture 1 and Fig. 4, the operation principle of the present embodiment are as follows：
It is that 16MHz, power are the sine wave that 13dBm, first phase are 0 that outside source 1, which provides frequency, gives simulation power splitter 2；
Simulation power splitter 2 is received after the signal of the offer of outside source 1, and output two-way frequency is that 16MHz, power are 10dBm, first phase
For 0 sine wave, wherein giving 960M frequency sources 3 all the way, the first programmable logic array FPGA1 is given on another road；FPGA1 connects
Base band data and the 16MHz signals of the simulation output of power splitter 2 that external equipment is provided are received, base band data is cached in memory
In DDR3, data controlling signal is produced using the 16MHz signals, base band data and control signal are periodically sent to control electricity
The second programmable logic array FPGA2 in road；FPGA2 is received after base band data and control signal, successively to base band data
Cached and detection process, extract the configuration information that outgoing packet contains, the control signal sended over reference to FPGA1 is completed
To main QDUC chips and 3 configurations from QDUC chips, the register more new signal IO_UPDATE that wherein FPGA2 is sent needs
Main QDUC chips and 3 are given simultaneously from QDUC chips, to ensure that four QDUC chips export the waveform of coherent；Main QDUC chips
Synchronizing signal SYN_IN is exported to digital power splitter 5, synchronizing signal SYN_IN is divided into 10 tunnels by digital power splitter 5, and 10 tunnel is same
Any signal all the way in step signal gives the power splitter B of the second power splitter four, produces SYN_IN points of the synchronizing signal of four road coherents
Main QDUC and 3 is not given from QDUC；960M frequency sources 3 export the 960MHz sine waves of 10 road coherents, the 10 road reference clock
In any signal all the way give the power splitter A of the first power splitter four, produce the reference clock REF_CLK of four road coherents, send respectively
To main QDUC chips and 3 from QDUC chips；Main QDUC chips and 3 base band datas sent from QDUC chips reception FPGA2,
Digital Up Convert processing is carried out, it is each to export the required intermediate-freuqncy signal of user all the way, after low pass filter LPF, finally
Export the multichannel coherent analog signal required for user.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (8)
1. a kind of device for producing multichannel coherent analog signal, including outside source (1), simulation power splitter (2), 960M frequencies
Source (3), signal generator (4) and digital power splitter (5), it is characterised in that：
The signal generator (4) includes：Base band data generation circuit (41), control circuit (42), the orthogonal function being sequentially connected
Word up-conversion QDUC circuits (43) and filter circuit (44)；
Digital power splitter (5) is connected across between control circuit (42) and QDUC circuits (43), forms the feedback circuit of synchronizing signal；
Simulation power splitter (2) is connected with the input of control circuit (42), for receiving configurable clock generator；
960M frequency sources (3) are connected with the input of QDUC circuits (43), for receiving reference clock.
2. device according to claim 1, it is characterised in that：Digital power splitter (5) includes power-devided circuit (51) and power supply
Circuit (52)；
The power-devided circuit (51), its input is connected with QDUC circuits (43), for producing Multi-path synchronous signal；Its output end
Be connected with control circuit (42) it is connected, the synchronizing signal for sending coherent；
The power circuit (52), its output end is connected with power-devided circuit (51), for providing work electricity for power-devided circuit (51)
Pressure.
3. device according to claim 1, it is characterised in that：Base band data generation circuit (41), which includes 1 first, to be compiled
Journey logic array FPGA1,1 DDR3 memory, 1 the first fiber optic receiver and 10 fiber optic transmitters；
The first programmable logic array FPGA1 and DDR3 is bi-directionally connected, for caching the data for receiving and sending, control
DDR3 storage and reading and the reception and transmission of control data；
First fiber optic receiver is connected with the first programmable logic array FPGA1, the base for receiving external equipment transmission
Band data；
10 fiber optic transmitters are connected with the first programmable logic array FPGA1, the data for sending DDR3 storages.
4. device according to claim 1, it is characterised in that：Circuit (42) is controlled to include 1 the second FPGA battle array
Arrange FPGA2,2 four power splitters and 1 the second fiber optic receiver；
The second programmable logic array FPGA2 is bi-directionally connected with the second fiber optical transceiver, for receiving base band data and control
The transmission of data processed；
2 four power splitters, its input with QDUC circuits (43) is connected, for providing reference for QDUC circuits (43)
Clock and synchronizing signal.
5. device according to claim 1, it is characterised in that：Quadrature DUC QDUC circuits (43) include a master
QDUC chips and three are from QDUC chips；
The main QDUC chips are connected with the input of digital power splitter (5), for sending synchronizing signal；
The main QDUC chips and three be connecteds from QDCU chips with control circuit (42), for receiving base band data, controlling
Signal and synchronizing signal.
6. device according to claim 1, it is characterised in that：Filter circuit (44) includes 4 low pass filter LPF, its
Connection corresponding with 4 QDUC chips in QDUC circuits (43), the pure signal for obtaining respectively.
7. device according to claim 1, it is characterised in that：960M frequency sources (3) include：The frequency multiplier circuit being sequentially connected
(31), work(point amplifying circuit (32) and bandwidth-limited circuit (33), is that 960MHz, power are 17dbm for producing channelized frequencies
Sinusoidal signal.
8. device according to claim 1, it is characterised in that：The outside source (1) is defeated with simulation power splitter (2)
Enter end to be connected, be that 16MHz, power are the sine wave that 10dBm, first phase are 0 for producing two-way frequency.
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| CN201710522651.0A CN107247252A (en) | 2017-06-30 | 2017-06-30 | Produce the device of multichannel coherent analog signal |
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| CN201710522651.0A CN107247252A (en) | 2017-06-30 | 2017-06-30 | Produce the device of multichannel coherent analog signal |
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| CN108429580A (en) * | 2018-02-08 | 2018-08-21 | 武汉邮电科学研究院有限公司 | The measuring system and method for arbitrary point OSNR in a kind of optic communication links |
| CN111521977A (en) * | 2020-04-22 | 2020-08-11 | 安徽华可智能科技有限公司 | Radar signal source |
| CN112219354A (en) * | 2018-06-12 | 2021-01-12 | 三菱电机株式会社 | Radio Frequency (RF) transmitter and RF transmission method |
| CN113992236A (en) * | 2021-11-18 | 2022-01-28 | 阎镜予 | GNSS pseudo satellite time frequency cascade type synchronization system |
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| CN108429580A (en) * | 2018-02-08 | 2018-08-21 | 武汉邮电科学研究院有限公司 | The measuring system and method for arbitrary point OSNR in a kind of optic communication links |
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| CN112219354B (en) * | 2018-06-12 | 2022-02-01 | 三菱电机株式会社 | Radio Frequency (RF) transmitter and RF transmission method |
| CN111521977A (en) * | 2020-04-22 | 2020-08-11 | 安徽华可智能科技有限公司 | Radar signal source |
| CN113992236A (en) * | 2021-11-18 | 2022-01-28 | 阎镜予 | GNSS pseudo satellite time frequency cascade type synchronization system |
| CN116578164A (en) * | 2023-07-13 | 2023-08-11 | 中星联华科技（北京）有限公司 | Multichannel coherent signal generating device and multichannel coherent signal source |
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