CN104617926B - A kind of swallow pulse formula clock synchronization circuit - Google Patents
A kind of swallow pulse formula clock synchronization circuit Download PDFInfo
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- CN104617926B CN104617926B CN201510053179.1A CN201510053179A CN104617926B CN 104617926 B CN104617926 B CN 104617926B CN 201510053179 A CN201510053179 A CN 201510053179A CN 104617926 B CN104617926 B CN 104617926B
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- 230000001360 synchronised effect Effects 0.000 claims abstract description 17
- 238000007688 edging Methods 0.000 claims abstract description 12
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- 210000001367 artery Anatomy 0.000 claims description 2
- 210000003462 vein Anatomy 0.000 claims description 2
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000003111 delayed effect Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000012952 Resampling Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
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Abstract
The invention discloses a kind of swallow pulse formula clock synchronization circuit, including edging trigger selection circuit, its input is connected with lock-out pulse input signal caused by master chip；Step-by-step movement variable delay circuit, its input are connected with from lock-out pulse output signal caused by chip；The output end of the edging trigger selection circuit is connected to the input of XOR gate with the output end of step-by-step movement variable delay circuit, to carry out xor operation；The output of the XOR gate synchronizes clock output all the way after swallow pulse circuit detects, and another way feeds back to the step-by-step movement variable delay circuit by synchronous pulse-generating circuit.Circuit of the present invention does not need high speed reset signal to produce chip, simplifies the design of circuit board, reduces the complexity of system, advantageously reduce the cost of system, also reduces the difficulty of debugging circuit board.
Description
Technical field
The present invention relates to a kind of swallow pulse formula clock synchronization circuit.
Background technology
At present, high--speed multi--channel data acquisition system usually contains multiple data conversion chips, in the most of this kind of system
, it is necessary to which the data flow that each passage is gathered to gained is accurately alignd in time in number application so that multichannel collecting system
There is delay that is identical or determining between the data of collection and the analog signal of input, in order to follow-up Data Management Analysis, this is just
It is required that the output signal for being distributed in multiple data conversion chips of different physical locations is overturn at the time of identical or determination, this will
Seek the clock signal stringent synchronization of multiple data conversion chip internals.
In order to realize the synchronization of multi-chip clock, traditional solution has two kinds：Synchronous reset mode and swallow pulse mode.
Synchronous reset mode is by the lock-out pulse of one high speed of each chip while transmission, being answered while realizing each chip
Position.Nondeterministic statement caused by being overlapped in order to avoid reset signal with clock edges, should ensure that reset signal and chip
Clock signal meet suitable delay relation, meanwhile, the rise/fall of reset signal is along also must be precipitous enough.In order to full
Sufficient these requirements, it usually needs extra high-speed synchronous pulses generation chip and manual debugging process repeatedly.Thus while
Synchronous reset mode is relatively simple in principle, and the realization of its hardware is not easy to, to pulse-generating circuit and board design
Requirement it is higher, particularly after clock frequency reaches more than GHz, the process of debugging is more difficult.
Swallow pulse mode is per subsynchronous two adjacent chips, there is provided the chip of synchronization pulse (reference signal) is referred to as
Master chip, it is referred to as by synchronizing chip from chip.Its general principle is that master chip is produced into synchronization pulse and out of chip
Synchronization pulse compares caused by portion, if detecting that both have differences, the high-frequency clock out of chip just is pruned into one
Individual pulse signal, a pulse " being gulped down " is shown as in time domain waveform and is fallen.Generally by chip internal by frequency dividing caused by most
The clock of low speed is as lock-out pulse.By the process of multiple swallow pulse, the clock signal and adjacent chips of final chip internal
Interior clock reaches synchronous.The process that synchronous chip repeats swallow pulse with adjacent chip again is completed, until owning in system
Chip all reaches synchronous.Traditional swallow pulse method of synchronization requires the synchronization pulse of master chip and the lock-out pulse from chip
Signal has identical delay path, needs to increase extra port for this chip to receive oneself caused and other chips production
Raw synchronization pulse.The path delay of the self-loop of synchronization pulse and master chip synchronization pulse needs strict phase
Deng, to board design require it is higher, after particularly clock frequency reaches more than GHz, the nuance of circuit board trace all may be used
It can cause synchronization failure.
The content of the invention
The defects of the present invention seeks to exist for prior art, provides a kind of swallow pulse formula clock synchronization circuit, the circuit
The self-loop of conventional synchronization pulse signal is eliminated, increases step-by-step movement variable delay circuit in chip internal, is deposited by inside
The suitable delay of device configuration selection, the program reduces high-speed chip synchronously required port number, while simplifies circuit board
Design, reduces the requirement of board design, improves the convenience that chip uses.
The present invention to achieve the above object, adopts the following technical scheme that：A kind of swallow pulse formula clock synchronization circuit, including side
Along triggering selection circuit, its input is connected with lock-out pulse input signal caused by master chip；Step-by-step movement variable delay circuit,
Its input is connected with from lock-out pulse output signal caused by chip；The output end of the edging trigger selection circuit and stepping
The output end of formula variable delay circuit is connected to the input of XOR gate, to carry out xor operation；The output of the XOR gate is led to
After crossing swallow pulse circuit detection, clock output is synchronized all the way, and another way feeds back to described by synchronous pulse-generating circuit
Step-by-step movement variable delay circuit.
Further, the edging trigger selection circuit includes the latch Latch and edge triggered flip flop being sequentially connected in series
DFF；The signal input part D of the latch Latch is connected with lock-out pulse input signal, and its signal output part Q touches with described
Send out device DFF signal input part D connections；The Enable Pin CLK of the latch Latch and the output end of OR gate connect；It is described or
The first input end of door is connected with clock input signal, and the second input is connected with triggering edge selection signals；Touch at the edge
The signal output part Q and XOR gate that send out device DFF first input end connect；The Enable Pin CLK of the edge triggered flip flop DFF and when
Clock input signal connects.
Further, the step-by-step movement variable delay circuit includes multiple delayed-trigger DFF being sequentially connected in series, wherein setting
Put and be connected in the delayed-trigger DFF of input side signal input part D with the lock-out pulse output signal；It is each described
Delayed-trigger DFF Enable Pin CLK is connected with clock input signal, each delayed-trigger DFF signal output
Hold Q connections corresponding with the input of MUX respectively, the output end of the MUX and the second of the XOR gate
Input connects.
Beneficial effects of the present invention：Circuit of the present invention does not need high speed reset signal to produce chip, simplifies circuit board
Design, the complexity of system is reduced, advantageously reduce the cost of system, also reduce the difficulty of debugging circuit board.
Traditional swallow pulse formula clock synchronization circuit is contrasted, eliminates the conventional synchronization pulse signal in chip exterior oneself
Loop, increase step-by-step movement variable delay circuit in chip internal, pass through the suitable delay of internal register configuration selection, the program
Reduce high-speed chip synchronously required port number, while simplify board design, reduce the requirement of board design,
Improve the convenience that chip uses.
Brief description of the drawings
Fig. 1 is traditional multichip synchronization system connection diagram.
Fig. 2 is multichip synchronization system connection diagram of the present invention.
Fig. 3 is chip internal synchronous circuit theory diagram of the present invention.
Fig. 4 is the time diagram of synchronizing process of the present invention.
Fig. 5 is that lock-out pulse of the present invention delay and the corresponding relation of delay selection signal and the selection of triggering edge are illustrated
Figure.
Embodiment
The multi-chip connected mode of the improved swallow pulse formula clock synchronization circuit that this programme is proposed as shown in Fig. 2 by
One has been reduced in the number of clock terminal mouth, traditional swallow pulse method of synchronization of comparison diagram 1, the port number of chip
The number of mesh and interconnection line all greatly reduces.The improved swallow pulse formula clock synchronization circuit that this programme is proposed, its essence are
The self-loop link of synchronization pulse in traditional swallow pulse formula clock synchronization circuit is eliminated, increases step-by-step movement in chip internal
Variable delay circuit completes similar functions.
Shown in Fig. 3, it is related to a kind of swallow pulse formula clock synchronization circuit of the present invention, including edging trigger selection circuit, its
Input is connected with lock-out pulse input signal caused by master chip；Step-by-step movement variable delay circuit, its input with from chip
Caused lock-out pulse output signal connection；The output end of the edging trigger selection circuit and step-by-step movement variable delay circuit
Output end is connected to the input of XOR gate, to carry out xor operation；The output of the XOR gate is detected by swallow pulse circuit
Afterwards, clock output is synchronized all the way, and another way feeds back to the step-by-step movement variable delay electricity by synchronous pulse-generating circuit
Road.
Wherein, the edging trigger selection circuit includes the latch Latch and edge triggered flip flop DFF being sequentially connected in series；
The signal input part D of the latch Latch is connected with lock-out pulse input signal, its signal output part Q and the trigger
DFF signal input part D connections；The Enable Pin CLK of the latch Latch and the output end of OR gate connect；The OR gate
First input end is connected with clock input signal, and the second input is connected with triggering edge selection signals；The trigger DFF's
The first input end of signal output part Q and XOR gate connects；The Enable Pin CLK of the edge triggered flip flop DFF believes with clock input
Number connection.
Wherein, the step-by-step movement variable delay circuit includes multiple delayed-trigger DFF being sequentially connected in series, and is provided with
The first delayed-trigger DFF signal input part D is connected with the lock-out pulse output signal；Each trigger
DFF Enable Pin CLK is connected with clock input signal, each delayed-trigger DFF signal output part Q respectively with it is more
The input of road selector is corresponding to be connected, and the output end of the MUX is connected with the second input of the XOR gate.
Operation principle is：The lock-out pulse input signal of master chip, snapped to first by edging trigger selection circuit interior
The rising edge of portion's clock.And by from lock-out pulse output signal caused by chip oneself, then passing through step-by-step movement variable delay circuit
After adjustment delay, xor operation is carried out with the lock-out pulse input signal Jing Guo resampling.Swallow pulse circuit can detect XOR gate
Output result, when rising edge occurs in the result of XOR, then gulp down a clock signal pulse.Arteries and veins is gulped down by repetitious
After punching operation, the lock-out pulse input signal after final resampling and the lock-out pulse output signal after variable delay circuit
Reach consistent.The time diagram of synchronizing process is as shown in Figure 4.
Illustrated below to triggering the selection at edge and the delayed selection culture of step-by-step movement variable delay circuit.Selection is suitable
Triggering edge, be in order to avoid lock-out pulse input signal conflicts with the edge of internal clocking, cause d type flip flop sampled result
It is uncertain.Therefore the alignment relation according to the edge of lock-out pulse input signal and the edge of internal clock signal is needed, to select
Suitable triggering edge is selected, ensures that the d type flip flop in edging trigger selection circuit has and enough establishes the retention time.Step-by-step movement can
Become the delayed selection culture of delay circuit, be to increase the delay from the lock-out pulse output signal of chip, make the delay and main core
The delay of the lock-out pulse input signal of piece offsets.Due to triggering the difference at edge, it can also cause master chip lock-out pulse defeated
Enter the delay difference of signal, therefore the delayed selection culture needs the selection with triggering edge to coordinate, both collective effects are reached delay and supported
The purpose to disappear.Fig. 5 gives the schematic diagram of an appropriate value, and lock-out pulse delay therein refers to synchronous caused by master chip
Pulse signal reaches the predicted delay time from chip.For example, when lock-out pulse delay is 1.5T (T is clock frequency), should
It is 2 to set the delayed selection culture, and the selection of triggering edge is 1.Lock-out pulse delay can be by emulating or testing acquisition.
The present invention is especially suitable for the chip chamber of more than 1GHz more ADC, DAC systems or other high-speed digital systems is same
Step.
1st, it will be moved from the synchronization pulse path of chip to chip internal, reduce port and the interconnection line of chip
Number.
2nd, trigger edge selection and step-by-step movement variable delay device cooperates, ensure that internal latency can be same with master chip
Step pulse signal delay offsets, and realizes synchronizing process.
3rd, triggering the length of delay of edge selection and step-by-step movement variable delay device be able to can be covered various by software merit rating
Different lock-out pulse length of delays.
In addition, multi-chip clock synchronization circuit proposed by the invention had both gone for multichannel ADC, DAC system,
Going for other has the multichip system of clock synchronisation requirement.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (3)
- A kind of 1. swallow pulse formula clock synchronization circuit, it is characterised in that including edging trigger selection circuit, its input and main core Lock-out pulse input signal caused by piece connects；Step-by-step movement variable delay circuit, its input with from synchronous arteries and veins caused by chip Rush output signal connection；The output end and the output end of step-by-step movement variable delay circuit of the edging trigger selection circuit are connected to The input of XOR gate, to carry out xor operation；The output of the XOR gate synchronizes all the way after swallow pulse circuit detects Clock exports, and another way feeds back to the step-by-step movement variable delay circuit by synchronous pulse-generating circuit.
- 2. swallow pulse formula clock synchronization circuit as claimed in claim 1, it is characterised in that the edging trigger selection circuit bag Include the latch Latch and edge triggered flip flop DFF being sequentially connected in series；The signal input part D of the latch Latch with it is synchronous Pulse input signal is connected, and its signal output part Q is connected with the signal input part D of the trigger DFF；The latch Latch Enable Pin CLK and the output end of OR gate connect；The first input end of the OR gate is connected with clock input signal, the Two inputs are connected with triggering edge selection signals；The signal output part Q of the edge triggered flip flop DFF and the first of XOR gate is defeated Enter end connection；The Enable Pin CLK of the edge triggered flip flop DFF is connected with clock input signal.
- 3. swallow pulse formula clock synchronization circuit as claimed in claim 2, it is characterised in that the step-by-step movement variable delay circuit Including multiple delayed-trigger DFF being sequentially connected in series, the signal input in the delayed-trigger DFF of input side is provided with End D is connected with the lock-out pulse output signal；Each delayed-trigger DFF Enable Pin CLK inputs with clock to be believed Number connection, each delayed-trigger DFF signal output part Q is corresponding with the input of MUX respectively to be connected, institute The output end of MUX is stated to be connected with the second input of the XOR gate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510053179.1A CN104617926B (en) | 2015-02-02 | 2015-02-02 | A kind of swallow pulse formula clock synchronization circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510053179.1A CN104617926B (en) | 2015-02-02 | 2015-02-02 | A kind of swallow pulse formula clock synchronization circuit |
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| CN104617926B true CN104617926B (en) | 2018-04-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106374898B (en) * | 2016-10-18 | 2019-08-20 | 天津大学 | Multichannel exports gating switch timing and generates structure |
| CN109194334B (en) * | 2018-11-12 | 2024-01-23 | 苏州云芯微电子科技有限公司 | Synchronous system applied to multichannel high-speed digital-to-analog converter |
| CN111262562B (en) * | 2020-03-02 | 2021-08-27 | 上海交通大学 | Metastable state detection circuit |
| CN112416848B (en) * | 2020-11-18 | 2023-10-20 | 海光信息技术股份有限公司 | Source chip, destination chip, data transmission method and processor system |
| CN112213733B (en) * | 2020-12-03 | 2021-02-26 | 深圳市海创光学有限公司 | Synchronous voltage-controlled adjustable pulse generating circuit and fiber laser |
| CN114420030B (en) * | 2022-01-27 | 2022-11-04 | 成都利普芯微电子有限公司 | PWM generating circuit, driving chip, and electronic apparatus |
| CN114420043B (en) * | 2022-01-27 | 2022-11-18 | 成都利普芯微电子有限公司 | Drive circuit, drive chip and display device |
| CN114614823B (en) * | 2022-02-25 | 2023-06-06 | 苏州迅芯微电子有限公司 | Chip clock synchronization method, data acquisition card and data acquisition system |
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| TW200820617A (en) * | 2006-10-23 | 2008-05-01 | Realtek Semiconductor Corp | Fraction-N frequency divider and method thereof |
| CN102339014A (en) * | 2010-05-13 | 2012-02-01 | 玛克西姆综合产品公司 | Synchronization of a generated clock |
| CN103248532A (en) * | 2012-02-02 | 2013-08-14 | 安立股份有限公司 | Jitter measuring trigger generator, jitter measuring apparatus using the same, method of generating jitter measuring trigger, and method of measuring jitter |
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| US7940100B2 (en) * | 2007-09-24 | 2011-05-10 | Qualcomm, Incorporated | Delay circuits matching delays of synchronous circuits |
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|---|---|---|---|---|
| US7301379B1 (en) * | 2005-07-29 | 2007-11-27 | Conexant Systems, Inc. | Systems and method for a delay locked loop with false-lock detection |
| TW200820617A (en) * | 2006-10-23 | 2008-05-01 | Realtek Semiconductor Corp | Fraction-N frequency divider and method thereof |
| CN102339014A (en) * | 2010-05-13 | 2012-02-01 | 玛克西姆综合产品公司 | Synchronization of a generated clock |
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