CN104617926A - Pulse swallowing type clock synchronization circuit - Google Patents
Pulse swallowing type clock synchronization circuit Download PDFInfo
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- CN104617926A CN104617926A CN201510053179.1A CN201510053179A CN104617926A CN 104617926 A CN104617926 A CN 104617926A CN 201510053179 A CN201510053179 A CN 201510053179A CN 104617926 A CN104617926 A CN 104617926A
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- 230000009747 swallowing Effects 0.000 title abstract 5
- 230000001360 synchronised effect Effects 0.000 claims description 18
- 238000007688 edging Methods 0.000 claims description 11
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000003111 delayed effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000012952 Resampling Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000013138 pruning Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Abstract
The invention discloses a pulse swallowing type clock synchronization circuit. The pulse swallowing type clock synchronization circuit comprises an edge trigger selection circuit and a stepping type variable delay circuit, wherein an input end of the edge trigger selection circuit is connected with a synchronization pulse input signal generated by a master chip, an input end of the stepping type variable delay circuit is connected with a synchronization pulse output signal generated by the master chip, an output end of the edge trigger selection circuit and an output end of the stepping type variable delay circuit are connected with an input end of an exclusive or gate so as to perform exclusive or operation, output of the exclusive or gate is detected through a pulse swallowing circuit, and then one path of the output is output through a synchronization clock, and the other path of the output is fed back to the stepping type variable delay circuit through a synchronization pulse generating circuit. The pulse swallowing type clock synchronization circuit does not need a high speed reset signal generation circuit, simplifies design of a circuit board, reduces complexity of a system, reduces cost of the system, and reduces debugging difficultly of the circuit board.
Description
Technical field
The present invention relates to one and gulp down pulsed clock synchronization circuit.
Background technology
At present, high--speed multi--channel data acquisition system is usually containing multiple data transaction chip, in the great majority application of this type systematic, the data flow of each channel acquisition gained is needed to align accurately in time, make between the data of multichannel collecting system acquisition and the analog signal of input, there is delay that is identical or that determine, so that follow-up Data Management Analysis, this just requires that the output signal of the multiple data transaction chips being distributed in different physical location overturn in the moment that is identical or that determine, and this requires the clock signal stringent synchronization of multiple data transaction chip internal.
In order to realize multi-chip clock synchronous, traditional solution has two kinds: synchronous reset mode and gulp down pulse mode.Synchronous reset mode is the lock-out pulse by sending a high speed to each chip simultaneously, resets while realizing each chip.Overlap with clock edges in order to avoid reset signal and the nondeterministic statement that causes, should ensure that the clock signal of reset signal and chip meets suitable delay relation, meanwhile, the rise/fall of reset signal is along also sufficiently precipitous.In order to meet these requirements, usually need extra high-speed synchronous pulses generation chip and manual debugging process repeatedly.Although therefore synchronous reset mode is comparatively simple in principle, the realization of its hardware is also not easy, and the requirement that paired pulses produces circuit and board design is higher, and particularly after clock frequency reaches more than GHz, the process of debugging is more difficult.
Gulp down pulse mode often subsynchronous two adjacent chips, provide the chip of synchronization pulse (reference signal) to be called master chip, be called from chip by synchronizing chip.Its general principle master chip is produced synchronization pulse to compare with the synchronization pulse that the inside from chip produces, if detect that both there are differences, just by a pulse signal of pruning from the high-frequency clock in chip, time domain waveform shows as a pulse and " is gulped down ".The clock of the lowest speed usually produced by frequency division by chip internal is as lock-out pulse.Through repeatedly gulping down the process of pulse, the clock signal of final chip internal reaches synchronous with the clock in adjacent chips.Complete synchronous chip and repeat to gulp down the process of pulse with adjacent chip again, until all chips all reach synchronous in system.Traditional impulsive synchronization mode that gulps down requires that the synchronization pulse of master chip has identical delay path with the synchronization pulse from chip, and chip needs to increase extra port to receive the synchronization pulse produced with other chips oneself produced for this reason.The self-loop of synchronization pulse needs strictly equal with the path delay of master chip synchronization pulse, and require higher to board design, after particularly clock frequency reaches more than GHz, the nuance of circuit board trace all may cause synchronization failure.
Summary of the invention
The defect that the present invention seeks to exist for prior art provides one to gulp down pulsed clock synchronization circuit, this circuit eliminates the self-loop of conventional synchronization pulse signal, stepping variable delay circuit is increased at chip internal, suitable delay is selected by internal register configuration, the program decreases the synchronous required port number of high-speed chip, simplify board design simultaneously, reduce the requirement of board design, improve the convenience that chip uses.
The present invention for achieving the above object, adopts following technical scheme: one gulps down pulsed clock synchronization circuit, comprises edging trigger selection circuit, and the lock-out pulse input signal that its input and master chip produce is connected; Stepping variable delay circuit, its input outputs signal with the lock-out pulse produced from chip and is connected; The output of described edging trigger selection circuit and the output of stepping variable delay circuit are connected to the input of XOR gate, to carry out xor operation; The output of described XOR gate is by after gulping down impulse circuit and detecting, and synchronised clock output is carried out on a road, and synchronous pulse-generating circuit of separately leading up to feeds back to described stepping variable delay circuit.
Further, described edging trigger selection circuit comprises the latch Latch and trigger DFF that connect successively; The signal input part D of described latch Latch is connected with lock-out pulse input signal, and its signal output part Q is connected with the signal input part D of described trigger DFF; The Enable Pin CLK of described latch Latch with or the output of door be connected; First input end that is described or door is connected with clock input signal, and the second input and triggering edge select signal to be connected; The signal output part Q of described trigger DFF is connected with the first input end of XOR gate; The Enable Pin CLK of described trigger DFF is connected with clock input signal.
Further, described stepping variable delay circuit comprises multiple trigger DFF connected successively, and the signal input part D being wherein arranged on the first described trigger DFF outputs signal with described lock-out pulse and is connected; The Enable Pin CLK of each described trigger DFF is all connected with clock input signal, the signal output part Q of each described trigger DFF is corresponding with the input of MUX respectively to be connected, and the output of described MUX is connected with the second input of described XOR gate.
Beneficial effect of the present invention: circuit of the present invention does not need high speed reset signal to produce chip, simplifies the design of circuit board, reduces the complexity of system, be conducive to the cost of reduction system, also reduce the difficulty of debugging circuit board.
Contrast tradition gulps down pulsed clock synchronization circuit, eliminate the self-loop of the conventional synchronization pulse signal being in chip exterior, stepping variable delay circuit is increased at chip internal, suitable delay is selected by internal register configuration, the program decreases the synchronous required port number of high-speed chip, simplify board design simultaneously, reduce the requirement of board design, improve the convenience that chip uses.
Accompanying drawing explanation
Fig. 1 is traditional multichip synchronization system connection diagram.
Fig. 2 is multichip synchronization system connection diagram of the present invention.
Fig. 3 is chip internal synchronous circuit theory diagram of the present invention.
Fig. 4 is the time diagram of synchronizing process of the present invention.
Fig. 5 is the corresponding relation schematic diagram that lock-out pulse of the present invention postpones to select with delay selection signal and triggering edge.
Embodiment
The multi-chip connected mode gulping down pulsed clock synchronization circuit of the improvement that this programme proposes as shown in Figure 2, number due to clock terminal mouth has been reduced to one, the tradition of comparison diagram 1 gulps down impulsive synchronization mode, and the port number of chip and the number of interconnection line all greatly reduce.The improvement that this programme proposes gulp down pulsed clock synchronization circuit, its essence eliminates the self-loop link that tradition gulps down synchronization pulse in pulsed clock synchronization circuit, increases stepping variable delay circuit complete similar functions at chip internal.
Shown in Fig. 3, relate to one of the present invention and gulp down pulsed clock synchronization circuit, comprise edging trigger selection circuit, the lock-out pulse input signal that its input and master chip produce is connected; Stepping variable delay circuit, its input outputs signal with the lock-out pulse produced from chip and is connected; The output of described edging trigger selection circuit and the output of stepping variable delay circuit are connected to the input of XOR gate, to carry out xor operation; The output of described XOR gate is by after gulping down impulse circuit and detecting, and synchronised clock output is carried out on a road, and synchronous pulse-generating circuit of separately leading up to feeds back to described stepping variable delay circuit.
Wherein, described edging trigger selection circuit comprises the latch Latch and trigger DFF that connect successively; The signal input part D of described latch Latch is connected with lock-out pulse input signal, and its signal output part Q is connected with the signal input part D of described trigger DFF; The Enable Pin CLK of described latch Latch with or the output of door be connected; First input end that is described or door is connected with clock input signal, and the second input and triggering edge select signal to be connected; The signal output part Q of described trigger DFF is connected with the first input end of XOR gate; The Enable Pin CLK of described trigger DFF is connected with clock input signal.
Wherein, described stepping variable delay circuit comprises multiple trigger DFF connected successively, and the signal input part D being wherein arranged on the first described trigger DFF outputs signal with described lock-out pulse and is connected; The Enable Pin CLK of each described trigger DFF is all connected with clock input signal, the signal output part Q of each described trigger DFF is corresponding with the input of MUX respectively to be connected, and the output of described MUX is connected with the second input of described XOR gate.
Operation principle is: the lock-out pulse input signal of master chip, first snaps to the rising edge of internal clocking by edging trigger selection circuit.And outputed signal by the lock-out pulse produced from chip oneself, then after being postponed by the adjustment of stepping variable delay circuit, carry out xor operation with the lock-out pulse input signal through resampling.Gulp down the Output rusults that impulse circuit can detect XOR gate, when rising edge appears in the result of XOR, then gulp down a clock signal pulse.Through repetitious gulp down pulse operation after, the lock-out pulse input signal after final resampling outputs signal with the lock-out pulse after variable delay circuit and reaches consistent.The time diagram of synchronizing process as shown in Figure 4.
Below the selection of triggering edge and the delayed selection culture of stepping variable delay circuit are described.Select suitable triggering edge, be in order to avoid lock-out pulse input signal conflicts with the edge of internal clocking, cause d type flip flop sampled result uncertain.Therefore need the alignment relation according to the edge of lock-out pulse input signal and the edge of internal clock signal, select suitable triggering edge, the d type flip flop ensureing in edging trigger selection circuit has enough sets up the retention time.The delayed selection culture of stepping variable delay circuit, is to increase the delay outputed signal from the lock-out pulse of chip, the Late phase of the lock-out pulse input signal of this delay and master chip is offset.Due to the difference of triggering edge, the delay of master chip lock-out pulse input signal also can be caused different, and therefore the delayed selection culture needs to coordinate with the selection of triggering edge, and the object postponing to offset is reached in both actings in conjunction.Fig. 5 gives the schematic diagram of an appropriate value, and lock-out pulse wherein postpones to refer to synchronization pulse arrival that master chip the produces predicted delay time from chip.Such as, when lock-out pulse postpones for 1.5T (T is clock frequency), should arrange the delayed selection culture is 2, and triggering edge is chosen as 1.Lock-out pulse postpones can by emulating or testing acquisition.
The chip chamber that the present invention is specially adapted to many ADC, DAC systems of more than 1GHz or other high-speed digital systems is synchronous.
1, chip internal is moved in the synchronization pulse path from chip, decrease the port of chip and the number of interconnection line.
2, triggering edge selection and stepping variable delay device cooperatively interact, and ensure that internal latency can be offset with the synchronization pulse Late phase of master chip, realize synchronizing process.
3, the length of delay of triggering edge selection and stepping variable delay device is all by software merit rating, can cover various different lock-out pulse length of delay.
In addition, multi-chip clock synchronization circuit proposed by the invention had both gone for multichannel ADC, DAC system, also went for the multichip system that other have clock synchronisation requirement.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. gulp down a pulsed clock synchronization circuit, it is characterized in that, comprise edging trigger selection circuit, the lock-out pulse input signal that its input and master chip produce is connected; Stepping variable delay circuit, its input outputs signal with the lock-out pulse produced from chip and is connected; The output of described edging trigger selection circuit and the output of stepping variable delay circuit are connected to the input of XOR gate, to carry out xor operation; The output of described XOR gate is after gulping down impulse circuit and detecting, and synchronised clock output is carried out on a road, and synchronous pulse-generating circuit of separately leading up to feeds back to described stepping variable delay circuit.
2. gulp down pulsed clock synchronization circuit as claimed in claim 1, it is characterized in that, described edging trigger selection circuit comprises the latch Latch and trigger DFF that connect successively; The signal input part D of described latch Latch is connected with lock-out pulse input signal, and its signal output part Q is connected with the signal input part D of described trigger DFF; The Enable Pin CLK of described latch Latch with or the output of door be connected; First input end that is described or door is connected with clock input signal, and the second input and triggering edge select signal to be connected; The signal output part Q of described trigger DFF is connected with the first input end of XOR gate; The Enable Pin CLK of described trigger DFF is connected with clock input signal.
3. gulp down pulsed clock synchronization circuit as claimed in claim 2, it is characterized in that, described stepping variable delay circuit comprises multiple trigger DFF connected successively, and the signal input part D being wherein arranged on the described trigger DFF of input side outputs signal with described lock-out pulse and is connected; The Enable Pin CLK of each described trigger DFF is all connected with clock input signal, the signal output part Q of each described trigger DFF is corresponding with the input of MUX respectively to be connected, and the output of described MUX is connected with the second input of described XOR gate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510053179.1A CN104617926B (en) | 2015-02-02 | 2015-02-02 | A kind of swallow pulse formula clock synchronization circuit |
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| CN201510053179.1A CN104617926B (en) | 2015-02-02 | 2015-02-02 | A kind of swallow pulse formula clock synchronization circuit |
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| CN104617926A true CN104617926A (en) | 2015-05-13 |
| CN104617926B CN104617926B (en) | 2018-04-10 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374898A (en) * | 2016-10-18 | 2017-02-01 | 天津大学 | Time sequence generating structure of multi-channel output gating switch |
| CN109194334A (en) * | 2018-11-12 | 2019-01-11 | 苏州云芯微电子科技有限公司 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
| CN111262562A (en) * | 2020-03-02 | 2020-06-09 | 上海交通大学 | Metastable state detection circuit |
| CN112213733A (en) * | 2020-12-03 | 2021-01-12 | 深圳市海创光学有限公司 | Synchronous voltage-controlled adjustable pulse generating circuit and fiber laser |
| CN112416848A (en) * | 2020-11-18 | 2021-02-26 | 海光信息技术股份有限公司 | Source chip, destination chip, data transmission method and processor system |
| CN114420030A (en) * | 2022-01-27 | 2022-04-29 | 成都利普芯微电子有限公司 | PWM generating circuit, driving chip, and electronic apparatus |
| CN114420043A (en) * | 2022-01-27 | 2022-04-29 | 成都利普芯微电子有限公司 | Drive circuit, drive chip and display device |
| CN114614823A (en) * | 2022-02-25 | 2022-06-10 | 苏州迅芯微电子有限公司 | Chip clock synchronization method, data acquisition card and data acquisition system |
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| US7301379B1 (en) * | 2005-07-29 | 2007-11-27 | Conexant Systems, Inc. | Systems and method for a delay locked loop with false-lock detection |
| TW200820617A (en) * | 2006-10-23 | 2008-05-01 | Realtek Semiconductor Corp | Fraction-N frequency divider and method thereof |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374898A (en) * | 2016-10-18 | 2017-02-01 | 天津大学 | Time sequence generating structure of multi-channel output gating switch |
| CN106374898B (en) * | 2016-10-18 | 2019-08-20 | 天津大学 | Multichannel exports gating switch timing and generates structure |
| CN109194334A (en) * | 2018-11-12 | 2019-01-11 | 苏州云芯微电子科技有限公司 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
| CN109194334B (en) * | 2018-11-12 | 2024-01-23 | 苏州云芯微电子科技有限公司 | Synchronous system applied to multichannel high-speed digital-to-analog converter |
| CN111262562A (en) * | 2020-03-02 | 2020-06-09 | 上海交通大学 | Metastable state detection circuit |
| CN112416848A (en) * | 2020-11-18 | 2021-02-26 | 海光信息技术股份有限公司 | Source chip, destination chip, data transmission method and processor system |
| CN112416848B (en) * | 2020-11-18 | 2023-10-20 | 海光信息技术股份有限公司 | Source chip, destination chip, data transmission method and processor system |
| CN112213733A (en) * | 2020-12-03 | 2021-01-12 | 深圳市海创光学有限公司 | Synchronous voltage-controlled adjustable pulse generating circuit and fiber laser |
| CN114420030A (en) * | 2022-01-27 | 2022-04-29 | 成都利普芯微电子有限公司 | PWM generating circuit, driving chip, and electronic apparatus |
| CN114420043A (en) * | 2022-01-27 | 2022-04-29 | 成都利普芯微电子有限公司 | Drive circuit, drive chip and display device |
| CN114614823A (en) * | 2022-02-25 | 2022-06-10 | 苏州迅芯微电子有限公司 | Chip clock synchronization method, data acquisition card and data acquisition system |
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| CN104617926B (en) | 2018-04-10 |
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Address after: Room 708-1, Building 1, Northwest District, Suzhou Nanocity, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Free Trade Pilot Zone, Suzhou City, Jiangsu Province, 215124 Patentee after: Xunxin Microelectronics (Suzhou) Co.,Ltd. Address before: Unit A4-110 C, No. 218 Xinghu Street, Suzhou Industrial Park, Suzhou City, Jiangsu Province, 215000 Patentee before: ACELA MICRO CO.,LTD. |
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