CN112416848A

CN112416848A - Source chip, destination chip, data transmission method and processor system

Info

Publication number: CN112416848A
Application number: CN202011296358.5A
Authority: CN
Inventors: 梁岩; 王文根
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2021-02-26
Anticipated expiration: 2040-11-18
Also published as: CN112416848B

Abstract

The application provides a source chip, a destination chip, a data transmission method and a processor system, which comprise a data coding module and a driver, wherein the data coding module is connected with the driver; the data coding module is used for receiving the serial data, coding the serial data to obtain coded data and transmitting the coded data to the driver, wherein jump delay exists between any two adjacent data of the coded data; the driver is used for receiving the coded data and sending the coded data to the destination chip of the opposite end, so that the destination chip of the opposite end restores the coded data into serial data according to the coded data with jump delay between any two adjacent data. Through the coding of the serial data, the coded data carries a clock signal through the change of the jump delay, and compared with a chip self-adaptive clock which does not carry the clock signal and needs an opposite terminal in the prior art, the difficulty of clock recovery is reduced, and the delay of data transmission is reduced.

Description

Source chip, destination chip, data transmission method and processor system

Technical Field

The present application relates to the field of computers, and in particular, to a source chip, a destination chip, a data transmission method, and a processor system.

Background

In the prior art, when data is transmitted between two die chips (die), a source chip often transmits data and a clock signal corresponding to the data to a destination chip, and the destination chip can collect the received data according to the received clock signal. However, since data and a clock signal need to be transmitted simultaneously during transmission, the amount of data to be transmitted is large.

In another mode of the prior art, the source chip may only transmit data to the destination chip, and the destination chip may adjust the frequency of its clock signal through the feedback circuit, so that the frequency of the clock can adapt to the data transmitted by the source chip, and the destination chip collects the received data according to the adjusted frequency of the clock. However, the above method requires the feedback circuit to adjust its own clock, so that the clock recovery circuit is complex and the data transmission delay is large.

Disclosure of Invention

An embodiment of the present invention provides a source chip, a destination chip, a data transmission method, and a processor system, so as to solve the problem of a large delay in data transmission between chip dies in the prior art.

In a first aspect, an embodiment of the present application provides a source chip, including a data encoding module and a driver, where the data encoding module is connected to the driver; the data coding module is used for receiving serial data, coding the serial data to obtain coded data and transmitting the coded data to the driver, wherein any two adjacent data of the coded data have jump delay; the driver is used for receiving the coded data and sending the coded data to a destination chip of an opposite end, so that the destination chip of the opposite end restores the coded data into the serial data according to the coded data with transition delay between any two adjacent data.

In the foregoing embodiment, the data encoding module may encode the serial data to obtain encoded data, so as to implement that any two adjacent data of the encoded data have a transition delay therebetween. Because the jump delay exists between any two adjacent data, when the chip at the opposite end receives one data, the chip at the opposite end can know the change of the jump delay, namely the change of each jump delay corresponds to one received data, thereby equivalently realizing the transmission of clock signals by utilizing the coded data. Through the coding of the serial data, the coded data carries a clock signal through the change of the jump delay, and compared with a chip self-adaptive clock which does not carry the clock signal and needs an opposite terminal in the prior art, the difficulty of clock recovery is reduced, and the delay of data transmission is reduced.

In one possible design, the data encoding module is configured to receive serial data and encode the serial data to obtain encoded data, and specifically includes: receiving current data; judging whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; if yes, encoding the current data into an intermediate level; if not, encoding the current data into a level state consistent with the current data.

In the above embodiment, the level state of the current data may be compared with the level state of the previous data to determine whether the level states of the current data and the previous data are consistent, and if so, the level state of the current data may be represented by an intermediate level, and if not, the original level state of the current data may be retained. Through the introduction of the middle level, the level state of the latter data in the two adjacent data can be changed when the two adjacent data are at the same level, so that the condition that the same level does not occur in the two adjacent data is realized.

In one possible design, the data encoding module includes a first digital trigger, a second digital trigger, an exclusive nor operator, and a selector; the CLK end of the first digital trigger is connected with a clock signal line for transmitting a clock signal, the input end of the first digital trigger is connected with a serial data line for transmitting serial data, and the output end of the first digital trigger is connected with the first input end of the exclusive-nor operator; the second input end of the exclusive OR operator is connected with the serial data line, and the output end of the exclusive OR operator is connected with the first input end of the selector; the output end of the selector is connected with the input end of the second digital trigger; the output end of the second digital flip-flop is connected with the second input end of the selector, and the CLK end of the second digital flip-flop is connected with the clock signal line.

In the above embodiment, the first digital flip-flop may delay the serial data by one clock cycle, and the exclusive nor operation may be performed on the serial data and the serial data delayed by one clock cycle to obtain the operation result. The level state of the bit data can be determined according to the specific operation result and the level state of the previous bit data.

In a possible design, the data encoding module is configured to receive the serial data and encode the serial data to obtain encoded data, and specifically includes: performing bit-to-bit exclusive OR operation on the serial data and the serial data delayed by one clock cycle by the first digital trigger by using the exclusive OR operator to obtain an operation result; if the operation result is 0, determining the level of the bit of the serial data corresponding to the operation result in the corresponding bit of the coded data as an original level by using the selector; if the operation result is 1, judging whether the level state of the coded data corresponding to the previous bit of data of the serial data is an intermediate level according to the output result of the second digital trigger; if the level state of the coded data corresponding to the previous bit of data is an intermediate level, determining that the level of the bit of the serial data corresponding to the operation result at the corresponding bit of the coded data is an original level; and if the level state of the coded data corresponding to the previous bit of data is not the intermediate level, determining that the level of the bit of the serial data corresponding to the operation result in the corresponding bit of the coded data is the intermediate level.

In the above-described embodiment, if the operation result is 0, it indicates that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it indicates that the level state of the current bit data is the same as the actual level state of the previous bit data, and further determination is needed: whether the level state of the previous bit data is changed to the intermediate level. If the level state of the previous bit data is changed into the intermediate level, the level state of the current bit data does not need to be modified, and the original level can be directly output to be distinguished from the level state of the previous bit data; if the level state of the previous bit data is not changed to the intermediate level, the level state of the current bit data needs to be modified to the intermediate level to be distinguished from the level state of the previous bit data.

In a second aspect, the present application provides a destination chip, which, in cooperation with the source chip of the first aspect or any one of the possible designs of the first aspect, includes a first comparator, a second comparator, a clock recovery circuit, and a data recovery circuit; the first comparator is used for receiving encoded data sent by a source chip of an opposite terminal, comparing the encoded data with a first reference level, and making an output of the encoded data, which is higher than the first reference level, be a high level and an output of the encoded data, which is lower than the first reference level, be a low level to obtain a first waveform, wherein the first reference level is between a middle level and the high level; the second comparator is configured to receive the encoded data, compare the encoded data with a second reference level, and output higher than the second reference level in the encoded data is a high level and output lower than the second reference level is a low level to obtain a second waveform, where the second reference level is between the middle level and the low level; the clock recovery circuit is used for acquiring a pulse with a first waveform and a pulse with a second waveform, and performing merging processing on the acquired pulses to acquire a clock recovery signal; the data recovery circuit is used for collecting the coded data according to the clock recovery signal and recovering the coded data into serial data.

In the above embodiment, the first comparator may restore the middle level to the low level through its own reference level to obtain a first waveform; the second comparator can restore the middle level to a high level through the reference level of the second comparator, and a second waveform is obtained. Then the clock recovery circuit can respectively obtain the pulse corresponding to the first waveform turning position and the pulse corresponding to the second waveform turning position, and then the two pulses are processed in parallel, so that a clock recovery signal can be obtained. The data recovery circuit can collect the coded data according to the clock recovery signal and recover the coded data into serial data. Through the cooperation of the first comparator, the second comparator and the clock recovery circuit, the clock signal can be recovered from the coded data.

In one possible design, the clock recovery circuit includes at least one first delay, a first exclusive or operator, at least one second delay, a second exclusive or operator, and an or operator; the at least one first delayer is used for delaying the first waveform; the first exclusive-or operator is used for carrying out exclusive-or operation on the first waveform and the first waveform delayed by the at least one first delayer to obtain a first pulse waveform; the at least one second delayer is used for delaying the second waveform; the second exclusive-or operator is configured to perform exclusive-or operation on the second waveform and the second waveform delayed by the at least one second delay unit to obtain a second pulse waveform; the OR arithmetic unit is used for carrying out OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, and the pulse fusion waveform is the clock recovery signal.

In the above embodiments, the clock recovery circuit includes a first delay, a first xor operator, a second delay, a second xor operator, and an or operator. The first delay is configured to delay the first waveform, and the first xor operator is configured to perform xor processing on the delayed first waveform and the first waveform to obtain a waveform composed of a pulse signal of the first waveform at the flip position, where the waveform may be referred to as a first pulse waveform. The second exclusive-or operator performs exclusive-or processing on the delayed second waveform and the second waveform to obtain a waveform composed of the pulse signal of the second waveform at the inversion position, and the waveform is referred to as a second pulse waveform. And taking the sum of the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, wherein the time interval between two adjacent pulses of the pulse fusion waveform is the same as the time interval between two adjacent data in the coded data, so that the pulse fusion waveform is a clock recovery signal.

In one possible design, the clock recovery circuit further includes a divide-by-two divider, and a CLK terminal of the divide-by-two divider is connected to an output terminal of the or operator; the frequency halving device is used for performing frequency halving processing on the clock recovery signal to obtain a clock recovery signal with a duty ratio of 50%.

In the above embodiment, after obtaining the clock recovery signal, the clock recovery signal may be subjected to a frequency division by a frequency divider to obtain a clock recovery signal with a duty ratio of 50%. The clock recovery signal after the frequency division by two is more stable.

In one possible design, the data recovery circuit is configured to collect the encoded data according to the clock recovery signal and recover the encoded data into serial data, and specifically includes: determining that the received current data is in an intermediate level state; and acquiring the level state of the previous data of the current data, and taking the level state of the previous data as the level state of the current data.

In the above embodiment, when the data recovery circuit recovers the encoded data into serial data, the data recovery circuit may collect the encoded data according to the frequency of the clock recovery signal, and determine whether the received current data is in the intermediate level state according to the comparison result of the first comparator and the second comparator, if not, the high level is recovered to 1 corresponding to the high level, and the low level is recovered to 0 corresponding to the low level. And if the current data is in the intermediate level state, acquiring the level state of the previous data, and determining the numerical value corresponding to the current data according to the level state of the previous data, wherein the recovery process is simple and has small operand.

In a third aspect, the present application provides a data transmission method, which is applied to a source chip, and the method includes: the data coding module of the source chip receives serial data, codes the serial data to obtain coded data, and transmits the coded data to a driver of the source chip, wherein jump delay exists between any two adjacent data of the coded data; and the driver receives the coded data and sends the coded data to a destination chip of an opposite end so that the destination chip of the opposite end processes the coded data.

In one possible design, the data encoding module receives serial data and encodes the serial data to obtain encoded data, including: receiving current data; judging whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; if yes, encoding the current data into an intermediate level; if not, the level state corresponding to the current data is reserved.

In one possible design, the data encoding module includes a first digital trigger, a second digital trigger, an exclusive nor operator, and a selector; the CLK end of the first digital trigger receives a clock signal, the input end of the first digital trigger is used for receiving the serial data, and the output end of the first digital trigger is connected with the first input end of the exclusive-nor operator; the second input end of the exclusive OR operator is used for receiving the serial data, and the output end of the exclusive OR operator is connected with the first input end of the selector; the output end of the selector is connected with the input end of the second digital trigger; the output end of the second digital flip-flop is connected with the second input end of the selector, and the CLK end of the second digital flip-flop is used for receiving the clock signal; the data coding module receives the serial data, codes the serial data to obtain coded data, and comprises: carrying out bit-to-bit exclusive-or operation on the serial data and the serial data delayed by one clock cycle to obtain an operation result; if the operation result is 0, determining the level of the data of the corresponding bit of the serial data to be an original level; if the operation result is 1, judging whether the level state of the previous bit data is an intermediate level; if the level state of the previous bit data is the intermediate level, determining the level of the data of the corresponding bit of the serial data as the original level; and if the level state of the previous bit data is not the intermediate level, determining that the level of the data of the corresponding bit of the serial data is the intermediate level.

In the above embodiment, the first digital flip-flop may delay the serial data by one clock cycle, and the exclusive nor operation may be performed on the serial data and the serial data delayed by one clock cycle to obtain the operation result. The level state of the bit data can be determined according to the specific operation result and the level state of the previous bit data. If the operation result is 0, it indicates that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it indicates that the level state of the current bit data is the same as the actual level state of the previous bit data, and further determination is needed: whether the level state of the previous bit data is changed to the intermediate level. If the level state of the previous bit data is changed into the intermediate level, the level state of the current bit data does not need to be modified, and the original level can be directly output to be distinguished from the level state of the previous bit data; if the level state of the previous bit data is not changed to the intermediate level, the level state of the current bit data needs to be modified to the intermediate level to be distinguished from the level state of the previous bit data.

In a fourth aspect, the present application provides a data transmission method, which is applied to a destination chip, and the method includes: a first comparator of the destination chip receives encoded data sent by a source chip of an opposite terminal, compares the encoded data with a first reference level, outputs higher than the first reference level in the encoded data are high levels, outputs lower than the first reference level are low levels, a first waveform is obtained, and the first waveform is transmitted to a clock recovery circuit of the destination chip, wherein the first reference level is between a middle level and the high levels; a second comparator of the destination chip receives the encoded data, compares the encoded data with a second reference level, outputs higher than the second reference level in the encoded data are high levels, outputs lower than the second reference level are low levels, a second waveform is obtained, and the second waveform is transmitted to a clock recovery circuit of the destination chip, wherein the second reference level is between the middle level and the low level; the clock recovery circuit acquires the pulse with the inverted waveform of the first waveform and the pulse with the inverted waveform of the second waveform, performs parallel processing on the acquired pulses to acquire a clock recovery signal, and transmits the clock recovery signal to the data recovery circuit of the target chip; and the data recovery circuit collects the coded data according to the clock recovery signal and recovers the coded data into serial data.

In one possible design, the clock recovery circuit includes at least one first delay, a first exclusive or operator, at least one second delay, a second exclusive or operator, and an or operator; the clock recovery circuit acquires a pulse with a waveform inversion of a first waveform and a pulse with a waveform inversion of a second waveform, and performs merging processing on the acquired pulses to acquire a clock recovery signal, and the clock recovery circuit includes: the at least one first delay delays the first waveform; the first exclusive-or operator performs exclusive-or operation on the first waveform and the delayed first waveform to obtain a first pulse waveform, wherein the first pulse waveform is a waveform where a pulse signal corresponding to waveform inversion of the first waveform is located; the at least one second delay delays the second waveform; the second exclusive-or operator performs exclusive-or operation on the second waveform and the delayed second waveform to obtain a second pulse waveform, wherein the second pulse waveform is a waveform where a pulse signal corresponding to waveform inversion of the second waveform is located; and the OR arithmetic unit performs OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, wherein the pulse fusion waveform is the clock recovery signal.

In one possible design, the clock recovery circuit further includes a divide-by-two divider, and a CLK terminal of the divide-by-two divider is connected to an output terminal of the or operator; after the or operator performs or processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, the method further includes: and the frequency halving device performs frequency halving processing on the clock recovery signal to obtain a clock recovery signal with the duty ratio of 50%.

In one possible design, the data recovery circuit collects the encoded data according to the clock recovery signal and recovers the encoded data into serial data, including: determining that the received current data is in an intermediate level state; and acquiring the level state of the previous data of the current data, and taking the level state of the previous data as the level state of the current data.

In a fifth aspect, the present application provides a processor system comprising a chip of the first aspect or any one of the possible designs of the first aspect, and a chip of the second aspect or any one of the possible designs of the second aspect.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 illustrates a prior art application scenario for data transmission between chip dies;

FIG. 2 is a block diagram of a processor system according to an embodiment of the present disclosure;

FIG. 3 shows a schematic structural diagram of a data encoding module;

FIG. 4 shows a corresponding waveform diagram during operation of the data encoding module;

FIG. 5a shows a schematic diagram of the structure of the driver outputting a high state;

FIG. 5b shows a schematic diagram of the structure of the driver output intermediate level state;

FIG. 5c shows a schematic diagram of the structure of the driver outputting a low state;

FIG. 6 illustrates a waveform diagram of one embodiment of encoding serial data into encoded data;

FIG. 7 illustrates waveforms generated by the clock recovery circuit during operation;

FIG. 8 shows a schematic of a clock recovery circuit;

fig. 9 is a schematic flowchart illustrating a data transmission method according to an embodiment of the present application;

fig. 10 is a schematic flow chart illustrating a data transmission method according to another embodiment of the present application;

fig. 11 shows a flowchart illustrating a specific step of step S230 in fig. 10.

Detailed Description

Referring to fig. 1, fig. 1 shows a manner of data transmission between chip dies in a comparative example, and the data transmission of a source chip 100 to a destination chip 200 is explained below. In the embodiments of the present application, the chips mentioned herein are die without specific description.

The transmitted data may be Non Return to Zero (NRZ) codes or Pulse Amplitude Modulation (PAM) codes. NRZ transmits

data

0 and 1 through low and high levels, respectively, and PAM codes transmit a plurality of data through encoding using a plurality of levels.

In the source chip 100, the parallel-to-serial conversion module 101 converts four parallel data into one serial data, and sends out the serial data through the driver 102.

In the destination chip 200, data is collected by the first receiver 201 and the second receiver 202 at different clock transitions, respectively. For example, it is not assumed that the first receiver 201 collects data on the rising edge of the clock and the second receiver 202 collects data on the falling edge of the clock. The clock may be a preset clock.

The first receiver 201 and the second receiver 202 perform data acquisition according to a preset clock, transmit the acquired data to the serial-to-parallel conversion module 203 for serial-to-parallel conversion, the serial-to-parallel conversion module 203 converts the two acquired data paths into four parallel data paths again, and transmit the four parallel data paths to the logic module 204.

The logic block 204 may determine whether the data is clocked early or late based on the four received paths of parallel data. If the data leads the clock, the logic block 204 may adjust a Phase Interpolator (PI) block 205 to advance the clock; if the data is behind the clock, the logic block 204 may adjust the PI block 205 to delay the clock.

The PI module 205 may obtain a clock signal from a Phase Locked Loop (PLL) 206, and adjust the clock signal according to an instruction of the logic module 204.

In the above manner of data transmission, the logic module 204 is required to adjust the clock according to the phase relationship between the clock and the data, which results in a large data transmission delay.

In order to solve the problem, the coded data is obtained by coding the serial data, so that any two adjacent data of the coded data have jump delay, and the coded data carry a clock signal through the change of the jump delay, so that the difficulty of clock recovery is reduced.

Referring to fig. 2, fig. 2 shows a processor system provided by an embodiment of the present application, which includes a source chip 100 and a destination chip 200, where the source chip 100 and the destination chip 200 communicate with each other.

The source chip 100 includes a parallel-serial conversion module 101, a data encoding module 110, and a driver 102, and the parallel-serial conversion module 101, the data encoding module 110, and the driver 102 are sequentially connected.

The parallel-serial conversion module 101 is configured to convert four paths of parallel data into one path of serial data, and transmit the serial data to the data encoding module 110.

The data encoding module 110 is configured to receive serial data, encode the serial data to obtain encoded data, and transmit the encoded data to the driver 102, where any two adjacent data of the encoded data have a transition delay therebetween.

Optionally, the data encoding module 110 is specifically configured to: receiving current data; judging whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; if yes, encoding the current data into an intermediate level; if not, the level state corresponding to the current data is reserved.

Referring to fig. 6, fig. 6 shows an embodiment of encoding serial data into encoded data, for which: 010011000111, the parallel-serial conversion module 101 may perform data transmission according to the clock signal CLK: one data can be transmitted to the data encoding module 110 every time the transition of the CLK is delayed, that is, one data can be transmitted to the data encoding module 110 at both the rising edge and the falling edge of the CLK.

The data encoding module 110 may convert data 0 into a low level state L, convert data 1 into a high level state H, and determine the level state of the current data as an intermediate level state M when the level state of the current data coincides with the level state of the previous data.

The process of converting three consecutive identical data in serial data into encoded data can be performed as follows:

three consecutive 0 s in the serial data 010011000111 are not taken as an example. If the first 0 is different from the previous level state of data 1, the level state corresponding to the first 0 is L.

The second 0 originally corresponds to the level state L, but since the second 0 originally corresponds to the level state which is the same as the level state corresponding to the first 0, and is L, the level state corresponding to the second 0 can be determined as the intermediate level state M.

The level state originally corresponding to the third 0 is L, and since the level state corresponding to the second 0 is determined as the intermediate level state M and does not coincide with the level state originally corresponding to the third 0, the level state originally corresponding to the third 0 can be output.

In summary, the encoded data corresponding to the serial data 000 is LML.

Through the above processing method, serial data can be obtained: 010011000111 corresponding coded data: LHL MHM LML HMH, it is obvious that there is a transition delay between two adjacent data of the encoded data.

Alternatively, in an embodiment, the data encoding module 110 may also convert data 0 into a high level state H, convert data 1 into a low level state L, and determine the level state of the current data as an intermediate level state M when the level state of the current data is consistent with the level state of the previous data. The correspondence of data values to level states should not be construed as a limitation of the present application.

Referring to fig. 3, in one embodiment, the data encoding module 110 includes a first digital trigger 111, a second digital trigger 112, an exclusive nor operator 113, and a selector 114.

The CLK terminal of the first digital flip-flop 111 is configured to receive a clock signal, the input terminal of the first digital flip-flop 111 is configured to receive serial data, and the output terminal of the first digital flip-flop 111 is connected to the first input terminal of the exclusive nor operator 113.

A second input terminal of the exclusive nor operator 113 is configured to receive serial data, and an output terminal of the exclusive nor operator 113 is connected to the first input terminal of the selector 114.

The output of the selector 114 is connected to the input of the second digital flip-flop 112; the output of the second digital flip-flop 112 is coupled to a second input of the selector 114, and the CLK terminal of the second digital flip-flop 112 is configured to receive the clock signal.

The first digital flip-flop 111 is configured to delay the serial data TxDat by one clock cycle, and the exclusive nor operator 113 is configured to perform exclusive nor operation on the serial data TxDat and the serial data TxDat _ d delayed by one clock cycle, so as to obtain an operation result.

The selector 114 is configured to determine the selection result txwaak output by the current clock cycle selector 114 according to the operation result and the selection result txwaak _ d output by the previous clock cycle selector 114.

Alternatively, referring to fig. 4, when TxDat is the same as or the processing result TxDat _ d is 0, it is determined that the selection result txwaak output by the current clock cycle selector 114 is 0.

When the processing result of TxDat and TxDat _ d is 1 and the selection result txwaak _ d output by the previous clock cycle selector 114 is 0, it is determined that the selection result txwaak output by the current clock cycle selector 114 is 1.

When the processing result of TxDat and TxDat _ d is 1 and the selection result txwaak _ d output by the previous clock cycle selector 114 is 1, it is determined that the selection result txwaak output by the current clock cycle selector 114 is 0.

Wherein txwak is 1, and the driver 102 outputs an intermediate level; txwak is 0 and the driver 102 outputs the level signal corresponding to the serial data.

If the operation result is 0, it indicates that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it indicates that the level state of the current bit data is the same as the actual level state of the previous bit data, and further determination is needed: whether the level state of the previous bit data is changed to the intermediate level.

If the level state of the previous bit of data is changed to the intermediate level, that is, the selection result txwak _ d output by the previous clock cycle selector 114 corresponding to the level state of the previous bit of data is 1, the level state of the current bit of data does not need to be modified, and the original level can be directly output (that is, the selection result txwak output by the current clock cycle selector 114 is 0) to be distinguished from the level state of the previous bit of data; if the level state of the previous bit of data is not changed to the intermediate level, that is, the selection result txwaak _ d output by the previous clock cycle selector 114 corresponding to the level state of the previous bit of data is 0, the level state of the current bit of data needs to be modified to the intermediate level (that is, the selection result txwaak output by the current clock cycle selector 114 is 1) to be distinguished from the level state of the previous bit of data.

The driver 102 is configured to receive the encoded data and send the encoded data to the chip at the opposite end, so that the chip at the opposite end processes the encoded data.

Referring to fig. 5a to 5c, fig. 5a, 5b, and 5c together show a circuit diagram of an embodiment of the driver 102, the driver 102 includes a first resistor R1, a second resistor R2, a first switch k1, and a second switch k2, wherein the power source is grounded via the first resistor R1, the first switch k1, the second switch k2, and the second resistor R2 in sequence. One end of the transmission line is connected between the first switch k1 and the second switch k2, and the other end of the transmission line is connected with the ground resistor R3 of the opposite chip.

If the first switch k1 is closed and the second switch k2 is open, the transmission line transmits high level VDD/2, see fig. 5a for details; if the first switch k1 and the second switch k2 are both closed, the transmission line transmits an intermediate level VDD/4, see fig. 5b for details; if the first switch k1 is open and the second switch k2 is closed, the transmission line transmits a low level 0, as shown in fig. 5 c. Wherein the high level VDD/2 may correspond to data 1, and the low level 0 may correspond to data 0.

The source chip 100 may control a level state of the output of the driver 102 by controlling the closing or turning off of the first switch k1 or the second switch k 2.

For the source chip 100 provided in this embodiment of the application, the data encoding module 110 may encode serial data to obtain encoded data, so as to implement that any two adjacent data of the encoded data have a transition delay. Because the jump delay exists between any two adjacent data, when the chip at the opposite end receives one data, the chip at the opposite end can know the change of the jump delay, namely the change of each jump delay corresponds to one received data, which is equivalent to the transmission of a clock signal by utilizing the coded data. Through the coding of the serial data, the coded data carries a clock signal through the change of the jump delay, and compared with a chip self-adaptive clock which does not carry the clock signal and needs an opposite terminal in the prior art, the difficulty of clock recovery is reduced, and the delay of data transmission is reduced.

The destination chip 200 may cooperate with the source chip 100 described above. The destination chip 200 includes a first comparator 210, a second comparator 220, a clock recovery circuit 230, a data recovery circuit 240, and a serial-to-parallel conversion module 203.

The first comparator 210 is configured to receive encoded data sent by a chip at an opposite end, compare the encoded data with a first reference level, and output higher than the first reference level in the encoded data is a high level and output lower than the first reference level is a low level to obtain a first waveform. Wherein the first reference level is between the intermediate level and the high level.

The second comparator 220 is configured to receive the encoded data, compare the encoded data with a second reference level, and output higher than the second reference level in the encoded data is a high level, and output lower than the second reference level is a low level, so as to obtain a second waveform. Wherein the second reference level is between the intermediate level and the low level.

Referring to FIG. 6, the first reference level may be a dashed line denoted by D1 for the encoded data position in FIG. 6, and the second reference level may be a dashed line denoted by D2 for the encoded data position in FIG. 6. Fig. 7 shows a first waveform amp _ h obtained by processing the encoded data by the first comparator 210, and a second waveform amp _ l obtained by processing the encoded data by the second comparator 220.

The manner in which the first comparator 210 derives the first waveform from the encoded data is explained in detail below:

taking the first four-digit LHLM of encoded data as an example, please see fig. 6:

the first bit number L is lower than the first reference level D1 of the first comparator 210, and the output is 0;

if the second number H is higher than the first reference level D1 of the first comparator 210, the output is 1;

if the third bit number L is lower than the first reference level D1 of the first comparator 210, the output is 0;

if the fourth bit number M is lower than the first reference level D1 of the first comparator 210, the output is 0;

thus, the first waveform corresponding to the first four bits LHLM of encoded data is 0100.

The judgment can be performed according to each number of the encoded data, so that a complete first waveform amp _ h corresponding to the complete encoded data is obtained.

The manner in which the second comparator 220 derives the second waveform from the encoded data is explained in detail below:

the first four-digit LHLM of the encoded data is also not taken as an example, please see fig. 6:

the first bit number L is lower than the second reference level D2 of the second comparator 220, and the output is 0;

the second bit number H is higher than the second reference level D2 of the second comparator 220, the output is 1;

if the third bit number L is lower than the second reference level D2 of the second comparator 220, the output is 0;

the fourth bit number M is higher than the second reference level D2 of the second comparator 220, and the output is 1;

thus, the second waveform corresponding to the first four bits LHLM of encoded data is 0101.

The judgment can be performed according to each number of the encoded data, so as to obtain a complete second waveform amp _ l corresponding to the complete encoded data.

The clock recovery circuit 230 is configured to obtain a pulse with a waveform inverted from the first waveform and a pulse with a waveform inverted from the second waveform, and perform a combining process on the obtained pulses to obtain a clock recovery signal RXCLK.

Referring to fig. 7, the clock recovery circuit 230 includes at least one first delay 231, a first xor operator 232, at least one second delay 233, a second xor operator 234, an or operator 235, and a frequency divider 236.

The at least one first delay 231 is sequentially connected to delay the first waveform amp _ h and transmit the delayed first waveform to the first exclusive or operator 232. Wherein the delay time of the at least one first delayer 231 for the first waveform is greater than the sum of the change time of the rising edge of the first waveform and the change time of the falling edge of the first waveform.

The first exclusive or operator 232 is configured to perform an exclusive or operation on the first waveform and the delayed first waveform to obtain a first pulse waveform edge _ h. The first delay 231 is configured to delay the first waveform, and the first xor operator 232 is configured to xor the delayed first waveform with the first waveform to obtain a waveform composed of the pulse signal at the inversion position of the first waveform, which may be referred to as a first pulse waveform.

The at least one second delayer 233 is sequentially connected to delay the second waveform amp _ l and transmit the delayed second waveform to the second exclusive or operator 234. Wherein the delay time of the at least one second delayer 233 to the second waveform is greater than the sum of the change time of the rising edge of the second waveform and the change time of the falling edge of the second waveform.

The second exclusive or operator 234 is configured to perform an exclusive or operation on the second waveform and the delayed second waveform to obtain a second pulse waveform edge _ l. The second exclusive or operator 234 exclusive-ors the delayed second waveform and the second waveform to obtain a waveform composed of the pulse signal of the second waveform at the inversion position, which is referred to as a second pulse waveform.

The or arithmetic unit 235 is configured to perform or processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, where the pulse fusion waveform is a clock recovery signal edge _ h | edge _ l.

And taking the sum of the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform edge _ h | edge _ l, wherein the time interval between two adjacent pulses of the pulse fusion waveform edge _ h | edge _ l is the same as the time interval between two adjacent data in the encoded data, so that the pulse fusion waveform is a clock recovery signal.

The frequency divider 236 is configured to divide the clock recovery signal by two to obtain a clock recovery signal RXCLK with a duty ratio of 50%.

The rising edge and the falling edge of the clock recovery signal RXCLK can trigger signal collection, because the clock is recovered from the encoded data, the Jitter characteristic of the clock is consistent with the encoded data, and the difficulty of data recovery is reduced.

After obtaining the clock recovery signal, the clock recovery signal may be further subjected to a frequency division by two by the frequency divider 236, so as to obtain a clock recovery signal with a duty ratio of 50%. The clock recovery signal after the frequency division by two is more stable.

The data recovery circuit 240 is configured to collect encoded data according to the clock recovery signal and recover the encoded data into serial data.

The data recovery circuit 240 is specifically configured to: determining that the received current data is in an intermediate level state; and acquiring the level state of the previous data of the current data, and taking the level state of the previous data as the level state of the current data.

When the data recovery circuit 240 recovers the encoded data into serial data, the encoded data may be collected according to the frequency of the clock recovery signal, and whether the received current data is in the intermediate level state is determined according to the comparison result of the first comparator 210 and the second comparator 220, if not, the high level is recovered to 1 corresponding to the high level, and the low level is recovered to 0 corresponding to the low level. And if the current data is in the intermediate level state, acquiring the level state of the previous data, and determining the numerical value corresponding to the current data according to the level state of the previous data, wherein the recovery process is simple and has small operand.

The serial-to-parallel conversion module 203 is configured to convert the serial data recovered by the data recovery circuit 240 into four parallel data.

Through the cooperation of the first comparator 210, the second comparator 220 and the clock recovery circuit 230, the clock signal can be recovered from the encoded data.

Referring to fig. 9, fig. 9 shows a data transmission method provided in the embodiment of the present application, which is applied to the source chip 100, and specifically includes the following steps S110 to S120:

step S110, a data coding module of a source chip receives serial data, codes the serial data to obtain coded data, and transmits the coded data to a driver of the source chip, wherein any two adjacent data of the coded data have jump delay.

Step S120, the driver receives the encoded data and sends the encoded data to a destination chip of the opposite end, so that the destination chip of the opposite end processes the encoded data.

The data encoding module 110 may encode the serial data to obtain encoded data, so as to implement a transition delay between any two adjacent data of the encoded data. Because the jump delay exists between any two adjacent data, when the chip at the opposite end receives one data, the chip at the opposite end can know the change of the jump delay, namely the change of each jump delay corresponds to one received data, thereby equivalently realizing the transmission of clock signals by utilizing the coded data. Through the coding of the serial data, the coded data carries a clock signal through the change of the jump delay, and compared with a chip self-adaptive clock which does not carry the clock signal and needs an opposite terminal in the prior art, the difficulty of clock recovery is reduced, and the delay of data transmission is reduced.

Optionally, in a specific embodiment, the step S110 specifically includes the following steps: receiving current data; judging whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; if yes, encoding the current data into an intermediate level; if not, the level state corresponding to the current data is reserved.

The level state of the current data and the level state of the previous data can be compared to judge whether the level states of the current data and the previous data are consistent, if so, the level state of the current data is represented by an intermediate level, and if not, the original level state of the current data is reserved. Through the introduction of the middle level, the level state of the latter data in the two adjacent data can be changed when the two adjacent data are at the same level, so that the condition that the same level does not occur in the two adjacent data is realized.

Optionally, in another specific embodiment, the step S110 specifically includes the following steps: carrying out bit-to-bit exclusive-or operation on the serial data and the serial data delayed by one clock cycle to obtain an operation result; if the operation result is 0, determining the level of the data of the corresponding bit of the serial data to be an original level; if the operation result is 1, judging whether the level state of the previous bit data is an intermediate level; if the level state of the previous bit data is the intermediate level, determining the level of the data of the corresponding bit of the serial data as the original level; and if the level state of the previous bit data is not the intermediate level, determining that the level of the data of the corresponding bit of the serial data is the intermediate level.

The first digital flip-flop 111 may delay the serial data by one clock cycle, and perform an exclusive nor operation on the serial data and the serial data delayed by one clock cycle to obtain an operation result. The level state of the bit data can be determined according to the specific operation result and the level state of the previous bit data. If the operation result is 0, it indicates that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it indicates that the level state of the current bit data is the same as the actual level state of the previous bit data, and further determination is needed: whether the level state of the previous bit data is changed to the intermediate level. If the level state of the previous bit data is changed into the intermediate level, the level state of the current bit data does not need to be modified, and the original level can be directly output to be distinguished from the level state of the previous bit data; if the level state of the previous bit data is not changed to the intermediate level, the level state of the current bit data needs to be modified to the intermediate level to be distinguished from the level state of the previous bit data.

Referring to fig. 10, fig. 10 shows a data transmission method provided by the embodiment of the present application, which is applied to the destination chip 200, and specifically includes the following steps S210 to S240:

step S210, a first comparator of a destination chip receives encoded data sent by a source chip of an opposite terminal, compares the encoded data with a first reference level, outputs higher than the first reference level in the encoded data are high levels, and outputs lower than the first reference level are low levels, so as to obtain a first waveform, and transmits the first waveform to a clock recovery circuit of the destination chip.

Wherein the first reference level is between a middle level and a high level.

Step S220, a second comparator of the destination chip receives the encoded data, compares the encoded data with a second reference level, outputs higher than the second reference level in the encoded data are high levels, and outputs lower than the second reference level are low levels, so as to obtain a second waveform, and transmits the second waveform to a clock recovery circuit of the destination chip.

Wherein the second reference level is between the intermediate level and a low level.

In step S230, the clock recovery circuit obtains the pulse with the inverted waveform of the first waveform and the pulse with the inverted waveform of the second waveform, and performs combining processing on the obtained pulses to obtain a clock recovery signal, and transmits the clock recovery signal to the data recovery circuit of the destination chip.

Optionally, referring to fig. 11, in a specific embodiment, the step S230 may include the following steps S231 to S236:

in step S231, at least one first delay 231 delays the first waveform.

In step S232, the first exclusive or operator 232 performs exclusive or operation on the first waveform and the delayed first waveform to obtain a first pulse waveform, where the first pulse waveform is a waveform where a pulse signal corresponding to the waveform inversion of the first waveform is located.

In step S233, at least one second delay 233 delays the second waveform.

In step S234, the second xor operator 234 performs xor operation on the second waveform and the delayed second waveform to obtain a second pulse waveform, where the second pulse waveform is a waveform where a pulse signal corresponding to the waveform inversion of the second waveform is located.

In step S235, the or operator 235 performs or processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, where the pulse fusion waveform is the clock recovery signal.

The first exclusive or operator 232 performs exclusive or processing on the delayed first waveform and the first waveform to obtain a waveform composed of the pulse signal of the first waveform at the inversion position, and the waveform can be referred to as a first pulse waveform. The second exclusive or operator 234 exclusive-ors the delayed second waveform and the second waveform to obtain a waveform composed of the pulse signal of the second waveform at the inversion position, which is referred to as a second pulse waveform. And taking the sum of the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, wherein the time interval between two adjacent pulses of the pulse fusion waveform is the same as the time interval between two adjacent data in the coded data, so that the pulse fusion waveform is a clock recovery signal.

In step S236, the frequency divider 236 performs frequency division processing on the clock recovery signal to obtain a clock recovery signal with a duty ratio of 50%.

The clock recovery signal is subjected to frequency division by two by the frequency divider 236, and a clock recovery signal with a duty ratio of 50% is obtained. The clock recovery signal after the frequency division by two is more stable.

Step S240, the data recovery circuit collects the encoded data according to the clock recovery signal and recovers the encoded data into serial data.

Optionally, step S240 specifically includes the following steps: determining that the received current data is in an intermediate level state; and acquiring the level state of the previous data of the current data, and taking the level state of the previous data as the level state of the current data.

When the data recovery circuit 240 recovers the encoded data into serial data, the encoded data may be collected according to the frequency of the clock recovery signal, and whether the received current data is in the intermediate level state is determined according to the comparison result of the first comparator and the second comparator, if not, the high level is recovered to 1 corresponding to the high level, and the low level is recovered to 0 corresponding to the low level. And if the current data is in the intermediate level state, acquiring the level state of the previous data, and determining the numerical value corresponding to the current data according to the level state of the previous data, wherein the recovery process is simple and has small operand.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. The source chip is characterized by comprising a data coding module and a driver, wherein the data coding module is connected with the driver;

the data coding module is used for receiving serial data, coding the serial data to obtain coded data and transmitting the coded data to the driver, wherein any two adjacent data of the coded data have jump delay;

the driver is used for receiving the coded data and sending the coded data to a destination chip of an opposite end, so that the destination chip of the opposite end restores the coded data into the serial data according to the coded data with transition delay between any two adjacent data.

2. The source chip according to claim 1, wherein the data encoding module is configured to receive serial data and encode the serial data to obtain encoded data, and specifically includes:

receiving current data;

judging whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data;

if yes, encoding the current data into an intermediate level;

if not, encoding the current data into a level state consistent with the current data.

3. The source chip of claim 1, wherein the data encoding module comprises a first digital flip-flop, a second digital flip-flop, an exclusive-nor operator, and a selector;

the CLK end of the first digital trigger is connected with a clock signal line for transmitting a clock signal, the input end of the first digital trigger is connected with a serial data line for transmitting serial data, and the output end of the first digital trigger is connected with the first input end of the exclusive-nor operator;

the second input end of the exclusive OR operator is connected with the serial data line, and the output end of the exclusive OR operator is connected with the first input end of the selector;

the output end of the selector is connected with the input end of the second digital trigger;

the output end of the second digital flip-flop is connected with the second input end of the selector, and the CLK end of the second digital flip-flop is connected with the clock signal line.

4. The source chip according to claim 3, wherein the data encoding module is configured to receive the serial data and encode the serial data to obtain encoded data, and specifically includes:

performing bit-to-bit exclusive OR operation on the serial data and the serial data delayed by one clock cycle by the first digital trigger by using the exclusive OR operator to obtain an operation result;

if the operation result is 0, determining the level of the bit of the serial data corresponding to the operation result in the corresponding bit of the coded data as an original level by using the selector;

if the operation result is 1, judging whether the level state of the coded data corresponding to the previous bit of data of the serial data is an intermediate level according to the output result of the second digital trigger;

if the level state of the coded data corresponding to the previous bit of data is an intermediate level, determining that the level of the bit of the serial data corresponding to the operation result at the corresponding bit of the coded data is an original level;

and if the level state of the coded data corresponding to the previous bit of data is not the intermediate level, determining that the level of the bit of the serial data corresponding to the operation result in the corresponding bit of the coded data is the intermediate level.

5. A destination chip, comprising, in combination with the source chip of any one of claims 1-4, a first comparator, a second comparator, a clock recovery circuit, and a data recovery circuit;

the first comparator is used for receiving encoded data sent by a source chip of an opposite terminal, comparing the encoded data with a first reference level, and making an output of the encoded data, which is higher than the first reference level, be a high level and an output of the encoded data, which is lower than the first reference level, be a low level to obtain a first waveform, wherein the first reference level is between a middle level and the high level;

the second comparator is configured to receive the encoded data, compare the encoded data with a second reference level, and output higher than the second reference level in the encoded data is a high level and output lower than the second reference level is a low level to obtain a second waveform, where the second reference level is between the middle level and the low level;

the clock recovery circuit is used for acquiring a pulse with a first waveform and a pulse with a second waveform, and performing merging processing on the acquired pulses to acquire a clock recovery signal;

the data recovery circuit is used for collecting the coded data according to the clock recovery signal and recovering the coded data into serial data.

6. The destination chip of claim 5, wherein the clock recovery circuit comprises at least one first delay, a first XOR operator, at least one second delay, a second XOR operator, and an OR operator;

the at least one first delayer is used for delaying the first waveform;

the first exclusive-or operator is used for carrying out exclusive-or operation on the first waveform and the first waveform delayed by the at least one first delayer to obtain a first pulse waveform;

the at least one second delayer is used for delaying the second waveform;

the second exclusive-or operator is configured to perform exclusive-or operation on the second waveform and the second waveform delayed by the at least one second delay unit to obtain a second pulse waveform;

the OR arithmetic unit is used for carrying out OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, and the pulse fusion waveform is the clock recovery signal.

7. The destination chip according to claim 6, wherein the clock recovery circuit further comprises a divide-by-two divider, a CLK terminal of the divide-by-two divider being connected to an output terminal of the OR operator;

the frequency halving device is used for performing frequency halving processing on the clock recovery signal to obtain a clock recovery signal with a duty ratio of 50%.

8. The destination chip according to claim 5, wherein the data recovery circuit is configured to collect the encoded data according to the clock recovery signal and recover the encoded data into serial data, and specifically includes:

determining that the received current data is in an intermediate level state;

and acquiring the level state of the previous data of the current data, and taking the level state of the previous data as the level state of the current data.

9. A data transmission method, applied to a source chip, the method comprising:

the data coding module of the source chip receives serial data, codes the serial data to obtain coded data, and transmits the coded data to a driver of the source chip, wherein jump delay exists between any two adjacent data of the coded data;

and the driver receives the coded data and sends the coded data to a destination chip of an opposite end so that the destination chip of the opposite end processes the coded data.

10. A data transmission method, applied to a destination chip, the method comprising:

a first comparator of the destination chip receives encoded data sent by a source chip of an opposite terminal, compares the encoded data with a first reference level, outputs higher than the first reference level in the encoded data are high levels, outputs lower than the first reference level are low levels, a first waveform is obtained, and the first waveform is transmitted to a clock recovery circuit of the destination chip, wherein the first reference level is between a middle level and the high levels;

a second comparator of the destination chip receives the encoded data, compares the encoded data with a second reference level, outputs higher than the second reference level in the encoded data are high levels, outputs lower than the second reference level are low levels, a second waveform is obtained, and the second waveform is transmitted to a clock recovery circuit of the destination chip, wherein the second reference level is between the middle level and the low level;

the clock recovery circuit acquires the pulse with the inverted waveform of the first waveform and the pulse with the inverted waveform of the second waveform, performs parallel processing on the acquired pulses to acquire a clock recovery signal, and transmits the clock recovery signal to the data recovery circuit of the target chip;

and the data recovery circuit collects the coded data according to the clock recovery signal and recovers the coded data into serial data.

11. A processor system comprising a source chip according to any one of claims 1 to 4 and a destination chip according to any one of claims 5 to 8.