CN108063661A - Sample circuit and receiving circuit based on Manchester's code - Google Patents
Sample circuit and receiving circuit based on Manchester's code Download PDFInfo
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- CN108063661A CN108063661A CN201711384182.7A CN201711384182A CN108063661A CN 108063661 A CN108063661 A CN 108063661A CN 201711384182 A CN201711384182 A CN 201711384182A CN 108063661 A CN108063661 A CN 108063661A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
Abstract
The present invention provides a kind of sample circuit based on Manchester's code, including：Input unit；It is connected with input unit, the clock unit that manchester decoder generates clock signal is carried out to input signal；It is connected with clock unit, for being delayed clock signal to obtain the clock delay unit of clock delay signal；And input terminal is connected with input unit and clock delay unit, the sampling unit that output terminal is connected with clock unit, for generating sampled signal, and sampled signal is sent to clock unit.The above-mentioned sample circuit based on Manchester's code, the rate of sampling need not be adaptively adjusted according to data rate, it is controlled using clock delay unit under different application scene to the demand of clock signal, input signal is sampled by simple sample circuit to obtain sampled signal, and sampled signal is fed back into clock unit, control the generation of clock signal.Circuit scale is simple, low in energy consumption.
Description
Technical field
The present invention relates to interface circuit field, more particularly to a kind of sample circuit based on Manchester's code and reception
Circuit.
Background technology
Manchester's code (Manchester Encoding), also referred to as phase code (Phase Encode) are a kind of
Common synchronised clock coding techniques.Its application in Ethernet medium system belongs to two kinds of bit synchronization sides in data communication
Self-synchronizing method in method, i.e. recipient are locked using including the specific coding of synchronizing signal from signal itself and extracting synchronizing signal
The fixed clock pulse frequency of oneself, reaches synchronous purpose.Data and clock are encoded in same data flow by the coding techniques,
While transmission code information, clock sync signal is also transferred to other side together, has a saltus step in every coding, there is no straight
Ingredient is flowed, therefore with self-synchronization and good antijamming capability.
Existing Manchester's code receiver to the data oversampling received and recovery or is adopted using high-frequency clock
The module for having Frequency Locking with PLL (phaselocked loop) etc. generates sampling clock, according to predetermined coding rule, may sample
1 is identified as during 0 → 1 saltus step, 0 is identified as when sampling 1 → 0 saltus step；Or 0 is identified as when sampling 0 → 1 saltus step,
1 is identified as when sampling 1 → 0 saltus step.
However, the prior art by high-frequency clock carries out over-sampling to the data that receive, it is necessary to frequency to high-frequency clock
Rate has more accurate limitation or is required to adaptively adjust the rate of sampling according to data rate.This realization method will
Ask circuit complicated, power consumption is notable.
The content of the invention
Based on this, it is necessary to for the problem of existing Manchester's code receiver circuit is complicated, power consumption is notable, provide one
Sample circuit and receiving circuit of the kind based on Manchester's code.
A kind of sample circuit based on Manchester's code, including：
For obtaining the input unit of input signal；
Be connected with the input unit, for according to sampled signal to the input signal carry out manchester decoder generation
The clock unit of the clock signal of fixed frequency；
It is connected with the clock unit, for being delayed the clock signal to obtain the clock delay list of clock delay signal
Member；And
Input terminal is connected with the input unit and the clock delay unit, and output terminal is connected with the clock unit
Sampling unit, the sampling unit carry out the input signal by the clock delay signal sampling generation sampled signal,
And the sampled signal is sent to the clock unit.
In one embodiment, the clock unit includes：
The buffer that input terminal is connected with the input unit for carrying out buffered to the input signal, obtains
Buffering signals；
The phase inverter that input terminal is connected with the input unit, for the input signal to be converted to inversion signal；With
And
Input terminal is connected with the output terminal of the buffer, the output terminal of the phase inverter and the sampling unit, defeated
The selector that outlet is connected with the clock delay unit, the selector are used to believe the buffering according to the sampled signal
Number, the inversion signal carry out manchester decoder generation fixed frequency clock signal.
In one embodiment, the duty cycle of the delay duration of the clock delay unit and the clock delay signal into
Positive correlation.
In one embodiment, further include：
Input terminal is connected with the input unit, the input time delay unit that output terminal is connected with the clock unit.
In one embodiment, the sampled signal carries out sampling life by the clock delay signal to the input signal
Into.
In one embodiment, the sampled signal controls the selector to the buffering signals and the inversion signal
It carries out manchester decoder and generates the clock signal.
In one embodiment, the clock delay unit includes the phase inverter of even number superposition.
In one embodiment, the sampling unit includes trigger and sample circuit, when the trigger is triggered,
The sample circuit carries out the input signal by the clock delay signal sampling generation sampled signal.
In one embodiment, when not yet generating the sampled signal under original state, the clock signal with it is described
Input signal sequential is identical, and when the sampled signal reaches first rising edge, the clock retrieving unit starts Man Chesi
Particular solution code generates the clock signal of fixed frequency.
A kind of receiving circuit, including the above-mentioned sample circuit based on Manchester's code.
Above-mentioned sample circuit and receiving circuit based on Manchester's code, clock unit are obtained using manchester decoder
The clock signal of fixed frequency need not adaptively adjust the rate of sampling according to data rate, utilize clock delay unit control
To the demand of clock signal under different application scene processed, input signal is sampled by simple sample circuit
Signal, and sampled signal is fed back into clock unit, control the generation of clock signal.The circuit scale is simple, low in energy consumption.
Description of the drawings
Fig. 1 is the module diagram of the sample circuit based on Manchester's code of an embodiment；
Fig. 2 is the key signal sequence diagram of the sample circuit based on Manchester's code of an embodiment；
Fig. 3 is the module diagram of the clock unit of an embodiment；
Fig. 4 is the module diagram of the sample circuit based on Manchester's code of another embodiment；
Fig. 5 is the key signal sequence diagram of the sample circuit based on Manchester's code of another embodiment.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 is the module diagram of the sample circuit based on Manchester's code of an embodiment.It is as shown in Figure 1, a kind of
Sample circuit based on Manchester's code, including：
For obtaining the input unit 20 of input signal, be connected with input unit 20, for according to sampled signal to input
Signal carries out the clock unit 40 of the clock signal of manchester decoder generation fixed frequency；It is connected, is used for clock unit 40
Clock signal is delayed to obtain the clock delay unit 60 of clock delay signal；And input terminal prolongs with input unit 20 and clock
Shi Danyuan 60 is connected, and the sampling unit 80 that output terminal is connected with clock unit 40, sampling unit is by clock delay signal to defeated
Enter signal and carry out sampling generation sampled signal, and sampled signal is sent to clock unit 40.
Specifically, input unit 20 is the input interface being connected with external equipment, receives the input signal of external equipment, will
It inputs the sample circuit based on Manchester's code, and input signal is the external signal by Manchester's code.
Wherein, Manchester's code is a synchronised clock coding techniques, is that symbol is divided into two equal intervals, is compiled
It at 1/2 of code bit, if being encoded data bit as " 1 ", bears and jumps, otherwise jumped to be positive；The beginning of bits of coded, if being encoded counting
It is " 1 " according to position, is then high level, otherwise is low level.
Due to containing abundant clock signal, DC component base in manchester encoded data and synchronised clock Unified coding
Originally it is zero, receiver can be easier to recover synchronised clock, and synchronous demodulation goes out data, have good interference free performance, this
Make it more suitable for transmission.
Clock unit 40, the clock for carrying out manchester decoder generation fixed frequency to input signal according to sampled signal are believed
Number.The clock signal of wherein fixed frequency be compared with depending on agreement, therefore in the application scenarios with same protocol, clock
The frequency of signal is relatively-stationary.
Corresponding with above-mentioned Manchester's code, manchester decoder process is more complicated than encoding, generally, decoding process
There are following steps：
(1) baud rate (or baud rate of known data stream) of data flow is obtained；
(2) clock signal (being substantially to discriminate between a frame edge and subluxation frame edge) of synchronous data flow；
(3) data stream is decoded according to two steps above.
Clock delay unit 60, for being delayed clock signal to obtain clock delay signal.According to different demands, clock
The delay time of delay unit 60 is configurable, can be pre-configured with according to the frequency of known input signal, according to difference
Delay can obtain different duty cycles, suitable for plurality of application scenes, such as 50% is needed in an application scenarios
Duty cycle, can configurable clock generator delay unit 60 delay duration, make it equal to 0.5 times of unit interval, and can match somebody with somebody
The delayed data needs put are consistent with the bit rate of data, otherwise may cause communication failure, obtain clear less than complete
Sampled signal, wherein, the data of bit rate, that is, transmitted per unit time.Sampling unit 80 is by clock delay signal to input
Signal carries out sampling generation sampled signal, and sampled signal is fed back to clock unit 40, controls the work of clock unit 40.
Fig. 2 is the key signal sequence diagram of the sample circuit based on Manchester's code of an embodiment.As shown in Fig. 2,
Input signal is the external signal by Manchester's code, and Man Chesi is based on into above-mentioned in the initial data stream of input signal
After the sample circuit of spy's coding, since the sampled signal that control clock unit 40 works not yet feeds back to clock in the initial state
Unit 40, in this period, the clock signal that clock unit 40 generates is the signal identical with input signal sequential, according to stream
Journey, clock signal obtain clock delay signal, clock delay signal input sample unit 80 by the delay of clock delay unit 60
Sampled signal is obtained by sampling processing, and sampled signal is fed back into clock unit 40, from first rising of sampled signal
Edge starts, and control clock unit 40 starts manchester decoder, generates the clock signal of fixed frequency, starts stable Man Chesi
Special decoding process.
The above-mentioned sample circuit based on Manchester's code, clock unit are fixed frequency using manchester decoder
Clock signal need not adaptively adjust the rate of sampling according to data rate, and different application is controlled using clock delay unit
To the demand of clock signal under scene, input signal is sampled by simple sample circuit to obtain sampled signal, and will
Sampled signal feeds back to clock unit, controls the generation of clock signal.The circuit scale is simple, low in energy consumption.
Fig. 3 is the module diagram of the clock unit of an embodiment.In one embodiment, as shown in figure 3, clock unit
40 include：The buffer 42 that input terminal is connected with input unit, the phase inverter 44 and input that input terminal is connected with input unit
End is connected with the output terminal of buffer 42, the output terminal of phase inverter 44 and sampling unit 80, output terminal and clock delay unit
The selector 46 of 60 connections.
Wherein, buffer 42 is used to carry out buffered to input signal, obtains buffering signals, wherein, buffer 42 is again
Claim buffer register, the data for peripheral hardware is sent temporarily are stored, so that processor is taken it away or for temporary storeroom
Reason device is sent to the data of peripheral hardware.
Phase inverter 44 can by the phasing back 180 degree of input signal, for input signal to be converted to inversion signal, because
And the buffering signals and inversion signal phase obtained after buffer 42 and phase inverter 44 are opposite.
Selector 46 is used to carry out buffering signals, inversion signal the fixed frequency of manchester decoder generation according to sampled signal
The clock signal of rate.
Specifically, since Manchester's code with " 01 " and " 10 " represents in straight binary data " 1 " and " 0 "
, therefore in actual circuit design, we complete this function using simple alternative numerical selector.Opposite in phase
Buffering signals and inversion signal pass through alternative data selector and carry out manchester decoder and generate clock signal.Data select
Device is selected one specified from one group of input signal and is sent to the circuit of output terminal, two choosings according to given input address code
One data selector is to select one specified from two signals to send to the circuit of output terminal.
Clock unit 40 is just constituted by the combination of simple buffer 42, phase inverter 44 and selector 46, is only needed
Under the feedback control of sampled signal, carrying out manchester decoder to buffering signals and inversion signal by selector 46 can obtain
To the clock signal of fixed frequency, due to need not be adjusted to data rate adaptation, circuit is simple, is easy to implement.
Fig. 4 is the module diagram of the sample circuit based on Manchester's code of another embodiment.In an implementation
In example, as shown in figure 4, the sample circuit based on Manchester's code includes：It is defeated for obtaining the input unit 20 of input signal
Enter end to be connected with input unit 20, the input time delay unit 30 that output terminal is connected with buffer 42, phase inverter 44；Input terminal with it is defeated
Enter delay unit 30 to connect, for carrying out buffered to input time delay signal, obtain the buffer 42 of buffering signals；Input terminal
It is connected with input time delay unit 30, for input time delay signal to be converted to the phase inverter 44 of inversion signal；Input terminal and buffering
Device 42, phase inverter 44 and sampling unit 80 connect, the selector 46 that output terminal is connected with clock delay unit 60；With selector
46 connections, for clock signal to be delayed to obtain to the clock delay unit 60 of clock delay signal and input terminal and the input
Unit 20 and the clock delay unit 60 connect, and output terminal is connected with selector 46, and input is believed by clock delay signal
Sampling generation sampled signal number is carried out, and sampled signal is fed back to the sampling unit 80 of selector 46.
Specifically, input time delay unit 30, effect are to ensure that it is terminated in each unit interval of input signal
Overturning afterwards obtains clock to judge whether to Data flipping, and input time delay unit 30 and clock delay unit 60 include
The phase inverter of even number superposition realizes accurate delay, the delay being made up of phase inverter by the superposition of even number of inverters
Unit has good delay performance, and can be by adjusting the number of phase inverter come into the adjusting of line delay, circuit structure
Simply, power consumption is very low.
The delay duration of clock delay unit 60 and the duty cycle of clock delay signal are positively correlated.According to different applications
The demand of the corresponding different duty of environment, configures clock delay unit 60, to obtain better duty cycle.
Sampling unit 80 includes trigger and sample circuit, and when trigger is triggered, sample circuit passes through clock delay
Signal carries out input signal sampling generation sampled signal.
More specifically, above-mentioned trigger is d type flip flop, prolong for being synchronized to input signal by clock delay unit 60
When clock delay signal on, generate sampled signal, and sampled signal fed back into clock unit 40.D type flip flop is in clock arteries and veins
The forward position (positive transition 0 → 1) for rushing CP is overturn, and the next state of trigger is depending on D ends before the rising edge of a pulse arrival of CP
State, i.e. next state=D.Therefore, it has the function of to set to 0, puts 1 two kinds.Since there is circuit maintenance obstruction to make during CP=1
With so during CP=1, the data mode at D ends changes, and does not interfere with the output state of trigger.
It is appreciated that the various the composition of sampling unit 80 is not limited to sample circuit, it is any simply to reach sampling
The circuit of function is all within the protection domain of application.
Specifically, when not yet generating sampled signal under original state, clock signal is identical with input signal sequential, when adopting
When sample signal reaches first rising edge, clock unit 40 starts manchester decoder, generates the clock signal of fixed frequency.
Fig. 5 is the key signal sequence diagram of the sample circuit based on Manchester's code of another embodiment.Such as Fig. 5 institutes
Show, specific coding and decoding operation principle can be understood by sequence diagram, and input signal is by the outer of Manchester's code
Portion's signal after the initial data stream of original input signal enters the above-mentioned sample circuit based on Manchester's code, first passes through
Input time delay unit 30 obtains input time delay signal into line delay, and the input terminal of input buffer 42 and phase inverter 44 is defeated respectively
Go out buffering signals and inversion signal, since the sampled signal that control clock unit 40 works not yet feeds back to choosing in the initial state
Device 46 is selected, in this period, the clock signal that selector 46 generates is the signal identical with input signal, according to flow, when
Clock signal obtains clock delay signal by the delay of clock delay unit 60, and clock delay signal input sample unit 80 is by adopting
Sample handles to obtain sampled signal, and sampled signal is fed back to selector 46, since first rising edge of sampled signal, control
Selector 46 processed starts manchester decoder, generates the clock signal of fixed frequency, starts stable manchester decoder flow.
A kind of receiving circuit, including the above-mentioned sample circuit based on Manchester's code.Manchester is based on using above-mentioned
The sample circuit of coding obtains sampled signal, and the clock unit of the Acquisition Circuit is fixed frequency using manchester decoder
Clock signal need not adaptively adjust the rate of sampling according to data rate, and different application is controlled using clock delay unit
To the demand of clock signal under scene, input signal is sampled by simple sample circuit to obtain sampled signal, and will
Sampled signal feeds back to clock unit, controls the generation of clock signal.The circuit scale is simple, low in energy consumption.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and description is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that come for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of sample circuit based on Manchester's code, which is characterized in that including：
For obtaining the input unit of input signal；
It is connected with the input unit, fixed for carrying out manchester decoder generation to the input signal according to sampled signal
The clock unit of the clock signal of frequency；
It is connected with the clock unit, for being delayed the clock signal to obtain the clock delay unit of clock delay signal；
And
Input terminal is connected with the input unit and the clock delay unit, the sampling that output terminal is connected with the clock unit
Unit, the sampling unit carry out the input signal by the clock delay signal sampling generation sampled signal, and will
The sampled signal is sent to the clock unit.
2. the sample circuit according to claim 1 based on Manchester's code, which is characterized in that the clock unit bag
It includes：
The buffer that input terminal is connected with the input unit for carrying out buffered to the input signal, is buffered
Signal；
The phase inverter that input terminal is connected with the input unit, for the input signal to be converted to inversion signal；And
Input terminal is connected with the output terminal of the buffer, the output terminal of the phase inverter and the sampling unit, output terminal
The selector being connected with the clock delay unit, the selector be used for according to the sampled signal to the buffering signals,
The inversion signal carries out the clock signal of manchester decoder generation fixed frequency.
3. the sample circuit according to claim 1 based on Manchester's code, which is characterized in that the clock delay list
The delay duration and the duty cycle of the clock delay signal of member are positively correlated.
4. the sample circuit according to claim 3 based on Manchester's code, which is characterized in that further include：
Input terminal is connected with the input unit, the input time delay unit that output terminal is connected with the clock unit.
5. the sample circuit according to claim 1 based on Manchester's code, which is characterized in that the sampled signal by
The clock delay signal carries out sampling generation to the input signal.
6. the sample circuit according to claim 2 based on Manchester's code, which is characterized in that the sampled signal control
It makes the selector and the buffering signals and the inversion signal is carried out with the manchester decoder generation clock signal.
7. the sample circuit according to claim 1 based on Manchester's code, which is characterized in that the clock delay list
Member includes the phase inverter of even number superposition.
8. the sample circuit according to claim 1 based on Manchester's code, which is characterized in that the sampling unit bag
Trigger and sample circuit are included, when the trigger is triggered, the sample circuit is by the clock delay signal to institute
It states input signal and carries out sampling generation sampled signal.
9. the sample circuit according to claim 1 based on Manchester's code, which is characterized in that when under original state still
When not generating the sampled signal, the clock signal is identical with the input signal sequential, when the sampled signal reaches the
During one rising edge, the clock retrieving unit starts manchester decoder, generates the clock signal of fixed frequency.
10. a kind of receiving circuit, including such as sample circuit of the claim 1-9 any one of them based on Manchester's code.
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| CN201711384182.7A CN108063661B (en) | 2017-12-20 | 2017-12-20 | Sampling circuit and receiving circuit based on Manchester coding |
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| CN111404543A (en) * | 2020-05-27 | 2020-07-10 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
| CN111769835A (en) * | 2020-07-03 | 2020-10-13 | 北京电力自动化设备有限公司 | Manchester code decoding method based on FPGA and IEC60044-8 standard |
| CN113626352A (en) * | 2021-07-01 | 2021-11-09 | 珠海全志科技股份有限公司 | Reading calibration method of memory controller, computer device and readable storage medium |
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| TWI796872B (en) * | 2021-12-14 | 2023-03-21 | 大陸商集創北方（珠海）科技有限公司 | Data receiving circuit, display driver chip and information processing device |
| CN115955374A (en) * | 2022-12-15 | 2023-04-11 | 上海创景信息科技有限公司 | Adaptive Manchester encoding and decoding optimization system, method, equipment and medium |
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