CN108063661B - Sampling circuit and receiving circuit based on Manchester coding - Google Patents
Sampling circuit and receiving circuit based on Manchester coding Download PDFInfo
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- CN108063661B CN108063661B CN201711384182.7A CN201711384182A CN108063661B CN 108063661 B CN108063661 B CN 108063661B CN 201711384182 A CN201711384182 A CN 201711384182A CN 108063661 B CN108063661 B CN 108063661B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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Abstract
The invention provides a sampling circuit based on Manchester coding, which comprises: an input unit; the clock unit is connected with the input unit and used for generating a clock signal by performing Manchester decoding on the input signal; the clock delay unit is connected with the clock unit and used for delaying the clock signal to obtain a clock delay signal; and the sampling unit is used for generating a sampling signal and sending the sampling signal to the clock unit, wherein the input end of the sampling unit is connected with the input unit and the clock delay unit, and the output end of the sampling unit is connected with the clock unit. According to the sampling circuit based on Manchester coding, the sampling rate does not need to be adjusted in a self-adaptive mode according to the data rate, the clock delay unit is used for controlling the requirements of the clock signal under different application scenes, the input signal is sampled through the simple sampling circuit to obtain the sampling signal, the sampling signal is fed back to the clock unit, and the generation of the clock signal is controlled. The circuit scale is simple, and the power consumption is low.
Description
Technical Field
The invention relates to the field of interface circuits, in particular to a sampling circuit and a receiving circuit based on Manchester coding.
Background
Manchester Encoding, also called Phase Encoding, is a commonly used technique for Encoding synchronous clocks. The application of the method in the Ethernet media system belongs to a self-synchronization method in two bit synchronization methods in data communication, namely, a receiving party extracts a synchronization signal from a signal by using a special code containing the synchronization signal to lock the clock pulse frequency of the receiving party, thereby achieving the purpose of synchronization. The coding technology codes data and a clock into the same data stream, transmits a clock synchronization signal to the opposite side together while transmitting code information, and each bit code has a jump without a direct current component, so that the coding technology has self-synchronization capability and good anti-interference capability.
The existing manchester coding receiver adopts a high-speed clock to oversample and recover received data, or adopts a PLL (phase locked loop) and other modules with frequency locking to generate a sampling clock, and according to a preset coding rule, the sampling clock is possibly identified as 1 when the sampling is carried out to the jump of 0 → 1 and identified as 0 when the sampling is carried out to the jump of 1 → 0; or 0 when the transition 0 → 1 is sampled and 1 when the transition 1 → 0 is sampled.
However, the prior art oversampling of the received data by the high-speed clock requires a more precise limitation on the frequency of the high-speed clock, or requires an adaptive adjustment of the sampling rate according to the data rate. This implementation requires complex circuitry and significant power consumption.
Disclosure of Invention
In view of the above, it is necessary to provide a sampling circuit and a receiving circuit based on manchester encoding, which solve the problems of complexity and significant power consumption of the existing manchester encoding receiver circuit.
A sampling circuit based on Manchester encoding, comprising:
an input unit for acquiring an input signal;
the clock unit is connected with the input unit and is used for performing Manchester decoding on the input signal according to the sampling signal to generate a clock signal with fixed frequency;
the clock delay unit is connected with the clock unit and is used for delaying the clock signal to obtain a clock delay signal; and
the input end is connected with the input unit and the clock delay unit, the output end is connected with the sampling unit connected with the clock unit, and the sampling unit samples the input signal through the clock delay signal to generate a sampling signal and sends the sampling signal to the clock unit.
In one embodiment, the clock unit includes:
the buffer with an input end connected with the input unit is used for buffering the input signal to obtain a buffered signal;
the input end of the phase inverter is connected with the input unit and is used for converting the input signal into an inverted signal; and
the input end of the selector is connected with the output end of the buffer, the output end of the phase inverter and the sampling unit, the output end of the selector is connected with the clock delay unit, and the selector is used for performing Manchester decoding on the buffer signal and the inverted signal according to the sampling signal to generate a clock signal with fixed frequency.
In one embodiment, the delay duration of the clock delay unit is positively correlated with the duty cycle of the clock delay signal.
In one embodiment, further comprising:
the input end of the input delay unit is connected with the input unit, and the output end of the input delay unit is connected with the clock unit.
In one embodiment, the sampling signal is generated by sampling the input signal with the clock delay signal.
In one embodiment, the sampling signal controls the selector to manchester decode the buffered signal and the inverted signal to generate the clock signal.
In one embodiment, the clock delay unit comprises an even number of stacked inverters.
In one embodiment, the sampling unit includes a flip-flop and a sampling circuit that samples the input signal by the clock delay signal to generate a sampling signal when the flip-flop is triggered.
In one embodiment, when the sampling signal is not generated in the initial state, the clock signal has the same timing as the input signal, and when the sampling signal reaches the first rising edge, the clock acquisition unit starts manchester decoding to generate the clock signal of a fixed frequency.
A receiving circuit comprises the sampling circuit based on Manchester coding.
According to the sampling circuit and the receiving circuit based on Manchester coding, the clock unit obtains the clock signal with fixed frequency by using Manchester decoding, the sampling rate is not required to be adaptively adjusted according to the data rate, the clock delay unit is used for controlling the requirements on the clock signal in different application scenes, the input signal is sampled by the simple sampling circuit to obtain the sampling signal, the sampling signal is fed back to the clock unit, and the generation of the clock signal is controlled. The circuit has simple scale and low power consumption.
Drawings
FIG. 1 is a block diagram of a sampling circuit based on Manchester encoding according to an embodiment;
FIG. 2 is a timing diagram of key signals of a sampling circuit based on Manchester encoding according to an embodiment;
FIG. 3 is a block diagram of a clock unit according to an embodiment;
FIG. 4 is a block diagram of a sampling circuit based on Manchester encoding according to another embodiment;
FIG. 5 is a timing diagram of key signals of a sampling circuit based on Manchester encoding according to another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a block diagram of a sampling circuit based on manchester encoding according to an embodiment. As shown in fig. 1, a sampling circuit based on manchester encoding includes:
an input unit 20 for acquiring an input signal, a clock unit 40 connected to the input unit 20 for generating a clock signal of a fixed frequency by Manchester decoding the input signal according to the sampling signal; a clock delay unit 60 connected to the clock unit 40 for delaying the clock signal to obtain a clock delay signal; and a sampling unit 80 having an input terminal connected to the input unit 20 and the clock delay unit 60 and an output terminal connected to the clock unit 40, the sampling unit sampling the input signal by the clock delay signal to generate a sampling signal, and transmitting the sampling signal to the clock unit 40.
Specifically, the input unit 20 is an input interface connected to an external device, receives an input signal of the external device, which is an external signal subjected to manchester encoding, and inputs the input signal to the sampling circuit based on manchester encoding.
The Manchester coding is a synchronous clock coding technology, a code element is divided into two equal intervals, 1/2 bits of a coded bit are subjected to negative jump if the coded data bit is '1', and the coded bit is subjected to positive jump otherwise; at the beginning of the coded bit, if the coded data bit is "1", it is high, otherwise it is low.
Because the Manchester coded data and the synchronous clock unified code contain abundant clock signals, the direct current component is basically zero, the receiver can recover the synchronous clock easily and demodulate the data synchronously, and the receiver has good anti-interference performance, so that the receiver is more suitable for channel transmission.
The clock unit 40 generates a clock signal of a fixed frequency by manchester-decoding the input signal based on the sampling signal. Wherein the clock signal of fixed frequency is protocol dependent, and thus in application scenarios with the same protocol, the frequency of the clock signal is relatively fixed.
Corresponding to the above manchester encoding, the manchester decoding process is more complicated than encoding, and generally, the decoding process has the following steps:
(1) acquiring the baud rate of the data stream (or the baud rate of the known data stream);
(2) synchronizing the clock signal of the data stream (essentially distinguishing between bit frame edges and half-bit frame edges);
(3) the data stream is decoded according to the above two steps.
And the clock delay unit 60 is configured to delay the clock signal to obtain a clock delay signal. According to different requirements, the delay time of the clock delay unit 60 is configurable, and can be preconfigured according to the known frequency of the input signal, and different duty ratios can be obtained according to different delays, so that the clock delay unit 60 is suitable for various application scenarios, for example, a 50% duty ratio is required in one application scenario, and the delay time of the clock delay unit 60 can be configured to be equal to 0.5 times of a unit time interval, and the configurable delay information needs to be consistent with the bit rate of data, otherwise, communication failure may be caused, and a complete and clear sampling signal cannot be obtained, wherein the bit rate is data transmitted in unit time. The sampling unit 80 samples the input signal by the clock delay signal to generate a sampling signal, and feeds the sampling signal back to the clock unit 40 to control the operation of the clock unit 40.
FIG. 2 is a timing diagram of key signals of a sampling circuit based on Manchester encoding according to an embodiment. As shown in fig. 2, the input signal is an external signal subjected to manchester encoding, after an initial data stream of the input signal enters the sampling circuit based on manchester encoding, since the sampling signal controlling the operation of the clock unit 40 has not been fed back to the clock unit 40 in an initial state, in this time period, the clock signal generated by the clock unit 40 is a signal having the same timing as the input signal, according to the flow, the clock signal is delayed by the clock delay unit 60 to obtain a clock delay signal, the clock delay signal is input to the sampling unit 80 to obtain a sampling signal through sampling processing, and the sampling signal is fed back to the clock unit 40, and from a first rising edge of the sampling signal, the clock unit 40 is controlled to start manchester decoding, generate a clock signal with a fixed frequency, and start a stable manchester decoding flow.
According to the sampling circuit based on Manchester coding, the clock unit obtains the clock signal with fixed frequency by using Manchester decoding, the sampling rate is not required to be adaptively adjusted according to the data rate, the clock delay unit is used for controlling the requirements on the clock signal in different application scenes, the input signal is sampled by the simple sampling circuit to obtain the sampling signal, the sampling signal is fed back to the clock unit, and the generation of the clock signal is controlled. The circuit has simple scale and low power consumption.
Fig. 3 is a block diagram of a clock unit according to an embodiment. In one embodiment, as shown in fig. 3, the clock unit 40 includes: a buffer 42 having an input terminal connected to the input unit, an inverter 44 having an input terminal connected to the input unit, and a selector 46 having an input terminal connected to the output terminal of the buffer 42, the output terminal of the inverter 44, and the sampling unit 80, and an output terminal connected to the clock delay unit 60.
The buffer 42 is used for buffering the input signal to obtain a buffered signal, wherein the buffer 42 is also called a buffer register and is used for temporarily storing data sent by an external device so that the processor takes the data away or is used for temporarily storing the data sent by the processor to the external device.
The inverter 44 may invert the phase of the input signal by 180 degrees for converting the input signal into an inverted signal, so that the phases of the buffered signal and the inverted signal obtained after passing through the buffer 42 and the inverter 44 are opposite.
The selector 46 is configured to manchester decode the buffered signal and the inverted signal based on the sampling signal to generate a clock signal with a fixed frequency.
Specifically, since manchester encoding uses "01" and "10" to represent "1" and "0" in ordinary binary data, in practical circuit design, we use a simple one-out-of-two digital selector to accomplish this function. The buffer signal and the inverted signal with opposite phases are subjected to Manchester decoding through the alternative data selector to generate a clock signal. The data selector selects a specified one of a group of input signals to be supplied to the circuit of the output terminal based on a given input address code, and the alternative data selector is a circuit that selects a specified one of two signals to be supplied to the output terminal.
The clock unit 40 is formed by a simple combination of the buffer 42, the inverter 44 and the selector 46, and the buffer signal and the inverted signal are Manchester-decoded by the selector 46 under feedback control of the sampling signal to obtain a clock signal with a fixed frequency.
Fig. 4 is a block diagram of a sampling circuit based on manchester encoding according to another embodiment. In one embodiment, as shown in fig. 4, the sampling circuit based on manchester encoding includes: an input unit 20 for obtaining an input signal, an input terminal of the input unit 20 being connected to the input unit 20, and an output terminal of the input unit 30 being connected to the buffer 42 and the inverter 44; a buffer 42 having an input end connected to the input delay unit 30 and configured to buffer the input delay signal to obtain a buffered signal; an inverter 44 having an input terminal connected to the input delay unit 30 and converting the input delay signal into an inverted signal; a selector 46 having an input terminal connected to the buffer 42, the inverter 44, and the sampling unit 80, and an output terminal connected to the clock delay unit 60; the clock delay unit 60 is connected to the selector 46, and is configured to delay the clock signal to obtain a clock delay signal, and the input end of the clock delay unit 60 is connected to the input unit 20 and the clock delay unit 60, and the output end of the clock delay unit is connected to the selector 46, and the clock delay unit samples the input signal to generate a sampling signal, and feeds the sampling signal back to the sampling unit 80 of the selector 46.
Specifically, the input delay unit 30 is used for ensuring the inversion after each unit time interval of the input signal is finished so as to judge whether to perform data inversion to obtain a clock, the input delay unit 30 and the clock delay unit 60 comprise an even number of superposed inverters, accurate delay is realized through superposition of the even number of inverters, the delay unit formed by the inverters has good delay performance, delay adjustment can be performed by adjusting the number of the inverters, the circuit structure is simple, and the power consumption is low.
The delay time period of the clock delay unit 60 is in positive correlation with the duty ratio of the clock delay signal. The clock delay unit 60 is configured according to the requirements of different duty ratios corresponding to different application environments, so as to obtain a better duty ratio.
The sampling unit 80 includes a flip-flop and a sampling circuit that samples an input signal by a clock delay signal to generate a sampling signal when the flip-flop is triggered.
More specifically, the flip-flop is a D flip-flop, and is configured to synchronize the input signal with the clock delay signal delayed by the clock delay unit 60, generate a sampling signal, and feed back the sampling signal to the clock unit 40. The D flip-flop flips at the leading edge (positive transition 0 → 1) of the clock pulse CP, and the secondary state of the flip-flop depends on the state at the D-side before the rising edge of the pulse of CP arrives, i.e., the secondary state is D. Therefore, it has two functions of setting 0 and setting 1. Since the circuit has the function of maintaining the blocking during the period of CP being 1, the data state of the D end changes during the period of CP being 1, and the output state of the flip-flop is not influenced.
It should be understood that the configuration of the sampling unit 80 is not limited to a sampling circuit, and any circuit that can simply achieve the sampling function is within the scope of the application.
Specifically, when the sampling signal is not generated yet in the initial state, the clock signal has the same timing as the input signal, and when the sampling signal reaches the first rising edge, the clock unit 40 starts manchester decoding to generate a clock signal of a fixed frequency.
FIG. 5 is a timing diagram of key signals of a sampling circuit based on Manchester encoding according to another embodiment. As shown in fig. 5, a specific operation principle of encoding and decoding can be understood from a timing diagram, where an input signal is an external signal subjected to manchester encoding, after an initial data stream of the initial input signal enters the sampling circuit based on manchester encoding, the input signal is delayed by the input delay unit 30 to obtain an input delay signal, and the input delay signal is respectively input to the input ends of the buffer 42 and the inverter 44 to output a buffer signal and an inverted signal, since a sampling signal for controlling the operation of the clock unit 40 is not fed back to the selector 46 in an initial state, in this time period, a clock signal generated by the selector 46 is the same as the input signal, the clock signal is delayed by the clock delay unit 60 to obtain a clock delay signal according to the flow, the clock delay signal is input to the sampling unit 80 to obtain a sampling signal through sampling processing, and the sampling signal is fed back to the selector 46, starting from the first rising edge of the sampling signal, the selector 46 is controlled to start manchester decoding, a clock signal of a fixed frequency is generated, and a stable manchester decoding flow is started.
A receiving circuit comprises the sampling circuit based on Manchester coding. The sampling circuit based on the Manchester coding is used for obtaining a sampling signal, a clock unit of the sampling circuit obtains a clock signal with fixed frequency by using Manchester decoding, the sampling rate is not required to be adjusted in a self-adaptive mode according to the data rate, the clock delay unit is used for controlling the requirements of the clock signal under different application scenes, the simple sampling circuit is used for sampling an input signal to obtain the sampling signal, the sampling signal is fed back to the clock unit, and the generation of the clock signal is controlled. The circuit has simple scale and low power consumption.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A sampling circuit based on Manchester coding, comprising:
an input unit for acquiring an input signal;
the clock unit is connected with the input unit and is used for performing Manchester decoding on the input signal according to the sampling signal to generate a clock signal with fixed frequency; the clock unit comprises a buffer with an input end connected with the input unit and is used for buffering the input signal to obtain a buffering signal; the input end of the phase inverter is connected with the input unit and is used for converting the input signal into an inverted signal; and
the input end of the selector is connected with the output end of the buffer, the output end of the phase inverter and the sampling unit, the output end of the selector is connected with the clock delay unit, and the selector is used for performing Manchester decoding on the buffer signal and the inverted signal according to the sampling signal to generate a clock signal with fixed frequency; the clock delay unit is connected with the clock unit and is used for delaying the clock signal to obtain a clock delay signal; and
the input end is connected with the input unit and the clock delay unit, the output end is connected with the sampling unit connected with the clock unit, and the sampling unit samples the input signal through the clock delay signal to generate a sampling signal and sends the sampling signal to the clock unit.
2. The sampling circuit based on Manchester encoding according to claim 1, wherein a delay time duration of the clock delay unit is positively correlated with a duty cycle of the clock delay signal.
3. The manchester-encoding-based sampling circuit according to claim 2, further comprising:
the input end of the input delay unit is connected with the input unit, and the output end of the input delay unit is connected with the clock unit.
4. The manchester-encoding-based sampling circuit according to claim 1, wherein the sampling signal is generated by sampling the input signal with the clock delay signal.
5. The manchester-encoding-based sampling circuit according to claim 1, wherein the sampling signal controls the selector to manchester decode the buffered signal and the inverted signal to generate the clock signal.
6. The manchester-encoding-based sampling circuit of claim 1 wherein the clock delay unit comprises an even number of stacked inverters.
7. The manchester-encoding-based sampling circuit according to claim 1, wherein the sampling unit comprises a flip-flop and a sampling circuit, and wherein the sampling circuit samples the input signal by the clock delay signal to generate a sampling signal when the flip-flop is triggered.
8. The manchester-encoding-based sampling circuit according to claim 1, wherein the clock signal has the same timing as the input signal when the sampling signal has not been generated in an initial state, and wherein the clock acquisition unit starts manchester decoding to generate the clock signal of a fixed frequency when the sampling signal reaches a first rising edge.
9. The sampling circuit based on Manchester coding according to claim 1, wherein the input unit is an input interface connected with an external device, and is used for receiving an input signal of the external device; the input signal is an external signal that has been manchester encoded.
10. A receiving circuit comprising a sampling circuit based on manchester encoding according to any one of claims 1 to 9.
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| CN111404543B (en) * | 2020-05-27 | 2020-09-15 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
| CN111769835A (en) * | 2020-07-03 | 2020-10-13 | 北京电力自动化设备有限公司 | Manchester code decoding method based on FPGA and IEC60044-8 standard |
| CN114067725A (en) | 2020-07-29 | 2022-02-18 | 联咏科技股份有限公司 | Light emitting diode driver and light emitting diode driving apparatus |
| CN113626352B (en) * | 2021-07-01 | 2024-04-30 | 珠海全志科技股份有限公司 | Memory controller reading calibration method, computer device and readable storage medium |
| CN114172764B (en) * | 2021-12-03 | 2023-09-22 | 上海橙科微电子科技有限公司 | Method and system for detecting different rates in data communication |
| TWI796872B (en) * | 2021-12-14 | 2023-03-21 | 大陸商集創北方（珠海）科技有限公司 | Data receiving circuit, display driver chip and information processing device |
| CN115955374B (en) * | 2022-12-15 | 2024-06-04 | 上海创景信息科技股份有限公司 | Adaptive Manchester encoding and decoding optimization system, method, equipment and medium |
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