CN112840571A

CN112840571A - Cross-clock domain processing circuit

Info

Publication number: CN112840571A
Application number: CN201880098603.6A
Authority: CN
Inventors: 白玉晶; 刘旭辉
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2021-05-25
Anticipated expiration: 2038-12-29
Also published as: CN112840571B; WO2020133537A1

Abstract

A clock domain crossing processing circuit is used for realizing the processing of data between asynchronous clock domains with low delay. The clock domain crossing processing circuit comprises a phase alignment circuit (330) and a synchronization circuit (340), wherein the phase alignment circuit (330) is used for adjusting the phase of a local working clock according to a control signal which is recovered by input data and contains phase change information of an input data clock, so that the working clock is aligned with the phase of the input data clock, and the input data clock and the working clock are used as clocks of the synchronization circuit to synchronize the input data. The phase of the local working clock is adjusted by the control signal recovered by the input data clock, so that the input data clock and the adjusted working clock can synchronously input data with lower delay, and the time delay of the data passing through the clock domain crossing processing circuit is reduced.

Description

Cross-clock domain processing circuit

Technical Field

The present application relates to the field of digital circuits, and more particularly, to a clock domain crossing processing circuit.

Background

Serdes (SERializer/DESerializer) is an important high-speed Serial link physical layer Technology, and is widely applied to various general purpose I/O (Input and Output) interfaces, such as interfaces of PCIe (Peripheral Component Interface Express), Ethernet (Ethernet), and SATA (Serial Advanced Technology Attachment). When two devices communicate, Serdes is used to convert multiple paths of low-speed parallel data signals into high-speed serial data signals at a data transmitting end, and convert the high-speed serial data signals into multiple paths of low-speed parallel data signals again at a receiving end after passing through a transmission medium. With the development of high-speed serial link technology, Serdes has higher and higher speed, and the Insertion Loss (IL) of the medium in the interconnection medium of the high-speed link is increased, so that a retimer (timer) needs to be introduced into the link to amplify the driving capability of the signal, so that the high-speed link can tolerate larger Insertion Loss. Retimers are used to relay data signals transmitted over a high speed serial link, for example, by reconstructing the signal using an internal clock to increase the transmission energy of the data signal. In addition, a retimer may also be used to filter out link jitter. Thereby degrading the performance of data transmission.

Shown in fig. 1 is a Retimer (Retimer)100 of the prior art. Due to the large signal attenuation and high frequency jitter in the high speed serial link, retimer 100 is typically disposed in the high speed serial link to relay the data signal and filter out the link jitter. Retimer 100 includes a receiving end 110, a data processing circuit 120, and a transmitting end 130. The receiving terminal 110 is configured to recover a receiving clock signal corresponding to the serial data according to the received serial data, convert the serial data into parallel data, and output the parallel data and the receiving clock signal to the data processing circuit 120. The data processing circuit 120 includes a clock domain crossing processing circuit, which buffers the parallel data through an elastic buffer (elastic buffer) according to the receiving clock signal and a transmitting clock signal generated by the transmitting end 130, and outputs the buffered parallel data to the transmitting end 130. In addition, the data processing circuit 120 is also used to perform encoding, decoding, scrambling, descrambling, and other processing on the parallel data. The transmitting terminal 130 is configured to convert the parallel data output by the data processing circuit 120 into serial data and output the serial data. The elastic buffer is a buffer with a variable data buffer amount, and the data buffer amount is determined by the receiving clock signal and the sending clock signal.

The receiving clock signal is a clock recovered from the received serial data, and the transmitting clock signal is a clock signal generated by the transmitting terminal 130, that is, a clock signal generated from a reference clock of the retimer 100, so that there is a frequency difference between the receiving clock signal and the transmitting clock signal, and the frequency difference is not fixed. Therefore, on the one hand, the clock domain crossing processing circuit in the data processing circuit 120 needs to perform asynchronous clock domain processing on the parallel data, so that the parallel data is synchronized from the clock domain of the receiving clock signal to the clock domain of the transmitting clock signal, and at the same time, the frequency offset existing between the receiving clock signal and the transmitting clock signal is also processed. In the retimer 100, the data processing delay of the clock domain crossing processing circuit of the prior art is very large due to the presence of the elastic buffer, so that the time for data to pass through the retimer becomes long, thereby reducing the data processing performance of the entire system. Under some transmission protocols, when a clock spread spectrum function needs to be supported, a clock domain crossing processing circuit introduces a larger delay when performing clock domain crossing processing on a signal, so that the data processing performance of the whole system is further reduced, and the influence on a high-speed serial link with sensitive delay is particularly obvious.

Disclosure of Invention

Embodiments of the present application provide a clock domain crossing processing circuit, which may be used to solve the problem that data is high in time delay when processing the clock domain crossing.

In a first aspect, an embodiment of the present application provides a clock domain crossing processing circuit, configured to perform clock domain crossing processing on input data. The clock domain crossing processing circuit comprises a phase alignment circuit and a synchronization circuit, wherein the phase alignment circuit is used for adjusting the phase of a first working clock according to a first control signal so as to align the phases of the two clocks, and outputting an input data clock and the adjusted first working clock to the synchronization circuit, so that the synchronization circuit can perform clock domain crossing synchronization on input data according to the two clocks so as to generate synchronous data, namely, synchronizing the input data in the clock domain of the input data clock to the clock domain of an output data clock. The input data clock is a clock recovered according to input data, the frequency of the first working clock is equal to that of the input data clock, the first working clock is a working clock of the clock domain crossing processing circuit or uses the same reference clock as the clock domain crossing processing circuit, the first control signal is also a control signal recovered according to the input data, and the first control signal includes phase change information of the input data clock.

The cross-clock domain processing circuit takes the control signal recovered from the input data as a reference to adjust the phase of the local clock (namely, the first working clock), so that the adjusted local clock can follow the phase of the input data clock in real time to be used as the clock of the synchronous circuit, thereby saving the hardware resources occupied by the elastic buffer, shortening the time for the data to pass through the cross-clock domain processing circuit, reducing the time delay for the cross-clock domain processing circuit to process the data, and improving the efficiency of data transmission.

In a possible implementation manner, the phase alignment circuit includes a phase detector, a digital filter, and a phase interpolator, where the phase detector is configured to phase-detect an input data clock and an output data clock, the digital filter is configured to filter a result of the phase detection and a first control signal, and output a result after the filtering as a second control signal, and the phase interpolator is configured to adjust a phase of a first operating clock according to the second control signal, so that the first operating clock and the input data clock are phase-aligned, and output the adjusted first operating clock as the output data clock to the synchronization circuit and the phase detector. The process of filtering the jitter may be to superimpose the signal first and then filter the jitter, or may be to superimpose the signal after filtering the jitter first. By processing the first working clock, the jitter of the first working clock signal is filtered, and the phase of the original input data clock is tracked, so that the clock which is used for synchronizing and has the phase tracking of the input data clock is generated by less hardware resources.

In a possible implementation, the phase interpolator is further configured to: generating a second intermediate clock according to the first working clock, wherein the phase difference between the first working clock and the second intermediate clock is a preset phase difference; and adjusting the phases of the first working clock and the second intermediate clock according to the second control signal, so that the phase of the input data clock is ahead of the phase of the first working clock and behind the phase of the second intermediate clock. The phase detector is further configured to perform phase detection on the input data clock, the output data clock (i.e., the adjusted first working clock) and the second intermediate clock, so as to determine a phase relationship among the three clocks and output a phase detection result. Through the phase adjustment, the phase interpolator can enable the rising edge of the input data clock to be always kept between the rising edge of the first working clock and the rising edge of the second intermediate clock, so that the purpose of phase alignment is achieved, and the phase interpolator can be used for synchronizing the input data.

In one possible embodiment, the phase interpolator adjusts the phases of the first operating clock and the second intermediate clock such that the phase difference between the first operating clock and the input data clock is equal to the phase difference between the input data clock and the second intermediate clock. The adjusted first operating clock generated by the phase interpolator is better able to phase align with the input data clock when the phase difference between the first operating clock and the second intermediate clock is small.

In a possible implementation, the phase interpolator is further configured to: when the phase of the input data clock is ahead of the phase of the first operating clock and behind the phase of the second intermediate clock, the second control signal is in a first state (e.g., binary number 10) to instruct the phase interpolator to maintain the phases of the first operating clock and the second intermediate clock; when the phase of the input data clock lags the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is in a second state (for example, binary number 00) to instruct the phase interpolator to adjust the phase, so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock; when the phase of the input data clock leads the phase of the first operating clock and leads the phase of the second intermediate clock, the second control signal is in a third state (e.g., binary number 01) to instruct the phase interpolator to adjust the phase such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock. When the frequency of the input data clock is deviated, the first working clock and the second intermediate clock are synchronously deviated, so that the first working clock can follow the phase of the input data clock in real time.

In a possible implementation, the filtering of the first control signal and the phase detection result by the digital filter is high frequency filtering, where the filtered first control signal includes phase change information corresponding to low frequency jitter of the input data clock. When the phase alignment circuit filters jitter of the input data clock at a high frequency, the jitter carried by the clock at a low frequency can be preserved and output to a downstream device along with the synchronous data, so that the cross-clock domain processing circuit can support a specific protocol or preset functions in the transmission link, such as turning on and off the SRIS function.

In a possible embodiment, the phase variation information includes independent clock spread spectrum information, independent clock non-spread spectrum information, or homologous clock information.

In a possible embodiment, the synchronization circuit includes a first sub-synchronization circuit and a second sub-synchronization circuit, wherein the first sub-synchronization circuit is configured to synchronize the input data according to an input data clock and output the result to the second sub-synchronization circuit; and the second sub-synchronous circuit synchronizes the result according to the first working clock to obtain the synchronous data. The synchronous processing of input data is realized through the two sub-synchronous circuits, the circuit structure of the clock domain crossing processing circuit is simplified, and the hardware area and the power consumption are saved.

In a possible implementation manner, the first sub-synchronization circuit and the second sub-synchronization circuit are both registers, and the two sub-synchronization circuits synchronize the input data through the input data clock and the first operation clock, respectively. The sub-synchronous circuit is realized through the register, so that the circuit complexity of the clock domain crossing processing circuit is greatly simplified, and the hardware area and the power consumption are further saved.

In a possible implementation, the clock domain crossing processing circuit further includes a first clock circuit for providing the first operating clock to the phase alignment circuit. The first working clock provided by the first clock circuit has less jitter and clutter, and is beneficial to the clock domain crossing synchronization of data.

In a possible implementation, the clock domain crossing processing circuit further includes a clock recovery circuit, which is configured to be driven by an operating clock of the clock domain crossing processing circuit, recover the received input data to obtain an input data clock and a first control signal, and output the input data, the first control signal, and the input data clock. The clock recovery circuit is used for carrying out clock recovery on input data, so that the recovered clock can be used for synchronizing the input data after being subjected to phase adjustment and the like, and the clock domain crossing processing is realized.

In one possible implementation, the input data is serial data, and the clock domain crossing processing circuit further includes a serial-to-parallel circuit configured to perform serial-to-parallel conversion on the input data and output the input data after the serial-to-parallel conversion (i.e., parallel input data) to the synchronization circuit. Correspondingly, the data between the two sub-synchronous circuits in the synchronous circuit is also parallel data. When the clock domain crossing processing circuit is used for processing parallel data, the efficiency of data synchronization can be improved.

In one possible implementation, the sending end sends input data to the cross-clock domain processing circuit, and the synchronous data is output to the receiving end, where the following three conditions exist: firstly, the sending end and the clock domain crossing processing circuit share one reference clock, and a clock used by the receiving end is independent of the shared reference clock; secondly, the receiving end and the clock domain crossing processing circuit share one reference clock, and the reference clock of the transmitting end is independent of the shared reference clock; and thirdly, the sending end, the receiving end and the clock domain crossing processing circuit share one reference clock. The reference clock of the clock domain crossing processing circuit can be independent of the receiving end and the sending end, and can also share the reference clock, so that the configuration of the clock signal is more flexible.

In a second aspect, embodiments of the present application provide a retimer for relaying N input data in a transmission link. The retimer includes a phase alignment circuit and N synchronization circuits (N is greater than or equal to 1 and N is a positive integer), where the phase alignment circuit is configured to adjust a phase of a first working clock according to a first control signal to align phases of the two clocks, and output an input data clock and the adjusted first working clock to the N synchronization circuits, so that the N synchronization circuits may perform clock domain crossing synchronization on N input data according to the two clocks to generate N synchronization data, that is, synchronize N input data in a clock domain of the input data clock to a clock domain of an output data clock. The frequency of the first working clock is equal to the frequency of the input data clock, the first working clock is the working clock of the retimer, or the same reference clock is used with the retimer, the input data clock is one of N recovered clock clocks recovered from N paths of input data, for example, the N recovered data clocks are recovered from N paths of input data through a clock recovery circuit, and one of the recovered clocks is selected as the input data clock. The first control signal is also one of N control signals recovered according to N paths of input data, and the first control signal includes phase change information of the input data clock.

The retimer uses the control signal recovered from the N input data paths as a reference to adjust the phase of the local clock (i.e., the first working clock), so that the adjusted local clock can follow the phase of the input data clock in real time to serve as the clock of the synchronization circuit, thereby saving the hardware resources occupied by the elastic buffer, shortening the time for the data to pass through the retimer, reducing the time delay for the retimer to process the data, and improving the efficiency of data transmission.

In a possible implementation manner, the phase alignment circuit includes a phase detector, a digital filter, and a phase interpolator, where the phase detector is configured to phase-detect an input data clock and an output data clock, the digital filter is configured to filter a result of the phase detection and a first control signal, and output a result after the filtering as a second control signal, and the phase interpolator is configured to adjust a phase of a first operating clock according to the second control signal, so that the first operating clock and the input data clock are phase-aligned, and output the adjusted first operating clock as the output data clock to the N synchronization circuits and the phase detector. By processing the first working clock, the jitter of the first working clock signal is filtered, and the phase of the original input data clock is tracked, so that the clock which is used for synchronizing and has the phase tracking of the input data clock is generated by less hardware resources.

In a possible implementation manner, each of the N synchronization circuits includes a first sub-synchronization circuit and a second sub-synchronization circuit, where the first sub-synchronization circuit is configured to synchronize one of the N input data according to an input data clock and output a result to the second sub-synchronization circuit; and the second sub-synchronous circuit synchronizes the result according to the first working clock to obtain one path of synchronous data in the synchronous data. The synchronous processing of the input data is realized through the two sub-synchronous circuits, the circuit structure of the retimer is simplified, and the hardware area and the power consumption are saved.

In a possible implementation manner, the first sub-synchronization circuit and the second sub-synchronization circuit are both registers, and the two sub-synchronization circuits synchronize the input data through the input data clock and the first operation clock, respectively. The sub-synchronous circuit is realized through the register, so that the circuit complexity of the retimer is greatly simplified, and the hardware area and the power consumption are further saved.

In one possible embodiment, the retimer further includes a first clock circuit for providing the first operating clock to the phase alignment circuit. The first working clock provided by the first clock circuit has less jitter and clutter, and is beneficial to the clock domain crossing synchronization of data.

In a possible implementation, the filtering of the first control signal and the phase detection result by the digital filter is high frequency filtering, where the filtered first control signal includes phase change information corresponding to low frequency jitter of the input data clock. When the phase alignment circuit high frequency filters the input data clock, the low frequency jitter carried by the clock can be preserved and output to downstream devices along with the synchronization data so that the retimer can support specific protocols or preset functions in the transmission link, such as turning SRIS functions on and off.

In a possible implementation, the retimer further includes N clock recovery circuits, which are respectively driven by the first operation clock of the retimer, recover the received N input data to obtain the N recovered data clocks and N control signals, and output the N input data, the N control signals, and the N recovered data clocks. The clock recovery circuit is used for carrying out clock recovery on input data, so that the recovered clock can be used for synchronizing the input data after being subjected to filtering, jittering and the like, and the clock domain crossing processing is realized.

In one possible implementation, the N input data are N serial input data, and the retimer further includes N deserializers, where the N deserializers are configured to deserialize the N input data and output converted results (i.e., N parallel data) to the N synchronization circuits. By converting the data from serial to parallel, the high-speed serial data in the transmission link can be converted into parallel data, the efficiency of the retimer for processing the data is improved, and the data processing time is saved.

In a possible implementation manner, the retimer further includes N parallel-to-serial circuits, and the N parallel-to-serial circuits are N parallel data, where the N parallel-to-serial circuits are configured to perform parallel-to-serial conversion on the N parallel synchronous data, respectively, and output a converted result. By converting the data into parallel serial, the processed (synchronized) data can be converted into high-speed serial signals again, the efficiency of the retimer for processing the data is improved, and the data processing time is saved.

In a possible implementation, the retimer further includes N data processing circuits and N data selectors, wherein input terminals of the N data processing circuits are respectively coupled to output terminals of the N clock recovery circuits, output terminals of the N data processing circuits are respectively coupled to input terminals of the N data selectors, and the N data processing circuits are configured to respectively decode, descramble, synchronize, scramble, and encode N paths of received input data; for each of the data processing circuit, the clock recovery circuit and the data selector coupled to each other, two input terminals of the data selector are coupled to an output terminal of the clock recovery circuit and an output terminal of the data processing circuit, respectively, and an output terminal of the data selector is coupled to an output terminal of the synchronization circuit. The data selector may be controlled by an additional control signal to select one of the two data signals received at the two input terminals as an output. In the retimer, data can directly perform synchronization across clock domains through the data selector, or can be processed by the data processing circuit first and then perform synchronization across clock domains through the data selector, so that the mode of processing input data by the retimer is more flexible, whether direct data pass through can be selected according to different transmission protocols, and the efficiency of relaying data is improved.

In one possible implementation, the sending end sends input data to the retimer and the synchronized data is output to the receiving end, where the following three cases exist: firstly, the sending end and the retimer share one reference clock, and a clock used by the receiving end is independent of the shared reference clock; secondly, the receiving end and the retimer share one reference clock, and the reference clock of the transmitting end is independent of the shared reference clock; and thirdly, the transmitting end, the receiving end and the retimer share one reference clock. The reference clock of the retimer may be independent from the receiving end and the transmitting end, or may share the reference clock, so that the configuration of the clock signal thereof is more flexible.

In one possible embodiment, the retimer is a multi-channel retimer, where N ≧ 2, and N is a positive integer. By increasing the number of circuits such as a synchronization circuit and a clock recovery circuit in the retimer, the retimer can simultaneously process multiple paths of input data, thereby further improving the efficiency of the retimer in relaying data.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a retimer of the prior art.

Fig. 2 is a retimer according to an embodiment of the present application.

Fig. 3 is a specific retimer in an embodiment of the present application.

Figure 4 is a more specific retimer in an embodiment of the present application.

FIG. 5(a) is a timing diagram of the phase interpolator in the embodiment of the present application;

FIG. 5(b) is another timing diagram of the phase interpolator in the embodiment of the present application;

fig. 5(c) is a timing chart of the phase interpolator according to the embodiment of the present application.

Fig. 6 is a synchronization circuit according to an embodiment of the present application.

Figure 7 is a more specific retimer in an embodiment of the present application.

Fig. 8 is a data processing circuit according to an embodiment of the present application.

Fig. 9 is a multi-channel retimer according to an embodiment of the present application.

The main reference numbers: a retimer 300; a data receiving circuit 310; a clock recovery circuit 312; a serial-to-parallel circuit 314; an equalizer 316; a second clock circuit 318; a data transmission circuit 320; a phase alignment circuit 330; a phase detector 332; a digital filter 334; a phase interpolator 336; a first clock circuit 335; a synchronization circuit 340; and a parallel-to-serial circuit 370.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

To address the problem of large retimer delay, embodiments of the present application provide a retimer 300 as shown in fig. 2. The retimer 300 is disposed on a high-speed serial communication link between the first device 210 and the second device 220. The communication link may be a communication link using PCIe (Peripheral Component Interface), Ethernet (Ethernet), and SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), USB (Universal Serial Bus), or other protocols. Retimer 300 is used to relay the data signal, for example, by reconstructing the signal using an internal clock, which increases the transmission energy of the data signal. Retimer 300 may also be used to filter out jitter in the communication link described above. The data signal may be a data signal transmitted from the first device 210 to the second device 220, or may be a data signal transmitted from the second device 220 to the first device 210. The first device and the second device may include terminal devices, such as a mobile phone and a tablet computer; may also include server devices, or communication base stations; or include circuitry disposed on two separate PCBs (Printed Circuit boards).

One particular embodiment of retimer 300 is shown in fig. 3. The retimer 300 includes a receiving circuit 310 and a transmitting circuit 320, wherein the receiving circuit 310 includes a clock recovery circuit 312 and a serial-parallel circuit 314, the clock recovery circuit 312 is configured to perform clock recovery on received serial data (input data) according to driving of a reference clock thereof, so as to obtain an input data clock and a first control signal, and output the serial data at the same time, and the recovered input data clock and the first control signal, the reference clock may be an operation clock of the receiving circuit 310, and the first control signal includes phase change information of the input data clock. The serial-to-parallel circuit 314 converts the serial data into parallel data and outputs the parallel data. Wherein the operating clock of receive circuitry 310 may be determined from the reference clock of retimer 300. The clock recovery circuit 312 can recover the clock by detecting the phase of the serial data, and the clock recovery circuit 312 can be implemented in various ways, such as using a passive filter and a limiting amplifier, using a narrow-band regenerative divider, using a synchronous oscillator, or using a phase-locked loop.

The transmitting circuit 320 is configured to perform clock domain crossing synchronization on the parallel data output by the receiving circuit 310, convert the synchronized parallel data into serial data, and output the serial data to the second device 220. Specifically, the transmission circuit 320 includes a phase alignment circuit 330, a synchronization circuit 340, and a parallel-to-serial circuit 370. The phase alignment circuit 330 is configured to receive the input data clock and the first working clock, adjust a phase of the first working clock according to the first control signal, so that the adjusted phase of the first working clock is aligned with the phase of the input data clock, and output the adjusted first working clock to the synchronization circuit 340 as the output data clock. The input data clock is a clock recovered by the clock recovery circuit 312 according to the input data, and the first control signal is also information recovered by the clock recovery circuit 312 according to the input data, which can be used as a control signal to control the phase alignment circuit 330 to adjust the phase of the first operating clock. The first operating clock is a clock independent from the input data clock, and is an operating clock of the transmitting circuit 320 in the retimer 300, and the frequency of the first operating clock is equal to the frequency of the input data clock. It should be noted that the first operating clock, i.e., the operating clock of the transmitting circuit 320 and the operating clock of the receiving circuit 310 (i.e., the second operating clock, hereinafter) are independent operating clocks, but the same reference clock (reference clock) or different reference clocks may be used.

The synchronization circuit 340 is configured to perform clock domain crossing synchronization on the parallel data generated by the clock recovery circuit 312 according to the input data clock and the output data clock, and generate synchronization data, where the synchronization data is in a clock domain of the output data clock. Since the data in the receiving circuit 310 is in the clock domain of the input data clock and the data in the transmitting circuit 320 is in the clock domain of the output data clock, the synchronizing circuit 340 synchronizes the parallel data from the clock domain of the input data clock to the clock domain of the output data clock. The parallel-to-serial circuit 370 is configured to convert the received synchronization data into serial output data and output the serial output data to the second device 220. The jitter of the high frequency components described above includes high frequency jitter generated by the high speed serial communication link and high frequency jitter generated by the clock recovery circuit 312 when recovering the clock.

It should be noted that "high frequency" in high frequency jitter and high frequency filtering in the present application should be a concept well known to those skilled in the art. The range of "high frequency" in this application will vary for clock signals of different frequencies. For example, for a clock signal with a frequency f equal to 100MHz, the jitter carried by the clock signal with a frequency greater than 0.5f should be considered as high-frequency jitter; correspondingly, the high-frequency jitter filtering is to filter out jitter with frequency greater than 0.5 f. More specifically, the phase alignment circuit 330 provided in this embodiment of the present application can perform high-frequency jitter filtering on a clock signal of 100MHz, and jitter carried by the clock signal and having a frequency higher than 500KHz is filtered. Correspondingly, low frequency jitter is jitter with a frequency less than 0.5 f. For another example, for a clock signal with a frequency f of 1GHz, the jitter carried by the clock signal with a frequency greater than 0.05f should be considered as high-frequency jitter, and the jitter below 0.05f should be considered as low-frequency jitter. Furthermore, phase alignment in this application is understood to mean that the phase difference of the rising edges of the two clock signals is a fixed value, for example, the phase difference is maintained at-1 °, 0 ° or 1 °; it can also be understood that the phase difference of the rising edges of the two clock signals remains within a certain range.

The first operating clock is an operating clock of the retimer, i.e., the clock is a local clock with less jitter. The retimer 300 uses the above-mentioned first control signal recovered from the input data to adjust the phase of the local clock, so that the adjusted local clock can follow the phase of the input data clock in real time to serve as the clock of the synchronization circuit 340, and the retimer 300 does not need to synchronize the clock domains through an elastic buffer when relaying data, so that the time for the data to pass through the retimer 300 is shorter, thereby reducing the delay of the retimer 300 in processing data, especially the delay of the data when crossing the clock domains, and improving the efficiency of data transmission.

Fig. 4 shows a specific embodiment of the phase alignment circuit 330. The Phase alignment circuit 330 includes a Phase Detector (PD) 332, a Digital Filter (Digital Filter)334, and a Phase Interpolator (PI) 336. The phase detector 332 is configured to perform phase detection on the output data clock and the input data clock, i.e., identify a phase relationship between the two clocks, and output a phase detection result. The digital filter 334 is configured to filter the phase detection result and the first control signal, and output the filtered result to the phase interpolator 336 as a second control signal. The digital filter 334 may add the phase discrimination result and the first control signal, filter the jitter, and output the result as a second control signal; or the phase discrimination result and the first control signal may be filtered and then superimposed, and then output as a second control signal. In one embodiment, the digital filter 334 is not responsive to high frequency jitter, but only to low frequency jitter, i.e., only filters out high frequency jitter while retaining low frequency jitter, which may carry information about the frequency or phase change of the input data clock. The phase interpolator 336 is configured to adjust a phase of the first operating clock according to the second control signal, so that the first operating clock is aligned with the input data clock, and output the adjusted first operating clock to the synchronization circuit 340 and the phase detector 332 as the output data clock.

Specifically, the phase interpolator 336 generates a second intermediate clock according to the phase of the first working clock, and the phase difference between the second intermediate clock and the first working clock is a preset fixed phase difference; secondly, the phase detector 332 performs phase detection on the output data clock, the second intermediate clock and the input data clock to determine the phase relationship among the three clock signals and output a phase-detected result, the digital filter 334 filters the phase-detected result and filters the first control signal at the same time, the two filtered results are superposed, and the superposed signal is output to the phase interpolator 336 as a second control signal, wherein the filtering is to filter jitter in the signal; the phase interpolator 336 adjusts the phases of the first operating clock and the second intermediate clock according to the second control signal, such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock, and outputs the adjusted first operating clock as the output data clock to the synchronization circuit 340 and the phase discriminator 332.

The first control signal is a control signal recovered by the clock recovery circuit 312. Specifically, the clock recovery circuit 312 recovers the first control signal including phase change information corresponding to jitter included in the input data clock while performing clock recovery on the input data, that is, the first control signal may indicate a state of phase change of the input data clock. In one embodiment, the first control signal includes low-frequency jitter information of the input data Clock, the low-frequency jitter is also called low-frequency offset (wander), and is usually Spread Spectrum Clock (Spread Spectrum Clock) information, or called non-uniform Reference Clock (Separated Reference Clock) information, such as independent Clock Spread Spectrum information, and may also be independent Clock non-Spread Spectrum information; the low frequency jitter may also be Common Reference Clock (Common Reference Clock) information; while the first control signal also includes high frequency jitter information of the input data clock, which typically comes from high frequency noise (or high frequency jitter) generated by the clock recovery circuit 312 and generated by the link. Therefore, the digital filter 334 is further configured to perform high frequency jitter filtering on the first control signal and the phase detection result to filter out high frequency noise and to retain phase change information corresponding to low frequency jitter of the input data clock.

As shown in fig. 4, the retimer 300 further includes a second clock circuit 318 and a first clock circuit 335, wherein the second clock circuit 318 is configured to generate a second operating clock according to the reference clock and output the second operating clock to the clock recovery circuit 312, so that the clock recovery circuit 312 recovers a clock signal from the input data; the first clock circuit 335 is used for generating a first operating clock according to the reference clock and outputting the first operating clock to the phase alignment circuit 330 to generate an output data clock. The first operating clock is generated by the first clock circuit 335 in the transmitting circuit 320, and the frequency of the first operating clock generated by the first clock circuit 335 is equal to the frequency of the input data clock. It should be noted that the second clock circuit 318 and the first clock circuit 335 in this embodiment are independent clock circuits, and the two clock circuits may be Phase Locked Loops (PLLs) or the like. The second clock circuit 318 and the first clock circuit 335 may use the same clock source as a reference clock, or may use two independent clock sources as reference clocks.

Since the clock signal is usually rectangular pulses having the same pulse width, its spectral components include higher harmonics, and the clock signal and these higher harmonics together generate electromagnetic interference in a certain circuit or between different circuits. In order to reduce the electromagnetic interference, a method of spreading a clock may be adopted, in which a predetermined modulation waveform (e.g., a lower frequency) is used to perform frequency modulation on the clock signal within a certain frequency range, so that peak energy included in the fundamental frequency and harmonics of the clock signal is reduced. For example, in the high-speed serial link, the input data clock may be a clock carrying spread spectrum clock SSC information. In the frequency domain, the SSC information appears as a clock signal that produces a spectrum with sideband harmonics. The digital filter 334 may preserve the full low frequency jitter while filtering the first intermediate clock at a high frequency, thereby preserving some of the clock information contained in the first intermediate clock, or some of the clock information contained in the input data clock, such as SSC information. At the same time, the digital filter 334 filters out high frequency jitter from the link and clock recovery circuit 312, etc. Therefore, when the SRIS function (Separate Reference-clock Independent SSC) is turned on in the high-speed serial link, both the input data clock and the output data clock in the retimer 300 may retain SSC information in the clock signal while filtering out high frequency jitter.

Since the input data clock contains low frequency jitter, the phase of the rising edge of the input data clock is usually not fixed, but drifts back and forth. As shown in fig. 5, the input data clock drifts within a certain clock offset range. The specific function of the phase interpolator 336 is illustrated by the timing diagram shown in fig. 5. First, the phase interpolator 336 is configured to receive a first working clock, generate a second intermediate clock according to a preset phase difference and a second control signal, where the second phase difference between the first working clock and the second intermediate clock is a preset fixed value, and the second phase difference is an alignment window in the diagram. The phase difference can also be understood as the phase difference between two adjacent rising edges of the first operating clock and the second intermediate clock. Next, the phase detector 332 detects the phases of the first operating clock, the second intermediate clock, and the input data clock to determine the phase relationship among the three clocks.

Taking fig. 5(a) as an example, the phase detector 332 may sample the first operating clock and the second intermediate clock, i.e., phase detection, with the rising edge of the input data clock to determine the phase relationship between the three clocks. If the sample value is 2 'b 10 (two-bit binary number, low 0 indicates that the sample value of the second intermediate clock is 0, and high 1 indicates that the sample value of the first operating clock is 1), that is, when the input data clock is at the rising edge, the first operating clock is at high level (1), and the second intermediate clock is at low level (0), that is, the case of the sample value of 2' b10 corresponds to the input data clock being in the alignment window, and the phase of the input data clock is ahead of the phase of the first operating clock and behind the phase of the second intermediate clock. The phase detector 332 filters the sampling result through the digital filter 334, and outputs the result to the phase interpolator 336 as a second control signal, so that the phase interpolator 336 can determine whether the input data clock is in the alignment window, i.e., between the first operating clock and the second intermediate clock, according to the second control signal.

In fig. 5(b), the input data clock is offset from the alignment window by a phase that lags the phase of the first operating clock and lags the phase of the second intermediate clock, when the rising edge of the input data clock has a sample value of 2' b 00. After receiving the second control signal (i.e., including the sample value 2 'b 00 generated by the phase detector 332) generated by the digital filter 334, the phase interpolator 336 adjusts the phase of the first operating clock by using a phase interpolation method, and also adjusts the phase of the second intermediate clock, so that the input data clock is within the alignment window formed after adjustment, i.e., the adjusted sample value becomes 2' b10 again.

In FIG. 5(c), the input data clock is also offset from the alignment window, with the phase of the input data clock leading the phase of the first operating clock and leading the phase of the second intermediate clock, when the rising edge of the input data clock has a sample value of 2 'b 11 or 2' b 01. Taking the sample value 2 ' b11 as an example, after receiving the second control signal (i.e., including the sample value 2 ' b11 generated by the phase detector 332) generated by the digital filter 334, the phase interpolator 336 adjusts the phase of the first operating clock by using a phase interpolation method, and also adjusts the phase of the second intermediate clock, so that the input data clock is within the alignment window formed after adjustment, that is, the adjusted sample value becomes 2 ' b10 again.

When the SRIS function is turned on in the high-speed serial link, the input clock signal carries SSC information, i.e., low-frequency jitter, and the phase of the input clock signal is always periodically changed, i.e., periodically drifted within a certain range. The phase interpolator 336 adjusts the phase of the first operating clock according to the period of the phase change of the input data clock, and the adjusted period is the period of the phase change of the input data clock, i.e., the SSC change period. Therefore, the phase of the output data clock (i.e. the adjusted first working clock) always changes along with the phase of the input data clock, thereby achieving the purposes of keeping low-frequency jitter and filtering high-frequency jitter.

In one embodiment, the phase interpolator 336 adjusts the first operating clock and the second intermediate clock such that the rising edge of the input data clock is always at the center of the alignment window, i.e., the second intermediate clock is out of phase with the input data clock by the same amount as the input data clock and the first operating clock. Thus, when the alignment window is small, the first operating clock generated by phase interpolator 336 can be better phase aligned with the input data clock.

One specific embodiment of the synchronization circuit 340 is shown in fig. 6. The synchronization circuit 340 includes a first sub-synchronization circuit 342 and a second sub-synchronization circuit 344, wherein the first sub-synchronization circuit 342 is configured to perform a first synchronization on the received input data according to the input data clock to obtain first temporary data; the second sub-synchronization circuit 344 is configured to perform a second synchronization on the first temporary data according to the first working clock (i.e., the output data clock) to obtain the synchronized data. The two clocks are used for carrying out two times of synchronous processing on the input data respectively, so that the synchronous data can be transmitted at the frequency of the output data clock, the metastable state can be prevented from occurring, and the retimer 300 is prevented from being influenced by the propagation of the metastable state.

In one embodiment, the first sub-synchronization circuit 342 and the second sub-synchronization circuit 344 in the synchronization circuit 340 are both registers, and the clock used by the first sub-synchronization circuit 342 is the input data clock, and the clock used by the second sub-synchronization circuit for operation is the first operation clock (i.e., the output data clock). The register may include a plurality of D flip-flops connected in parallel. From the two clocks, it is ensured that the second subsynchronous circuit 344 can sample the data correctly.

It should be noted that any one or more of the above-described phase alignment circuit 330, synchronization circuit 340, and clock recovery circuit 312, which are included in retimer 300 in this application, may also be used to implement other circuits or scenarios of cross-clock domain processing, and that retimer 300 in this application is merely an example of one scenario. In addition, the input data and the synchronization data in the embodiment of the present application may be parallel data or serial data. For example, an embodiment of the present application further provides a clock domain crossing processing circuit, which includes the phase alignment circuit 330, the synchronization circuit 340, and the clock recovery circuit 312, where the input data and the generated synchronization data received by the clock domain crossing processing circuit may be both parallel data and also both serial data.

Retimer 300, shown in fig. 7, is a more specific embodiment. Retimer 300 of fig. 7 further includes an equalizer 316, a second clock circuit 318, a data processing circuit 350, and a data selector 360. The Equalizer 316 is configured to perform equalization processing, such as Continuous Time Linear Equalizer (CTLE), on the serial data received by the receiving circuit 310, so as to improve the performance of an Eye Diagram (Eye Diagram) of the data receiving circuit 310 in a high-speed serial link with a large transmission loss, and output the equalized serial data to the clock recovery circuit 312. Second clock circuit 318 is used to provide a second operating clock to clock recovery circuit 312 based on the reference clock of retimer 300.

The first device 210 relays the data through the retimer 300 and transmits the relayed data to the second device 220. In one embodiment, first device 210 and retimer 300 share a common reference clock, and the reference clock of second device 220 is independent of the common reference clock; in one embodiment, second device 220 and retimer 300 share the same reference clock, and the reference clock of first device 210 is independent of the shared reference clock; in another embodiment, the first device 210, the second device 220, and the retimer 300 each use an independent reference clock.

The data processing circuit 350 is used for encoding and decoding, scrambling and descrambling, buffering, synchronizing and the like of data. The data processing circuit 350 may selectively perform decoding, descrambling, synchronization, scrambling, encoding, and the like on the received data, and the order of the above-described plurality of processes may be variable. For example, the received data may be sequentially subjected to decoding, descrambling, synchronization, scrambling, and encoding processing, may be sequentially subjected to decoding, synchronization, and encoding processing, or may be sequentially subjected to descrambling, synchronization, and scrambling processing. One particular implementation of data processing circuit 350 is shown in fig. 8. Specifically, the data processing circuit 350 includes a decoder (De-decoder) 351, a descrambler circuit (De-Scramber) 352, an Elastic Buffer (Elastic Buffer)353, a Link Training and State Machine (LTSSM) 354, a Scrambler circuit (Scramber) 355, and an Encoder (Encode) 356. The decoder 351 is configured to perform aligned decoding on the received data, for example, find a feature word in the received data, and remove a synchronization header in the data according to the feature word. The descrambler circuit 352 is used to descramble data output from the decoder 351. The elastic buffer 353 is used to buffer the data output by the descrambling circuit 352 and output the buffered data to the link training state machine 354, and the elastic buffer 353 is a buffer with a variable data buffer amount, and the data buffer amount is determined by the reference clock of the retimer 300. The link training state machine 354 is configured to receive data output by the elastic buffer 353 and train a link. For example, before a link using the PCIe interface is operating properly, the link needs to be trained by the link training state machine 354 to initialize the link and configure the link information. Upon completion of link training and normal operation, the data generated by the elastic buffer 353 can be output directly to the scrambling circuit 355 without going through the link training state machine 354. Scrambling circuit 355 is used to scramble the data output by link training state machine 354, where the scrambling may be performed in a manner corresponding to descrambling. The decoder 356 is configured to encode the scrambled data and output the encoded data.

The data selector 360 is configured to simultaneously receive the data generated by the clock recovery circuit 312 and the data generated by the data processing circuit 350, and select one of the two paths of data to output to the synchronization circuit 340. In one embodiment, the data selector 360 may select to output the data generated by the clock recovery circuit 312 or the data generated by the data processing circuit 350 through a control signal, which may be configured through a register. Since the data selector 360 has a function of selecting one of two data paths, parallel data can be transmitted from the data receiving circuit 310 to the data transmitting circuit 320 through two paths. First, the parallel data is output from the clock recovery circuit 312 to the data processing circuit 350, and then input from the data processing circuit 350 to the data transmission circuit 320 via the data selector 360. Under a specific transmission protocol, the parallel data is subjected to encoding and decoding, scrambling and descrambling, and the like in the data processing circuit 350. Secondly, parallel data is directly output from the clock recovery circuit 312, passes through the data selector 360 and is input to the data transmission circuit 320, without any data processing, and this BSF (Bit Stream forwarding) scheme can reduce the delay caused by the data passing through the retimer 300 to the maximum. Retimer 300 may be controlled to switch between the two modes described above by adjusting the control signal of data selector 360.

Fig. 9 shows a multi-channel retimer 1000 according to an embodiment of the present application, where the retimer 1000 includes an upstream retiming circuit 1010 and a downstream retiming circuit 1020. The uplink retiming circuit 1010 is used to relay and filter the multiple serial signals on the uplink high-speed serial transmission link from the first device 210 to the second device 220, and the downlink retiming circuit 1020 is used to relay and filter the multiple serial signals on the downlink high-speed serial transmission link from the second device 220 to the first device 210. It should be noted that the above concepts of up and down are relative. The circuit structure of retimer 1000 is illustrated by taking 4 uplink channels and 4 downlink channels as an example, but the present application does not limit the number of uplink channels and downlink channels in retimer 1000. Specifically, the upstream retiming circuit 1010 includes 4 upstream lanes, wherein each upstream lane includes a data receiving circuit, a data processing circuit, a data selector, and a data transmitting circuit, and the data flow direction is from the first device 210 to the second device 220; the downstream retiming circuit 1020 also includes 4 downstream channels, where each downstream channel includes a data receiving circuit, a data processing circuit, a data selector 360, and a data transmitting circuit, and the data flow direction of the downstream channel is opposite to that of the upstream retiming circuit 1010, from the second device 220 to the first device 210. Similar to the retimer 300, for each of the up lanes or the down lanes, serial data is converted into parallel data by the data receiving circuit n, data is processed by the data processing circuit n and output to the data selector 360, or directly output to the data selector 360 without the data processing circuit n, and finally, clock domain crossing synchronization is performed by the data transmitting circuit n and the synchronized parallel data is converted into serial data. In retimer 1000, n may be 1,2, …, 8.

The data receiving circuit 1, the data receiving circuit 2, the data receiving circuit 3, the data receiving circuit 4, the data receiving circuit 5, the data receiving circuit 6, the data receiving circuit 7, and the data receiving circuit 8 in the retimer 1000 shown in fig. 9 may include some or all of the circuits in the data receiving circuit 310 provided in the embodiment of the present application, and some of the circuits in the common data receiving circuit 310. The data transmission circuit 1, the data transmission circuit 2, the data transmission circuit 3, the data transmission circuit 4, the data transmission circuit 5, the data transmission circuit 6, the data transmission circuit 7, and the data transmission circuit 8 in the retimer 1000 may include some or all of the data transmission circuit 320 provided in the embodiment of the present application, and some of the data transmission circuit 320 may be shared.

In one embodiment, 4 data receiving circuits in the upstream retiming circuit 1010 may share one clock processing circuit 1, and 4 data receiving circuits in the downstream retiming circuit 1020 may share one clock processing circuit 2, and each of the clock processing circuits 1 and 2 may be the second clock circuit 318 in this embodiment. Recovering 4 paths of parallel data in the uplink retiming circuit 1010 through a clock processing circuit 1 to respectively output 4 paths of clock signals, and selecting one path of clock signal as an input clock signal to be output to the synchronous circuit; downlink retiming circuit 1020 works similarly.

In one embodiment, 4 data transmit circuits in the upstream retiming circuit 1010 may share one phase alignment circuit 330, and 4 data receive circuits in the downstream retiming circuit 1020 may share one phase alignment circuit 330. Each data transmission circuit in the upstream retiming circuit 1010 includes a synchronization circuit 340, and each data transmission circuit in the downstream retiming circuit 1010 also includes a synchronization circuit 340 to synchronize the input data to be synchronized in each data transmission circuit. In addition, the data processing circuit 1, the data processing circuit 2, the data processing circuit 3, the data processing circuit 4, the data processing circuit 5, the data processing circuit 6, the data processing circuit 7, and the data processing circuit 8 in the retimer 1000 may be the data processing circuit 320 provided in the embodiment of the present application.

In the multi-channel retimer 1000, the multiple channels share a clock processing circuit, a synchronization circuit 340 and a phase alignment circuit 330, so that the retimer 1000 further reduces the required buffer resources while ensuring low latency, thereby reducing the hardware area and power consumption of the retimer 1000 and improving the performance of the retimer 1000.

The specific architecture of multi-channel retimer 1000 is illustrated with a specific example. The retimer is used for relaying N paths of input data in the transmission link. The retimer includes a phase alignment circuit and N synchronization circuits (N is greater than or equal to 1 and N is a positive integer), where the phase alignment circuit is configured to adjust a phase of a first working clock according to a first control signal to align phases of the two clocks, and output an input data clock and the adjusted first working clock to the N synchronization circuits, so that the N synchronization circuits may perform clock domain crossing synchronization on N input data according to the two clocks to generate N synchronization data, that is, synchronize N input data in a clock domain of the input data clock to a clock domain of an output data clock. The frequency of the first working clock is equal to the frequency of the input data clock, the first working clock is the working clock of the retimer, or the same reference clock is used with the retimer, the input data clock is one of N recovered clock clocks recovered from N paths of input data, for example, the N recovered data clocks are recovered from N paths of input data through a clock recovery circuit, and one of the recovered clocks is selected as the input data clock. The first control signal is also one of N control signals recovered according to N paths of input data, and the first control signal includes phase change information of the input data clock.

The phase alignment circuit comprises a phase discriminator, a digital filter and a phase interpolator, wherein the phase discriminator is used for discriminating an input data clock and an output data clock, the digital filter is used for filtering and jittering a phase discrimination result and a first control signal and outputting a filtered and jittered result as a second control signal, and the phase interpolator is used for adjusting the phase of a first working clock according to the second control signal, so that the phases of the first working clock and the input data clock are aligned, and the adjusted first working clock is output to a synchronous circuit as the output data clock.

The phase interpolator adjusts the phases of the first operating clock and the second intermediate clock such that the phase difference between the first operating clock and the input data clock is equal to the phase difference between the input data clock and the second intermediate clock.

The phase interpolator is further configured to: generating a second intermediate clock according to the first working clock, wherein the phase difference between the first working clock and the second intermediate clock is a preset phase difference; and adjusting the phases of the first working clock and the second intermediate clock according to the second control signal, so that the phase of the input data clock is ahead of the phase of the first working clock and behind the phase of the second intermediate clock. The phase detector is further configured to perform phase detection on the input data clock, the output data clock (i.e., the adjusted first working clock) and the second intermediate clock, so as to determine a phase relationship among the three clocks and output a phase detection result.

The phase interpolator is further configured to: when the phase of the input data clock is ahead of the phase of the first operating clock and behind the phase of the second intermediate clock, the second control signal is in a first state (e.g., binary number 10) to instruct the phase interpolator to maintain the phases of the first operating clock and the second intermediate clock; when the phase of the input data clock lags the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is in a second state (for example, binary number 00) to instruct the phase interpolator to adjust the phase, so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock; when the phase of the input data clock leads the phase of the first operating clock and leads the phase of the second intermediate clock, the second control signal is in a third state (e.g., binary number 01) to instruct the phase interpolator to adjust the phase such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

Each of the N synchronization circuits includes a first sub-synchronization circuit and a second sub-synchronization circuit, wherein the first sub-synchronization circuit is configured to synchronize one of the N input data according to an input data clock and output a result to the second sub-synchronization circuit; and the second sub-synchronous circuit synchronizes the result according to the first working clock to obtain one path of synchronous data in the synchronous data.

The first sub-synchronous circuit and the second sub-synchronous circuit are registers, and the two sub-synchronous circuits synchronize input data through an input data clock and a first working clock respectively.

The retimer further includes a first clock circuit for providing the first operating clock to the phase alignment circuit.

The digital filter filters the jitter of the first control signal and the phase discrimination result into high-frequency jitter, wherein the filtered first control signal comprises phase change information corresponding to low-frequency jitter of the input data clock.

The phase change information includes independent clock spread spectrum information, independent clock non-spread spectrum information or homologous clock information.

The retimer further includes N clock recovery circuits, which are respectively driven by the first operating clock of the retimer, recover the received input data to obtain the N recovered data clocks and N control signals, and output the input data, the N control signals, and the N recovered data clocks.

The N-way input data is N-way serial input data, and the retimer further includes N serial-parallel circuits, wherein the N serial-parallel circuits are configured to respectively perform serial-parallel conversion on the N-way input data, and output a converted result (i.e., N-way parallel data) to the N synchronization circuits.

The retimer further includes N parallel-to-serial circuits, and the N paths of synchronous data are N paths of parallel data, where the N parallel-to-serial circuits are configured to perform parallel-to-serial conversion on the N paths of synchronous data, respectively, and output a converted result.

The retimer further comprises N data processing circuits and N data selectors, wherein input ends of the N data processing circuits are respectively coupled with output ends of the N clock recovery circuits, output ends of the N data processing circuits are respectively coupled with input ends of the N data selectors, and the N data processing circuits are used for respectively decoding, descrambling, synchronizing, scrambling and encoding N paths of received input data; for each of the data processing circuit, the clock recovery circuit and the data selector coupled to each other, two input terminals of the data selector are coupled to an output terminal of the clock recovery circuit and an output terminal of the data processing circuit, respectively, and an output terminal of the data selector is coupled to an output terminal of the synchronization circuit. The data selector may be controlled by an additional control signal to select one of the two data signals received at the two input terminals as an output.

The sending end sends input data to the retimer and the synchronized data is output to the receiving end, where the following three conditions exist: firstly, the sending end and the retimer share one reference clock, and a clock used by the receiving end is independent of the shared reference clock; secondly, the receiving end and the retimer share one reference clock, and the reference clock of the transmitting end is independent of the shared reference clock; and thirdly, the transmitting end, the receiving end and the retimer share one reference clock.

The retimer is a multichannel retimer, where N is greater than or equal to 2 and is a positive integer.

The retimer in the embodiment of the present application may be a retimer chip for repeating data signals on a high-speed serial transmission link and filtering jitter. The retimer chip may be an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or other types of Integrated circuits. The retimer chip includes any of the retimers provided herein, wherein the circuitry in the retimer is integrated on a wafer (die).

Embodiments of the present application also provide a retimer device, including one or more of the retimer chips described above. In one embodiment, the one or more retimer chips are independently packaged and disposed on a PCB (Printed Circuit Board); in one embodiment, the one or more retimer chips may also be independently packaged and separately disposed on a plurality of PCBs, and communicate through connection ports or data connection lines between the PCBs; in another embodiment, the plurality of retimer chips may also be packaged in a package structure and disposed on the PCB.

Claims

A cross-clock-domain processing circuit for cross-clock-domain processing of received input data, the cross-clock-domain processing circuit comprising a phase alignment circuit and a synchronization circuit, wherein:

the phase alignment circuit is configured to receive an input data clock and a first working clock, adjust a phase of the first working clock according to a first control signal, output the phase-adjusted first working clock to the synchronization circuit as an output data clock, align a phase of the output data clock with a phase of the input data clock, where the input data clock is a clock recovered according to the input data, the first working clock is a working clock of the clock domain crossing processing circuit, a frequency of the first working clock is equal to a frequency of the input data clock, the first control signal is a control signal recovered according to the input data, and the first control signal includes phase change information of the input data clock;

the synchronization circuit is configured to perform clock domain crossing synchronization on the input data according to the input data clock and the output data clock to generate synchronization data, where the synchronization data is in a clock domain of the output data clock.
The cross-clock-domain processing circuit of claim 1, wherein the phase alignment circuit comprises a phase detector, a digital filter, and a phase interpolator, wherein:

the phase discriminator is used for discriminating the phase of the input data clock and the output data clock and outputting a phase discrimination result;

the digital filter is used for filtering jitter of the phase discrimination result and the first control signal and outputting the filtered jitter result to the phase interpolator as a second control signal;

the phase interpolator is configured to adjust a phase of the first working clock according to the second control signal, so that the phase of the first working clock is aligned with a phase of the input data clock, and output the phase-adjusted first working clock to the synchronization circuit and the phase discriminator as the output data clock.
The cross-clock-domain processing circuit of claim 2, wherein the phase interpolator is further to:

generating a second intermediate clock according to the first working clock, wherein the phase difference between the first working clock and the second intermediate clock is a preset phase difference;

adjusting phases of the first operating clock and the second intermediate clock according to the second control signal such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

The phase detector is further to:

performing phase discrimination on the output data clock, the second intermediate clock and the input data clock, and determining a phase relationship among the output data clock, the second intermediate clock and the input data clock to output the phase discrimination result.
The cross-clock-domain processing circuit of claim 3, wherein the phase interpolator is further to:

the second control signal is for instructing the phase interpolator to hold the phases of the first operating clock and the second intermediate clock when the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock;

when the phase of the input data clock lags the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is used for instructing the phase interpolator to adjust the phases of the first working clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock;

when the phase of the input data clock leads the phase of the first operating clock and leads the phase of the second intermediate clock, the second control signal is in a state for instructing the phase interpolator to adjust the phases of the first operating clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.
The cross-clock-domain processing circuit of any of claims 2 to 4, wherein the digital filter is configured to filter jitter of the first control signal and the phase detection result to a high frequency jitter, wherein the filtered first control signal includes phase change information corresponding to a low frequency jitter of the input data clock.
The cross-clock domain processing circuit of claim 5, wherein the phase change information comprises independent clock spread spectrum information, independent clock non-spread spectrum information, or homologous clock information.
The cross-clock domain processing circuit of any of claims 1 to 6, further comprising a first clock circuit to provide the first operating clock to the phase alignment circuit.
The cross-clock domain processing circuit of claims 1-7, further comprising a clock recovery circuit, wherein:

the clock recovery circuit is configured to receive the input data, recover a clock in the input data to obtain the input data clock and the first control signal, and output the input data, the input data clock, and the first control signal.
The cross-clock-domain processing circuit of any of claims 1 to 8, wherein the synchronization circuit comprises a first sub-synchronization circuit and a second sub-synchronization circuit, wherein:

the first sub-synchronization circuit is used for synchronizing the input data according to the input data clock to obtain first temporary data;

the second sub-synchronization circuit is used for synchronizing the first temporary data according to the output data clock to obtain the synchronous data.
The cross-clock-domain processing circuit of claim 9, wherein the first sub-synchronization circuit and the second sub-synchronization circuit are registers, wherein the first operating clock of the first sub-synchronization circuit is the input data clock and the first operating clock of the second sub-synchronization circuit is the output data clock.
The cross-clock-domain processing circuit of any of claims 1 to 10, wherein the input data is serial data, wherein:

the clock domain crossing processing circuit further comprises a serial-to-parallel circuit, and the serial-to-parallel circuit is used for performing serial-to-parallel conversion on the input data and outputting the converted input data to the synchronous circuit.
A retimer for relaying N input data in a transmission link, comprising: the circuit comprises a phase alignment circuit and N synchronous circuits, wherein N is more than or equal to 1 and is a positive integer, wherein:

the phase alignment circuit is used for receiving an input data clock and a first working clock, adjusting the phase of the first working clock according to a first control signal, outputting the first working clock after phase adjustment to the N synchronous circuits as an output data clock, the phase of the output data clock is aligned with the phase of the input data clock, the input data clock is one of N recovered data clocks recovered from the N paths of input data, the first working clock is a working clock of the retimer, the frequency of the first working clock is equal to the frequency of the input data clock, the first control signal is one of N control signals recovered according to the N paths of input data, and the first control signal comprises phase change information of the input data clock;

each of the N synchronization circuits is configured to perform clock domain crossing synchronization on each of the N input data according to the input data clock and the output data clock to generate one of N synchronization data, where the N synchronization data is in a clock domain of the output data clock.
The retimer of claim 12, wherein the phase alignment circuit comprises a phase detector, a digital filter, and a phase interpolator, wherein:

the phase discriminator is used for discriminating the phase of the input data clock and the output data clock and outputting a phase discrimination result;

the digital filter is used for filtering jitter of the phase discrimination result and the first control signal and outputting the filtered jitter result to the phase interpolator as a second control signal;

the phase interpolator is configured to adjust a phase of the first working clock according to the second control signal, so that the phase of the first working clock is aligned with a phase of the input data clock, and output the phase-adjusted first working clock to the N synchronization circuits and the phase discriminator as the output data clock.
The retimer of claim 13, wherein the phase interpolator is further to:

generating a second intermediate clock according to the first working clock, wherein the phase difference between the first working clock and the second intermediate clock is a preset phase difference;

adjusting phases of the first operating clock and the second intermediate clock according to the second control signal such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

The phase detector is further to:

performing phase discrimination on the output data clock, the second intermediate clock and the input data clock, and determining a phase relationship among the output data clock, the second intermediate clock and the input data clock to output the phase discrimination result.
The retimer of claim 14, wherein the phase interpolator is further to:

the second control signal is for instructing the phase interpolator to hold the phases of the first operating clock and the second intermediate clock when the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock;

when the phase of the input data clock lags the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is used for instructing the phase interpolator to adjust the phases of the first working clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock;

when the phase of the input data clock leads the phase of the first operating clock and leads the phase of the second intermediate clock, the second control signal is used for instructing the phase interpolator to adjust the phases of the first operating clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.
The retimer of any of claims 13 to 15, wherein filtering of the first control signal and the phase detection result by the digital filter is high frequency filtering, wherein the filtered first control signal comprises phase change information corresponding to low frequency jitter of the input data clock.
The retimer of claim 16, wherein the phase change information comprises independent clock spread spectrum information, independent clock non-spread spectrum information, or homologous clock information.
The retimer of any of claims 12 to 17, further comprising a first clock circuit to provide the first operating clock to the phase alignment circuit.
The retimer of claims 12 to 18, further comprising N clock recovery circuits, wherein:

the N clock recovery circuits are configured to receive the N input data, recover clocks in the N input data, obtain the N recovered data clocks and the N first control signals, and output the N input data, the N recovered data clocks, and the N control signals.
The retimer of any of claims 12 to 19, wherein the synchronization circuit comprises a first subsynchronization circuit and a second subsynchronization circuit, wherein:

the first sub-synchronization circuit is used for synchronizing the input data according to the input data clock to obtain first temporary data;

the second sub-synchronization circuit is used for synchronizing the first temporary data according to the output data clock to obtain the synchronous data.
The retimer of claim 20, wherein the first subsynchronous circuit and the second subsynchronous circuit are registers, wherein the first operating clock of the first subsynchronous circuit is the input data clock, and wherein the first operating clock of the second subsynchronous circuit is the output data clock.
The retimer of any of claims 12 to 21, wherein the N input data are N serial data, wherein:

the retimer further includes N serial-parallel circuits, and is characterized in that the N serial-parallel circuits are configured to respectively perform serial-parallel conversion on the N paths of input data, and respectively output the converted N paths of input data to the N synchronization circuits.
The retimer of any of claims 12 to 22, wherein the N ways of synchronization data are N ways of parallel data, wherein:

the retimer further includes N parallel-to-serial circuits, and is characterized in that the N parallel-to-serial circuits are configured to convert the N paths of synchronous data into N paths of serial output data, and output the converted N paths of serial output data.
The retimer of any of claims 19 to 23, further comprising N data processing circuits and N data selectors, wherein:

the input ends of the N data processing circuits are respectively coupled with the output ends of the N clock recovery circuits, the output ends of the N data processing circuits are respectively coupled with the input ends of the N data selectors, and the N data processing circuits are used for respectively decoding, descrambling, synchronizing, scrambling and encoding the received N paths of input data;

for each of the data processing circuits, the clock recovery circuits, and the data selector coupled to each other, wherein:

two input ends of the data selector are respectively coupled with the output end of the clock recovery circuit and the output end of the data processing circuit, and the output end of the data selector is coupled with the output end of the synchronous circuit.
The retimer of any of claims 12 to 24, wherein the retimer is a multi-channel retimer, wherein N ≧ 2, and N is a positive integer.