CN107678488A - A kind of circuit of cross clock domain event transmission - Google Patents
A kind of circuit of cross clock domain event transmission Download PDFInfo
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- CN107678488A CN107678488A CN201711177343.5A CN201711177343A CN107678488A CN 107678488 A CN107678488 A CN 107678488A CN 201711177343 A CN201711177343 A CN 201711177343A CN 107678488 A CN107678488 A CN 107678488A
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- 101100243022 Mus musculus Pcnt gene Proteins 0.000 claims description 25
- 230000008929 regeneration Effects 0.000 claims description 21
- 238000011069 regeneration method Methods 0.000 claims description 21
- 238000005070 sampling Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
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- 101100421142 Mus musculus Selenon gene Proteins 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000012790 confirmation Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000003750 conditioning effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Abstract
A kind of circuit of cross clock domain event transmission, for the event transmission between different clock-domains in digital circuit field.The intensive event of burst is handled by the counting to event, what the event for making to generate again by frequency dividing can be errorless is delivered to another clock zone, reproduces event by the sample circuit in destination clock-domain；When there is data to be transmitted together with event, it can synchronously recover outgoing event and corresponding data.The program causes cross clock domain to transmit complete unilateralization, is not required to shake hands or bi-directional；By being appropriately arranged with, the program is adapted to the optional frequency relation and phase relation of the clock of two clock zones, applied widely.
Description
Technical field
This circuit is related to digital circuit field, and cross clock domain transmits event, signal, number especially in FPGA and ASIC
According to.
Background technology
In digital display circuit, including FPGA and ASIC, generally there are multiple clocks, it is necessary to transmit thing between different clock-domains
Part and data.
In order to reliably transmit, it is desirable to eliminate metastable state, without loss event；If also synchronous while the event of transmission pass
Pass corresponding data, then also require that event and data can still keep synchronous after transmitting, so as to facilitate and accurately by follow-up
Circuit receives.
Currently for different situations, there are a few class processing methods in the industry：It is delivered to when from the clock zone that frequency is f_clkA
When frequency is f_clkB clock zone,
（1）If f_clkA is much smaller than f_clkB, directly the signal from clkA clock zones can be sampled with clkB.
（2）If f_clkA is more than f_clkB or the two is more or less the same, by the signal exhibition from clkA clock zones
Width, then sampled by clkB.
The above method is mainly for elimination metastable state；And to accomplish not losing event, and ensure event and data
Synchronization, typically with the method shaken hands, i.e. first confirm that clkB clock zones are to receive before clkA transmission events and data
's；ClkB clock zones issue one confirmation signal of clkA clock zones again after the signal of clkA clock zones is received.This mode
Sudden intensive event can not be handled, shaking hands between two other clock zone also makes the reduction of event transmission efficiency.
The content of the invention
This programme does not lose event mainly in above-mentioned requirements, and ensures the synchronization of event and data.Mainly change
Enter a little that i.e. beneficial effect is：
（1）For sudden intensive event（Overall sparse, the short time is intensive）, event will not be lost, is all delivered to another
Clock zone；
（2）Whether individually transmit event, or transmit event and corresponding data simultaneously, be all unilateralization, it is not necessary to shake hands or
Confirmation signal, help to reduce delay, increase handling capacity；
（3）It is adapted to the optional frequency relation and phase relation of the clock of two clock zones.
This programme main thought is：For above-mentioned（1）（2）（3）Point, when being delivered to B domains from A domains：
（1）To event count in A domains, particularly when happen suddenly intensive event when, can record and arrive but not yet passed
Event total degree, pass one by one again afterwards；If also transmitting data while the event of transmission, also cached in A domains
Data, and ensure each event and the corresponding data syn-chronization outflow of the event.
（2）The representation of event is：It is pulse in A domains（For example often continue the high level of a clock cycle and represent one
Secondary event）, it is hopping edge to have a common boundary in AB（Rising edge or trailing edge represent event）, become reversion pulse again in B domains, so ensure each
Event has and only once transmitted；When ensureing that each event reaches B domains on circuit sequence, corresponding data（If）Also can
Effectively transmit.
（3）According to the relative size of two clocks clkA and clkB frequency, it is suitable to be set when event is generated in A domains
Frequency division counter value, the hopping edge interval long enough for the two expression events that are connected for ensureing to generate in A, can effectively be known by clkB
Not.
This programme content is as follows：
（Such as Fig. 1）A kind of circuit of cross clock domain event transmission, including two clock zones A and B, clock therein is respectively clkA
And clkB, it is characterised in that clock zone A includes event count maximum N, divide ratio K, event and overflows instruction ERR, event
Five p, data input d ports are inputted, and three regeneration of event count, event, data buffer storage units, clock zone B include
No data event output pout_0d, there are data event output pout_Wd, tri- ports of data output dout, and event to adopt
Two sample, data sampling units, wherein：
The event count maximum N is input port, and its value is positive integer, and it sets counts to existing event in A
The maximum allowed；
The divide ratio K is input port, and its value is positive integer, its set event regeneration unit generated it is two neighboring
The minimum interval of event is K times of clkA cycles；
It is output port that the event, which overflows instruction ERR, indicates that whether existing total number of events is more than N in current A；
The event input p is input port, and its each duration all represents an event for the pulse in a clkA cycle
Input；
The data input d is input port, and its bit wide is W, in the case where only transmitting event and not transmitting data, the port
Data are meaningless, and in the case of transmitting event and data at the same time, the pulse of the data of the port and corresponding event on p appears in
In the same clkA cycles；
No data event output pout_0d be output port, its each duration for a clkB cycle pulse all
Represent an event output；
It is described that to have data event output pout_Wd be output port, its each duration for a clkB cycle pulse all
Represent an event output；
The data output dout is output port, and its bit wide is positive integer W, and the situation of data is not transmitted in only transmission event
Under, the data of the port are meaningless, in the case of transmitting event and data at the same time, the data of the port and phase on pout_Wd
The pulse of event is answered to appear in the same clkB cycles；
Described event count unit connectivity port N, ERR, p, it is also connected with the frequency division counter output gcnt of event regeneration unit, the list
Member is that the event for having arrived in A but being not yet delivered in B counts to existing event in A, is up to N, when beyond N
Set ERR；
Described event regeneration unit connectivity port K, p, the counting output pcnt of event count unit is also connected with, the unit will be each
The event that B is delivered to from A is converted to a hopping edge risen or fallen on the output Qp of the unit, two neighboring saltus step
The minimum interval on edge is K times of clkA cycles；
Described data buffer storage unit connectivity port d, p, are also connected with pcnt, gcnt, export and are simultaneously stored in d for Q0, the interior reception of the unit,
When representing the hopping edge of event on event regeneration unit generation Qp, data corresponding with the event are also appeared on Q0,
The data lasting shortest time is K times of clkA cycles；
The event sampling unit connects Qp, and the hopping edge that event is each represented on Qp is converted to a width as one by the unit
The pulse in individual clkB cycles, the pulse are output on port pout_0d and pout_Wd；
The data sampling unit connects Q0, and the unit is converted to Q0 the data synchronous with clkB, the data output to port
On dout.
As one of numerous embodiments, in a kind of circuit of cross clock domain event transmission：
The event count unit includes an event counter pcnt, and its counting rule is to be zeroed after system reset, rear end
The event pulse that often arrived on mouth p then counts increasing one, maximum count to N, is counted when gcnt is K-1 and subtracts one, most subtotal
Zero is counted to, if an event is arrived on p when count value is N, ERR set.（Counting rule refer to Fig. 2）
The event regeneration unit includes a frequency counter gcnt, a hopping edge control circuit, wherein：
The frequency counter is used to count the clock periodicity between the adjacent hopping edge of each two of unit generation, and it is counted
Rule is the rearmounted K-1 of system reset, if meeting condition (pcnt when count value is K-1<2 && p==1)||(pcnt>=2)
Then zero setting, counted in each cycle when count value is less than K-1 in clock clkA and increase one, count value is up to K-1；
The hopping edge control circuit includes combinational circuit and output register Qp, the combinational circuit control under, whenever gcnt=
=K-1 simultaneously meets condition (pcnt<2 && p==1)||(pcnt>=2) when, register Qp value can be overturn.（Counting rule can join
Fig. 3 is examined, circuit refers to Fig. 4）
The data buffer storage unit includes pcnt decoders, gcnt decoders, N level production lines, wherein：
The pcnt decoders to pcnt decode, generation N+1 selection signal sel0, sel1 ..., selN, as a result, ought
When pcnt is some value i, corresponding selection signal seli is 1, and other N number of selection signals are 0；
The gcnt decoders decode to gcnt, generate a selection signal, the signal is 1 when gcnt is equal to K-1, in gcnt
It is 0 during not equal to K-1；
The N level production lines, comprising N-1 levels, N-2 levels ..., the 0th grade, the output QN-1 of N-1 levels is connected to N-2
Level, the output QN-2 of N-2 levels be connected to N-3 levels ..., the 1st grade of output Q1 be connected to the 0th grade, the 0th grade of output company
It is connected to the output Q0 of the unit；
Every one-level of the N level production lines has identical structure, wherein i-stage connection input port p, d, is also connected with i-th of choosing
Signal seli, the output of i+1 selection signal seli+1, gcnt decoder are selected, the i-stage includes 5 alternative selectors
61 ~ 65 and W bit wides a register Qi, wherein seli be connected to the control terminal of selector 61, p is connected to selector 62 and 65
Control terminal, seli+1 are connected to the control terminal of selector 64, and gcnt decoders export the control terminal for being connected to selector 63, deposit
Device Qi outputs are connected to the 0 of selector 61 and 62 and select input, and d is connected to the 1 of selector 61 and 64 and selects input, selector 61
Output end be connected to the 1 of selector 62 and select input, the output end of selector 62 is connected to the 0 of selector 63 and selects input,
The output end of selector 63 is connected to register Qi input, and the output Qi+1 of i+1 level production line is connected to selector 64
Input is selected with the 0 of 65, the output end of selector 64 is connected to the 1 of selector 65 and selects input, and the output end of selector 65 connects
Select input in be connected to selector 63 1.（Refer to Fig. 5, Fig. 6）
The event sampling unit includes 4 grades of register R3 ~ R0 and 2 XOR gates, and wherein R3 input connection clock zone A is defeated
The Qp gone out, R3 output end connection R2 input, R2 output end connection R1 input, R1 output end connection R0's is defeated
Enter end, R2 and R1 output end is connected respectively to two inputs of an XOR gate, and the output end of the XOR gate is connected to defeated
Exit port pout_0d, R1 and R0 output end are connected respectively to two inputs of another XOR gate, the output of the XOR gate
End is connected to output port pout_Wd.（Refer to Fig. 7）
The data sampling unit includes the register DR1 and DR0 of 2 grades of W bit wides, and wherein DR1 input connection clock zone A is defeated
The Q0 gone out, DR1 output end connection DR0 input, DR0 output end are connected to output port dout.（Refer to Fig. 8）
When the value of the input port K shakes maximum of T aj, clkB by clkA clock cycle nominal value Ta, clkA clock cycle
Clock cycle nominal value Tb, clkB clock cycle shakes register holding in register settling time Tbsu, B in maximum of T bj, B
Time Tbh determines that in the case of only biography event, K value is minimum（Tb+Tbj+Tbsu+Tbh）Divided by（Ta-Taj）Gained
Business round up, in the case of transmitting event and data at the same time, K value is minimum（Tb*2+Tbj*2+Tbsu+Tbh）
Divided by（Ta-Taj）The business of gained rounds up；
The value of the input port N is determined by the total number of events M in a period of time of most intensive transmission on the p of port, in extreme feelings
In the case of the i.e. continuous input of condition, N values are minimum（M-M/K) round up.
A kind of method of cross clock domain event transmission, is related to two clock zones A and B, and clock therein is respectively clkA and clkB,
Event is delivered in B from A, it is characterised in that comprise the following steps：
（1）Set event count maximum N, divide ratio K：
Wherein K value shakes maximum of T aj, clkB clock cycle mark by clkA clock cycle nominal value Ta, clkA clock cycle
Register holding time Tbh is true in register settling time Tbsu, B in title value Tb, clkB clock cycle shake maximum of T bj, B
Fixed, in the case of only biography event, K value is minimum（Tb+Tbj+Tbsu+Tbh）Divided by（Ta-Taj）The business of gained is upward
Round, in the case of transmitting event and data at the same time, K value is minimum（Tb*2+Tbj*2+Tbsu+Tbh）Divided by（Ta-
Taj）The business of gained rounds up；
Wherein N value is determined by the total number of events M in a period of time of most intensive transmission on input port p, is in extreme case
In the case of continuous input, N values are minimum（M-M/K) round up；
（2）The counting and regeneration of event, the caching of data：
It is that the event for having arrived in A but being not yet delivered in B counts to existing event in A, i.e., is arrived when on the p of port
During one event, count and increase one, when event regeneration passes out an event to B, counting subtracts one, counts minimum 0, is up to
N, instruction ERR set is overflowed to event when beyond N；
Is returned to when there is ERR set（1）Step, recalculates and sets N values；
When still having event to be delivered in B during event count is not for 0 i.e. A, event in A is seriatim delivered in B, then is made trouble
K times of the interval minimum clkA clock cycle of part；
In the case where only transmitting event and not transmitting data, it is not necessary to data buffer storage, transmit the situation of event and data at the same time
Under, corresponding data receiver on port is entered data into while occurring each event on p and is stored in caching, when each event
When B input is appeared in after regeneration, data corresponding with the event are also output on B data input pin from caching, the number
According to K times that the lasting shortest time is the clkA clock cycle；
（3）The sampling of event and data：
With the clock clkB in B to transmitted from A come event and data sample, generated in the case of only transmission event
It is synchronized with clkB event output, the event output sum for being synchronized with clkB is generated in the case of transmitting event and data at the same time
According to output.
In a kind of method of cross clock domain event transmission, each incoming event is the duration to be on A input port p
The pulse of one clkA clock cycle, a hopping edge risen or fallen is converted to after being regenerated by event, is handled in B
It is pulse of the duration for a clkB clock cycle afterwards.
Brief description of the drawings:
Fig. 1 is allomeric function block diagram；
Fig. 2 is " event count " pcnt state transition diagrams;
Fig. 3 is frequency counter gcnt state transition diagrams in " event regeneration "；
Fig. 4 is " event regeneration " circuit；
Fig. 5 is " data buffer storage " circuit；
Fig. 6 be data buffer storage N level production lines in i-stage circuit diagram；
Fig. 7 is " event sampling " circuit diagram；
Fig. 8 is " data sampling " circuit diagram；
Fig. 9 is first specific embodiment（Only transmit event）；
Figure 10 is second specific embodiment（Transmission event and data）.
Illustrate the implementation of such scheme with two examples below.In both examples it is assumed that clkA frequencies are 100MHz
That is Ta=10ns, clkB frequency are that 50MHz is Tb=20ns, and the shake of the two is all 0.2ns, and register builds in clkB clock zones
It is 0.3ns, retention time 0.1ns between immediately.In the two examples, A areas incoming event p signal in reference picture 9 or 10,
The high level in 3 clkA cycles is shared, the high level in each cycle represents an event pulse, so the event totally 3 times to arrive.
For the first time and front and rear event has longer interval, so can regard the sparse situation of event as；Continuously arrive twice below,
The intensive situation of event can be regarded as.So the event number M of most intensive arrival is 2.
First example is only to transmit event.
（1）Determine N, K：
Calculate（Tb+Tbj+Tbsu+Tbh）/（Ta-Taj）=(20+0.2+0.3+0.1）/（10-0.2）=2.10, round up for
3, K=3 are set.Calculate（M-M/K)=（2-2/3)=2, round up as 2, N=2 are set.
Below with reference to the sequential of the circuit of Fig. 1 ~ 8, and Fig. 9：
（2）Event count regenerates with event：
It can be seen that because K=3, gcnt are K-1 from 0 to 2；Because N=2, pcnt when event is intensive most
The matter of fundamental importance is to 2.
3 incoming events are changed into 3 hopping edges on Qp, behind two hopping edges interval it is minimum, but still be no less than K
=3 times of clkA clock cycle.
（3）Sampling of the B areas to event：
By clkB sampling, eliminate after metastable state by XOR gate, recover 3 events, each width is clkB clocks week
Phase.
Wherein, due to the phase relation of clkA and clkB in diagram, R3 can go out at first and the 3rd event in B areas
Existing metastable state, accordingly, indefinite state occurs in R2 and R1, is represented with " x ".In R2 and R1, as x=0, XOR gate exports such as
Pout_0d (x=0) in Fig. 9;As x=1, XOR gate output such as pout_0d (x=1) in Fig. 9.As can be seen that in both of these case
Under, output is all 3 events（Pulse often continues a clkB cycle and just represents an event）, it is correct.Another feelings
Condition is at second event, and without generating metastable, output is also correct.
In terms of three cases above, the phase regardless of clkA and clkB, nothing more than occurring metastable state and occurring without Asia
Stable state, and output result is all correct.This proved aforementioned advantages thirdly in, be adapted to two clock zones
The random phase relationship of clock.
And pass through（1）In to N, K calculating, it is also ensured that aforementioned advantages thirdly in, be adapted to two
The optional frequency relation of the clock of clock zone.
For first point of aforementioned advantages, from the point of view of this 3 events, no matter sparse（First event）, or it is close
Collection（Second and third event）As long as correctly setting N, K, event would not be lost.
Second example is to transmit event and data simultaneously.
（1）Determine N, K：
Calculate（Tb*2+Tbj*2+Tbsu+Tbh）/（Ta-Taj）=(20*2+0.2*2+0.3+0.1）/（10-0.2）=4.16, to
On round as 5, K=5 are set.Calculate（M-M/K)=（2-2/3)=2, round up as 2, N=2 are set.
Below with reference to the sequential of the circuit of Fig. 1 ~ 8, and Figure 10：
（2）Event count and event regeneration, data buffer storage：
It can be seen that because K=5, gcnt are K-1 from 0 to 4；Because N=2, pcnt when event is intensive most
The matter of fundamental importance is to 2.
3 incoming events are changed into 3 hopping edges on Qp, behind two hopping edges interval it is minimum, but still be no less than K
=5 times of clkA clock cycle.
From fig. 10 it can be seen that 3 incoming events correspond to 3 clkA cycle high level on p, corresponding 3 data a,
B, c is synchronous with 3 high level occurs.When upper 3 hopping edges of Qp occur, 3 data are also synchronously appeared on Q0 successively.
（3）Sampling of the B areas to event：
By clkB sampling, eliminate after metastable state by XOR gate, recover 3 events, each duration is one
The clkB clock cycle.
Wherein, it is similar with first example, 3 events occur successively in B have metastable state, without metastable state, have it is metastable
The situation of state, outgoing event pout_Wd are correct.
In Figure 10, although also there is metastable state and indefinite state in DR1, DR0 in the sampling to data, in pout_Wd
When upper 3 events are effective, corresponding 3 data a, b, c are also stable and correctly.Subsequent conditioning circuit can be according to this 3 things
Part effectively reads corresponding data.
All be unilateralization when transmitting event and data from Fig. 9 and Figure 10, i.e. the signal only from A to B, not from B to A
Signal, it is seen that need not shake hands or confirmation signal, help to reduce delay, increase handling capacity.This has proved beneficial effect
Second point.
Claims (9)
1. a kind of circuit of cross clock domain event transmission, including two clock zones A and B, clock therein be respectively clkA and
ClkB, it is characterised in that it is defeated that clock zone A includes event count maximum N, divide ratio K, event spilling instruction ERR, event
Enter five p, data input d ports, and three regeneration of event count, event, data buffer storage units, clock zone B include nothing
Data event output pout_0d, have data event output pout_Wd, tri- ports of data output dout, and event sampling,
Two units of data sampling, wherein：
（1）The event count maximum N is input port, and its value is positive integer, and it sets counts to existing event in A
Several allowed maximums；
（2）The divide ratio K is input port, and its value is positive integer, its set event regeneration unit generated it is adjacent
The minimum interval of two events is K times of clkA cycles；
（3）It is output port that the event, which overflows instruction ERR, indicates that whether existing total number of events is more than N in current A；
（4）The event input p is input port, and its each duration all represents a thing for the pulse in a clkA cycle
Part inputs；
（5）The data input d is input port, and its bit wide is W, in the case where only transmitting event and not transmitting data, the end
The data of mouth are meaningless, and in the case of transmitting event and data at the same time, the pulse of the data of the port and corresponding event on p goes out
In the present same clkA cycles；
（6）The no data event output pout_0d is output port, and its each duration is the pulse in a clkB cycle
All represent an event output；
（7）It is described that to have data event output pout_Wd be output port, its each duration for a clkB cycle pulse
All represent an event output；
（8）The data output dout is output port, and its bit wide is positive integer W, and the feelings of data are not transmitted in only transmission event
Under condition, the data of the port are meaningless, in the case of transmitting event and data at the same time, in the data and pout_Wd of the port
The pulse of corresponding event was appeared in the same clkB cycles；
（9）Described event count unit connectivity port N, ERR, p, the frequency division counter output gcnt of event regeneration unit is also connected with,
The unit is that the event for having arrived in A but being not yet delivered in B counts to existing event in A, is up to N, when super
Set ERR when going out N；
（10）Described event regeneration unit connectivity port K, p, the counting output pcnt of event count unit is also connected with, the unit will
The event that B is each delivered to from A is converted to a hopping edge risen or fallen on the output Qp of the unit, two neighboring
The minimum interval of hopping edge is K times of clkA cycles；
（11）Described data buffer storage unit connectivity port d, p, are also connected with pcnt, gcnt, export and are simultaneously deposited for Q0, the interior reception of the unit
Enter d, when representing the hopping edge of event on event regeneration unit generation Qp, data corresponding with the event also appear in Q0
On, the data lasting shortest time is K times of clkA cycles；
（12）The event sampling unit connects Qp, and the hopping edge that event is each represented on Qp is converted to a width by the unit
For the pulse in a clkB cycle, the pulse is output on port pout_0d and pout_Wd；
（13）The data sampling unit connects Q0, and the unit is converted to Q0 the data synchronous with clkB, and the data output arrives
On the dout of port.
A kind of 2. circuit of cross clock domain event transmission according to claim 1, it is characterised in that the event count list
Member includes an event counter pcnt, and its counting rule is to be zeroed after system reset, rear port p on often arrive a thing
Part pulse then counts increasing one, maximum count to N, is counted when gcnt is K-1 and subtracts one, least count to zero, when count value is N
If when p on arrive an event, ERR set.
3. the circuit of a kind of cross clock domain event transmission according to claim 1, it is characterised in that the event regeneration is single
Member includes a frequency counter gcnt, a hopping edge control circuit, wherein：
（1）The frequency counter is used to count the clock periodicity between the adjacent hopping edge of each two of unit generation, its
Counting rule is the rearmounted K-1 of system reset, if meeting condition (pcnt when count value is K-1<2 && p==1)||(pcnt
>=2) then zero setting, counted in each cycle when count value is less than K-1 in clock clkA and increase one, count value is up to K-1；
（2）The hopping edge control circuit includes combinational circuit and output register Qp, under combinational circuit control, whenever
Gcnt==K-1 simultaneously meets condition (pcnt<2 && p==1)||(pcnt>=2) when, register Qp value can be overturn.
A kind of 4. circuit of cross clock domain event transmission according to claim 1, it is characterised in that the data buffer storage list
Member includes pcnt decoders, gcnt decoders, N level production lines, wherein：
（1）The pcnt decoders to pcnt decode, generation N+1 selection signal sel0, sel1 ..., selN, its result
It is that when pcnt is some value i, corresponding selection signal seli is 1, and other N number of selection signals are 0；
（2）The gcnt decoders decode to gcnt, generate a selection signal, and the signal is 1 when gcnt is equal to K-1,
Gcnt is 0 when being not equal to K-1；
（3）The N level production lines, comprising N-1 levels, N-2 levels ..., the 0th grade, the output QN-1 of N-1 levels is connected to
N-2 levels, the output QN-2 of N-2 levels be connected to N-3 levels ..., the 1st grade of output Q1 be connected to the 0th grade, the 0th grade defeated
Go out to be connected to the output Q0 of the unit；
（4）Every one-level of the N level production lines has identical structure, wherein i-stage connection input port p, d, is also connected with i-th
Selection signal seli, the output of i+1 selection signal seli+1, gcnt decoder, the i-stage include 5 alternatives and selected
Device 61 ~ 65 and W bit wides a register Qi, wherein seli are connected to the control terminal of selector 61, and p is connected to selector 62 and 65
Control terminal, seli+1 is connected to the control terminal of selector 64, and gcnt decoders export the control terminal for being connected to selector 63, post
Storage Qi outputs are connected to the 0 of selector 61 and 62 and select input, and what d was connected to selector 61 and 64 1 selects input, selector
61 output end is connected to the 1 of selector 62 and selects input, and the output end of selector 62 is connected to 0 choosing input of selector 63
End, the output end of selector 63 are connected to register Qi input, and the output Qi+1 of i+1 level production line is connected to selector
Input is selected in the 0 of 64 and 65, and the output end of selector 64 is connected to the 1 of selector 65 and selects input, the output end of selector 65
Select input in be connected to selector 63 1.
5. the circuit of a kind of cross clock domain event transmission according to claim 1, it is characterised in that the event sampling is single
Member includes 4 grades of register R3 ~ R0 and 2 XOR gates, the Qp of wherein R3 input connection clock zone A outputs, R3 output end
Connect R2 input, R2 output end connection R1 input, R1 output end connection R0 input, R2 and R1 output
End is connected respectively to two inputs of an XOR gate, the output end of the XOR gate be connected to output port pout_0d, R1 and
R0 output end is connected respectively to two inputs of another XOR gate, and the output end of the XOR gate is connected to output port
pout_Wd。
A kind of 6. circuit of cross clock domain event transmission according to claim 1, it is characterised in that the data sampling list
Member includes the register DR1 and DR0 of 2 grades of W bit wides, and wherein DR1 input connects the Q0 of clock zone A outputs, DR1 output end
DR0 input is connected, DR0 output end is connected to output port dout.
A kind of 7. circuit of cross clock domain event transmission according to claim 1, it is characterised in that：
（1）The value of the input port K shakes maximum of T aj, clkB by clkA clock cycle nominal value Ta, clkA clock cycle
Clock cycle nominal value Tb, clkB clock cycle shakes in maximum of T bj, B register in register settling time Tbsu, B and protected
Time Tbh determinations are held, in the case of only biography event, K value is minimum（Tb+Tbj+Tbsu+Tbh）Divided by（Ta-Taj）Institute
The business obtained rounds up, and in the case of transmitting event and data at the same time, K value is minimum（Tb*2+Tbj*2+Tbsu+
Tbh）Divided by（Ta-Taj）The business of gained rounds up；
（2）The value of the input port N is determined by the total number of events M in a period of time of most intensive transmission on the p of port, extreme
In the case of the i.e. continuous input of situation, N values are minimum（M-M/K) round up.
8. a kind of method of cross clock domain event transmission, be related to two clock zones A and B, clock therein be respectively clkA and
ClkB, event is delivered in B from A, it is characterised in that comprise the following steps：
（1）Set event count maximum N, divide ratio K：
Wherein K value shakes maximum of T aj, clkB clock cycle mark by clkA clock cycle nominal value Ta, clkA clock cycle
Register holding time Tbh is true in register settling time Tbsu, B in title value Tb, clkB clock cycle shake maximum of T bj, B
Fixed, in the case of only biography event, K value is minimum（Tb+Tbj+Tbsu+Tbh）Divided by（Ta-Taj）The business of gained is upward
Round, in the case of transmitting event and data at the same time, K value is minimum（Tb*2+Tbj*2+Tbsu+Tbh）Divided by（Ta-
Taj）The business of gained rounds up；
Wherein N value is determined by the total number of events M in a period of time of most intensive transmission on input port p, is in extreme case
In the case of continuous input, N values are minimum（M-M/K) round up；
（2）The counting and regeneration of event, the caching of data：
It is that the event for having arrived in A but being not yet delivered in B counts to existing event in A, i.e., is arrived when on the p of port
During one event, count and increase one, when event regeneration passes out an event to B, counting subtracts one, counts minimum 0, is up to
N, instruction ERR set is overflowed to event when beyond N；
Is returned to when there is ERR set（1）Step, recalculates and sets N values；
When still having event to be delivered in B during event count is not for 0 i.e. A, event in A is seriatim delivered in B, then is made trouble
K times of the interval minimum clkA clock cycle of part；
In the case where only transmitting event and not transmitting data, it is not necessary to data buffer storage, transmit the situation of event and data at the same time
Under, corresponding data receiver on port is entered data into while occurring each event on p and is stored in caching, when each event
When B input is appeared in after regeneration, data corresponding with the event are also output on B data input pin from caching, the number
According to K times that the lasting shortest time is the clkA clock cycle；
（3）The sampling of event and data：
With the clock clkB in B to transmitted from A come event and data sample, generated in the case of only transmission event
It is synchronized with clkB event output, the event output sum for being synchronized with clkB is generated in the case of transmitting event and data at the same time
According to output.
9. the method for a kind of cross clock domain event transmission according to claim 8, it is characterised in that each incoming event exists
It is pulse of the duration for a clkA clock cycle on A input port p, is converted to after being regenerated by event on one
The hopping edge for rising or declining, it is pulse of the duration for a clkB clock cycle after being handled in B.
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