WO2020133537A1

WO2020133537A1 - Clock domain crossing processing circuit

Info

Publication number: WO2020133537A1
Application number: PCT/CN2018/125876
Authority: WO
Inventors: 白玉晶; 刘旭辉
Original assignee: 华为技术有限公司
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2020-07-02
Also published as: CN112840571A; CN112840571B

Abstract

Provided is a clock domain crossing (CDC) processing circuit for processing data between asynchronous clock domains with low delay. The CDC circuit comprises a phase alignment circuit (330) and a synchronization circuit (340), wherein the phase alignment circuit (330) is configured to adjust the phase of a local working clock according to a control signal recovered from input data and containing the phase change information of an input data clock such that the working clock and the input data clock are phase aligned, and the input data clock and the working clock are used as clocks of the synchronization circuit to synchronize the input data. The phase of the local working clock is adjusted by the control signal recovered from the input data clock such that the input data clock and the adjusted working clock can synchronize the input data with a low delay, thereby lowering the delay of data passing through the CDC processing circuit.

Description

A cross-clock domain processing circuit

Technical field

This application relates to the field of digital circuits, and in particular to processing circuits that cross the clock domain.

Background technique

Serdes (SERializer/DESerializer, serializer/deserializer), as an important high-speed serial link physical layer technology, is widely used in various general-purpose I/O (Input and Output) interfaces, such as Interfaces such as PCIe (Peripheral Component Interface), Ethernet (Ethernet), and SATA (Serial Advanced Technology Attachment). When two devices are communicating, Serdes is used to convert multiple low-speed parallel data signals into high-speed serial data signals at the data sending end, and to re-convert high-speed serial data signals into multiple low-speed parallels at the receiving end after passing through the transmission medium Data signal. With the development of high-speed serial link technology, the rate of Serdes is getting higher and higher, and the medium insertion loss (Insertion Loss, IL) in the high-speed link interconnection medium also increases, so it is necessary to introduce heavy A timer (retimer) amplifies the driving capability of the signal, so that the high-speed link can tolerate greater insertion loss. The retimer is used to relay the data signal transmitted on the high-speed serial link, for example, the internal clock reconstructs the signal to increase the transmission energy of the data signal. In addition, the retimer can also be used to filter out link jitter. Thereby reducing the performance of data transmission.

As shown in FIG. 1 is a retimer (Retimer) 100 in the prior art. Due to the large signal attenuation in the high-speed serial link and the high frequency jitter in the link, the retimer 100 is usually set in the high-speed serial link to relay the data signal and filter the link Jitter. The retimer 100 includes a receiving end 110, a data processing circuit 120, and a sending end 130. The receiving end 110 is used to recover the received clock signal corresponding to the serial data according to the received serial data, convert the serial data into parallel data, and output the parallel data and the received clock signal to the data processing circuit 120. The data processing circuit 120 includes a cross-clock domain processing circuit. The cross-clock domain processing circuit buffers the parallel data through an elastic buffer according to the received clock signal and the transmitted clock signal generated by the transmitting terminal 130. And output the buffered parallel data to the sending end 130. In addition, the data processing circuit 120 is also used to encode, decode, scramble, and descramble the parallel data. The sending end 130 is used to convert and output the parallel data output by the data processing circuit 120 to serial data. The above-mentioned elastic buffer is a buffer with a variable data buffer amount, and the data buffer amount is determined by the reception clock signal and the transmission clock signal.

The above received clock signal is the clock recovered from the received serial data, and the transmitted clock signal is the clock signal generated by the transmitting terminal 130, that is, the clock signal generated according to the reference clock of the retimer 100, so the above received clock signal and transmission The clock signal will have a frequency difference, and the frequency difference is not fixed. Therefore, on the one hand, the cross-clock domain processing circuit in the data processing circuit 120 needs to perform asynchronous clock domain processing on the parallel data, so that the parallel data is synchronized from the clock domain receiving the clock signal to the clock domain transmitting the clock signal, and the receiving The frequency offset (frequency offset) between the clock signal and the transmitted clock signal. In the retimer 100, due to the existence of the above-mentioned elastic buffer in the prior art cross-clock domain processing circuit, the data processing delay is very large, so that the time for the data to pass the retimer becomes longer, thereby reducing the overall system Data processing performance. Under some transmission protocols, when it is necessary to support the clock spread spectrum function, the cross-clock domain processing circuit will introduce a larger delay when processing the signal across the clock domain, thereby further reducing the data processing performance of the entire system. The impact of high-speed serial links with more sensitive delays is particularly noticeable.

Summary of the invention

The embodiments of the present application provide a cross-clock domain processing circuit, which can be used to solve the problem of high delay when data is processed in the cross-clock domain.

In a first aspect, an embodiment of the present application provides a cross-clock domain processing circuit, configured to perform cross-clock domain processing on input data. The cross-clock domain processing circuit includes a phase alignment circuit and a synchronization circuit, wherein the phase alignment circuit is used to adjust the phase of the first working clock according to the first control signal, so that the phases of the above two clocks are aligned, and the input data clock and the adjusted The first working clock is output to the synchronization circuit, so that the synchronization circuit can synchronize the input data across clock domains according to the above two clocks to generate synchronized data, that is, synchronize the input data in the clock domain of the input data clock to the output data The clock domain of the clock. Wherein, the input data clock is a clock recovered from the input data, the frequency of the first working clock is equal to the frequency of the input data clock, and the first working clock is the working clock of the cross-domain processing circuit, or The processing circuit uses the same reference clock. The first control signal is also a control signal recovered from the input data, and the first control signal includes phase change information of the input data clock.

Since the cross-clock domain processing circuit uses the control signal recovered from the input data as a reference to adjust the phase of the local clock (ie, the first working clock), the adjusted local clock can follow the phase of the input data clock in real time as a synchronization The clock of the circuit saves the hardware resources occupied by the elastic buffer, makes the time for the data to pass through the processing circuit across the clock domain shorter, thereby reducing the delay in processing data across the processing circuit across the clock domain, and improving the efficiency of data transmission.

In a possible implementation manner, the phase alignment circuit includes a phase discriminator, a digital filter, and a phase interpolator, where the phase discriminator is used to discriminate the input data clock and the output data clock, and the digital filter is used to discriminate the phase And the first control signal are filtered, and the filtered result is output as the second control signal. The phase interpolator is used to adjust the phase of the first operating clock according to the second control signal, so that the first operating clock and the input The data clocks are phase-aligned, and the adjusted first working clock is output as the output data clock to the synchronization circuit and the phase detector. The above-mentioned process of filtering and shaking may be that the signal is superimposed and then filtered, or that the signal is first filtered and then superimposed. By performing the above processing on the first working clock, the jitter of the first working clock signal is filtered out, and the phase of the original input data clock is tracked, so that the phase tracking input data clock is generated with less hardware resources for synchronization Clock.

In a possible implementation manner, the above-mentioned phase interpolator is further used to: generate a second intermediate clock according to the first working clock, and the phase difference between the first working clock and the second intermediate clock is a preset phase difference; The second control signal adjusts the phases of the first working clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock. Wherein, the phase detector is further used to phase-detect the input data clock, the output data clock (that is, the adjusted first working clock) and the second intermediate clock to determine the phase relationship of the three clocks, and output the phase detector result. Through the above phase adjustment, the phase interpolator can keep the rising edge of the input data clock always between the rising edge of the first working clock and the rising edge of the second intermediate clock to achieve the purpose of phase alignment, which can be used to synchronize the above Input data.

In a possible implementation manner, when the phase interpolator adjusts the phases of the first operating clock and the second intermediate clock, the phase difference between the first operating clock and the input data clock is equal to the input data clock and the second intermediate clock 'S phase difference. When the phase difference between the first working clock and the second intermediate clock is small, the adjusted first working clock generated by the phase interpolator can better align with the phase of the input data clock.

In a possible implementation manner, the above-mentioned phase interpolator is further used: when the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is in the first State (for example, binary number 10) to instruct the phase interpolator to maintain the phases of the first working clock and the second intermediate clock; when the phase of the input data clock lags the phase of the first working clock and the phase of the second intermediate clock, The above-mentioned second control signal is in the second state (for example, binary number 00) to instruct the phase interpolator to adjust the phase so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock; when input The phase of the data clock leads the phase of the first working clock and the phase of the second intermediate clock. The second control signal is in a third state (eg, binary number 01) to instruct the phase interpolator to adjust the phase so that the input data The phase of the clock leads the phase of the first working clock and lags the phase of the second intermediate clock. When the frequency of the input data clock shifts, the first working clock and the second intermediate clock shift synchronously, so that the first working clock can follow the phase of the input data clock in real time.

In a possible implementation manner, the filtering of the first control signal and the phase discrimination result by the digital filter is high-frequency filtering, wherein the filtered first control signal includes a low-frequency jitter corresponding to the input data clock Phase change information. When the phase alignment circuit performs high-frequency filtering and jitter on the input data clock, the low-frequency jitter carried by the clock can be retained and accompanied by synchronous data output to downstream devices, so that the cross-clock domain processing circuit can support specific protocols or Preset functions, such as turning on and off the SRIS function.

In a possible implementation manner, the phase change information includes independent clock spreading information, independent clock non-spreading information, or homologous clock information.

In a possible implementation manner, the synchronization circuit includes a first sub-synchronization circuit and a second sub-synchronization circuit, wherein the first sub-synchronization circuit is used to synchronize the input data according to the input data clock and output the result to the second sub-synchronization circuit Synchronization circuit; the second sub-synchronization circuit synchronizes the above result according to the first working clock to obtain the above synchronization data. The synchronization processing of input data is realized by two sub-synchronization circuits, which simplifies the circuit structure of the processing circuit across clock domains and saves the hardware area and power consumption.

In a possible implementation manner, the first sub-synchronous circuit and the second sub-synchronous circuit are both registers, and the two sub-synchronous circuits synchronize the input data through the input data clock and the first working clock, respectively. Implementing the sub-synchronization circuit through registers greatly simplifies the circuit complexity of the processing circuit across clock domains, further saving hardware area and power consumption.

In a possible implementation manner, the cross-clock domain processing circuit further includes a first clock circuit, configured to provide the first operating clock to the phase alignment circuit. The first clock circuit provides less jitter and clutter on the first working clock, which is beneficial to data synchronization across clock domains.

In a possible implementation manner, the cross-clock domain processing circuit further includes a clock recovery circuit, the clock recovery circuit is used to be driven by the working clock of the cross-clock domain processing circuit, and recovers the received input data to obtain the input data clock And the first control signal, and output the above input data, the first control signal and the input data clock. The clock recovery circuit performs clock recovery on the input data, so that the recovered clock can be used again to synchronize the input data after phase adjustment and other processing, so as to realize cross-clock domain processing.

In a possible implementation manner, the input data is serial data, and the cross-clock domain processing circuit further includes a serial-to-parallel circuit. The serial-to-parallel circuit is used to perform serial-to-parallel conversion on the input data and output the serial data. And the converted input data (that is, parallel input data) to the above synchronization circuit. Correspondingly, the data between the two sub-synchronization circuits in the synchronization circuit is also parallel data. When the cross-clock domain processing circuit is used to process parallel data, the efficiency of data synchronization can be improved.

In a possible implementation manner, the sending end sends input data to the cross-clock domain processing circuit, and the synchronous data is output to the receiving end, in which there are three cases: First, the sending end and the cross-clock domain processing circuit share one Reference clock, the clock used by the receiving end is independent of the above-mentioned common reference clock; second, the receiving end and the cross-clock domain processing circuit share a reference clock, the reference clock of the sending end is independent of the above-mentioned common reference clock; third, the above-mentioned sending The end, the receiver, and the cross-clock domain processing circuit share a reference clock. The reference clock of the cross-clock domain processing circuit can be independent of the receiving end and the sending end, and can also share the reference clock, making its clock signal configuration more flexible.

In a second aspect, an embodiment of the present application provides a retimer for relaying N input data in a transmission link. The retimer includes a phase alignment circuit and N synchronization circuits (N≥1 and N is a positive integer), wherein the phase alignment circuit is used to adjust the phase of the first working clock according to the first control signal, so that the above two clock phases Align, and output the input data clock and the adjusted first working clock to N synchronization circuits, so that N synchronization circuits can synchronize N channels of input data across clock domains according to the above two clocks to generate N channels of synchronized data That is, the N input data in the clock domain of the input data clock is synchronized to the clock domain of the output data clock. Wherein, the frequency of the first working clock is equal to the frequency of the input data clock, and the first working clock is the working clock of the retimer, or uses the same reference clock as the retimer, and the above input data clock is based on the N input One of the N recovered clock clocks recovered from the data, for example, N recovered data clocks are recovered from the N input data through a clock recovery circuit, and one of the recovered clocks is selected as the input data clock. The first control signal is also one of the N control signals recovered from the N input data, and the first control signal includes phase change information of the input data clock.

Since the retimer uses the control signal recovered from the N input data as a reference to adjust the phase of the local clock (ie, the first working clock), the adjusted local clock can follow the phase of the input data clock in real time as a synchronization The clock of the circuit thus saves the hardware resources occupied by the elastic buffer, makes the time for the data to pass through the retimer shorter, thereby reducing the delay in processing data by the retimer, and improving the efficiency of data transmission.

In a possible implementation manner, the phase alignment circuit includes a phase discriminator, a digital filter, and a phase interpolator, where the phase discriminator is used to discriminate the input data clock and the output data clock, and the digital filter is used to discriminate the phase And the first control signal are filtered, and the filtered result is output as the second control signal. The phase interpolator is used to adjust the phase of the first operating clock according to the second control signal, so that the first operating clock and the input The data clocks are phase-aligned, and the adjusted first working clock is output as the output data clock to N synchronization circuits and phase detectors. By performing the above processing on the first working clock, the jitter of the first working clock signal is filtered out, and the phase of the original input data clock is tracked, so that the phase tracking input data clock is generated with less hardware resources for synchronization Clock.

In a possible implementation manner, each of the N synchronization circuits includes a first sub-synchronization circuit and a second sub-synchronization circuit, where the first sub-synchronization circuit is used to synchronize the above according to the input data clock One of the N input data, and output the result to the second sub-synchronization circuit; the second sub-synchronization circuit synchronizes the result according to the first working clock to obtain one channel of the synchronization data. The synchronization processing of the input data is realized by two sub-synchronization circuits, which simplifies the circuit structure of the retimer and saves the hardware area and power consumption.

In a possible implementation manner, the first sub-synchronous circuit and the second sub-synchronous circuit are both registers, and the two sub-synchronous circuits synchronize the input data through the input data clock and the first working clock, respectively. The realization of the sub-synchronous circuit through the register greatly simplifies the circuit complexity of the retimer, and further saves the hardware area and power consumption.

In a possible implementation manner, the retimer further includes a first clock circuit, configured to provide the first operating clock to the phase alignment circuit. The first clock circuit provides less jitter and clutter on the first working clock, which is beneficial to data synchronization across clock domains.

In a possible implementation manner, the filtering of the first control signal and the phase discrimination result by the digital filter is high-frequency filtering, wherein the filtered first control signal includes a low-frequency jitter corresponding to the input data clock Phase change information. When the phase alignment circuit performs high-frequency filtering and jitter on the input data clock, the low-frequency jitter carried by the clock can be retained and accompanied by synchronized data output to downstream devices, so that the retimer can support a specific protocol or preset in the transmission link Functions, such as turning SRIS on and off.

In a possible implementation manner, the retimer further includes N clock recovery circuits, which are respectively driven by the first working clock of the retimer, and recover the received N input data to obtain the N recovery Data clock and N control signals, and output the above-mentioned N input data, N control signals and N recovered data clocks. The clock recovery circuit performs clock recovery on the input data, so that the recovered clock can be used again to synchronize the input data after filtering and jittering, so as to realize the processing across clock domains.

In a possible implementation manner, the N input data is N serial input data, and the retimer further includes N serial-parallel circuits, wherein the N serial-parallel circuits are used for N channels The input data is subjected to serial-to-parallel conversion, and the converted result (ie, N parallel data) is output to the N synchronization circuits. By serial-to-parallel conversion of data, high-speed serial data in the transmission link can be converted into parallel data, which improves the efficiency of data processing by the retimer and saves data processing time.

In a possible implementation manner, the retimer further includes N parallel-to-serial circuits, and the N synchronization data is N parallel data, wherein the N parallel-to-serial circuits are used to separately synchronize N channels of data Perform parallel-to-serial conversion and output the converted result. By performing parallel-to-serial conversion on the data, the processed (synchronized) data can be converted back to a high-speed serial signal, improving the efficiency of the data processing by the retimer and saving data processing time.

In a possible implementation manner, the retimer further includes N data processing circuits and N data selectors, wherein the input terminals of the N data processing circuits are respectively coupled to the output terminals of the N clock recovery circuits, and N The output end of the data processing circuit is respectively coupled with the input ends of the N data selectors. The N data processing circuits are used to decode, descramble, synchronize, scramble, and encode the received N input data, respectively. The coupled data processing circuit, clock recovery circuit and data selector, the two input terminals of the data selector are respectively coupled with the output terminal of the clock recovery circuit and the output terminal of the data processing circuit, and the output terminal of the data selector is connected with the synchronization circuit Output coupling. The data selector can be controlled by an additional control signal to select one of the two data signals received at the two input terminals as an output. In the retimer, data can be directly synchronized across the clock domain through the data selector, or it can be advanced through the processing of the data processing circuit, and then synchronized across the clock domain through the data selector, so that the retimer processes input data The method is more flexible, you can choose whether to pass data according to different transmission protocols, thereby improving the efficiency of relaying data.

In a possible implementation manner, the sending end sends input data to the retimer, and the synchronous data is output to the receiving end, in which there are three cases: First, the sending end and the retimer share a reference clock, and receive The clock used by the terminal is independent of the above-mentioned common reference clock; second, the receiving terminal and the retimer share a reference clock, and the reference clock of the transmitting end is independent of the above-mentioned shared reference clock; third, the transmitting end, the receiving end and the re-timer The timers share a reference clock. The reference clock of the retimer can be independent of the receiving end and the sending end, and can also share the reference clock, making its clock signal configuration more flexible.

In a possible implementation manner, the retimer is a multi-channel retimer, where N≥2, and N is a positive integer. By increasing the number of synchronization circuits, clock recovery circuits and other circuits in the retimer, the retimer can process multiple input data at the same time, thereby further improving the efficiency of the retimer to relay data.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art.

Figure 1 is a retimer in the prior art.

FIG. 2 is a retimer in the embodiment of the present application.

FIG. 3 is a specific retimer in the embodiment of the present application.

FIG. 4 is a more specific retimer in the embodiment of the present application.

5(a) is a timing diagram of a phase interpolator in an embodiment of this application;

5(b) is another timing diagram of the phase interpolator in the embodiment of the present application;

FIG. 5(c) is another timing diagram of the phase interpolator in the embodiment of the present application.

FIG. 6 is a synchronization circuit in an embodiment of the present application.

FIG. 7 is a more specific retimer in the embodiment of the present application.

FIG. 8 is a data processing circuit in an embodiment of the present application.

FIG. 9 is a multi-channel retimer in an embodiment of the present application.

Main reference signs: retimer 300; data receiving circuit 310; clock recovery circuit 312; serial parallel circuit 314; equalizer 316; second clock circuit 318; data transmission circuit 320; phase alignment circuit 330; phase detector 332 Digital filter 334; phase interpolator 336; first clock circuit 335; synchronization circuit 340; parallel-to-serial circuit 370.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application.

To solve the problem of a large delay of the retimer, an embodiment of the present application provides a retimer 300 as shown in FIG. 2. The retimer 300 is set on the high-speed serial communication link between the first device 210 and the second device 220. The communication link can use PCIe (Peripheral Component Interface, peripheral bus interface), Ethernet (Ethernet), and SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), serial connection (SCSI interface), USB (Universal Serial Bus, universal serial bus) and other protocol communication links. The retimer 300 is used to relay the data signal, for example, to reconstruct the signal by an internal clock, so that the transmission energy of the data signal increases. The retimer 300 can also be used to filter out the jitter in the above communication link. The above data signal may be a data signal sent from the first device 210 to the second device 220, or may be a data signal sent by the second device 220 to the first device 210. The first device and the second device may include terminal devices, such as mobile phones and tablet computers; they may also include server devices or communication base stations; or include two independent PCBs (Printed Circuit Board). Circuit.

As shown in FIG. 3, a specific implementation of the retimer 300 is shown. The retimer 300 includes a receiving circuit 310 and a transmitting circuit 320, wherein the receiving circuit 310 includes a clock recovery circuit 312 and a serial parallel circuit 314, the clock recovery circuit 312 is used to drive the received serial data according to the drive of its reference clock ( Input data) to perform clock recovery to obtain the input data clock and the first control signal, and simultaneously output the above serial data, and the recovered input data clock and the first control signal, the reference clock may be the working clock of the receiving circuit 310, The first control signal includes phase change information of the input data clock. The serial-parallel conversion circuit 314 is used to convert the serial data into parallel data and output the parallel data. The working clock of the receiving circuit 310 can be determined according to the reference clock of the retimer 300. The clock recovery circuit 312 can recover the clock by detecting the phase of the serial data. The clock recovery circuit 312 can be implemented in various ways, such as using a passive filter and a limiting amplifier, using a narrow-band regenerative divider, and using synchronization Oscillator implementation, or use a phase-locked loop, etc.

The sending circuit 320 is used for synchronizing the parallel data output by the receiving circuit 310 across clock domains, and converting the synchronized parallel data into serial data and outputting it to the second device 220. Specifically, the transmission circuit 320 includes a phase alignment circuit 330, a synchronization circuit 340, and a parallel-to-serial circuit 370. The phase alignment circuit 330 is used to receive the input data clock and the first working clock, adjust the phase of the first working clock according to the first control signal, so that the adjusted phase of the first working clock is aligned with the phase of the input data clock, and The adjusted first working clock is output to the synchronization circuit 340 as an output data clock. The input data clock is the clock recovered by the clock recovery circuit 312 from the input data, and the first control signal is also the information recovered by the clock recovery circuit 312 from the input data. This information can be used as a control signal to control the phase alignment circuit 330 Adjust the phase of the first working clock. The above-mentioned first working clock is a clock independent of the input data clock, and is the working clock of the transmitting circuit 320 in the retimer 300, and the frequency of the first working clock is equal to the frequency of the input data clock. It should be noted that the above first working clock, that is, the working clock of the sending circuit 320 and the working clock of the receiving circuit 310 (that is, the second working clock below) are independent working clocks, but the same reference clock (reference clock) may be used Or use different reference clocks.

The synchronization circuit 340 is configured to synchronize the parallel data generated by the clock recovery circuit 312 across clock domains according to the input data clock and the output data clock, and generate synchronized data, where the synchronized data is in the clock domain of the output data clock . Since the data in the receiving circuit 310 is in the clock domain of the input data clock and the data in the transmitting circuit 320 is in the clock domain of the output data clock, the synchronization circuit 340 synchronizes the parallel data from the clock domain of the input data clock to the output data clock Clock domain. The parallel-to-serial circuit 370 is used to convert the received synchronization data into serial output data, and output the serial output data to the second device 220. The jitter of the high-frequency component includes high-frequency jitter generated by the high-speed serial communication link, and high-frequency jitter generated by the clock recovery circuit 312 when recovering the clock.

It should be noted that the “high frequency” in the high-frequency jitter and high-frequency filtering in the present application should be a concept well known to those skilled in the art. For clock signals with different frequencies, the scope of "high frequency" in this application will be different. For example, for a clock signal with a frequency of f=100MHz, jitters with a frequency greater than 0.5f should be considered high-frequency jitter; correspondingly, high-frequency jitter filtering is to remove jitters with a frequency greater than 0.5f. More specifically, the phase alignment circuit 330 provided in the embodiment of the present application can perform high-frequency filtering and jittering on a 100 MHz clock signal, and all jitters with a frequency higher than 500 KHz carried by the clock signal will be filtered out. Correspondingly, low frequency jitter is jitter with a frequency less than 0.5f. As another example, for a clock signal with a frequency of f=1 GHz, jitters with a frequency greater than 0.05f should be considered high-frequency jitter, and jitters below 0.05f should be considered low-frequency jitter. In addition, the phase alignment in this application can be understood as that the phase difference of the rising edges of the two clock signals is a fixed value, for example, the phase difference remains -1°, 0°, or 1°; it can also be understood that the two The phase difference of the rising edge of the clock signal is kept within a certain range.

The first working clock is the working clock of the retimer, that is, the clock is a local clock with less jitter. The retimer 300 uses the first control signal recovered from the input data to adjust the phase of the local clock, so that the adjusted local clock can follow the phase of the input data clock in real time to serve as the clock of the synchronization circuit 340. The retimer When relaying data, 300 does not need to synchronize the clock domain through the elastic buffer, making the time for the data to pass through the retimer 300 shorter, thereby reducing the delay of the retimer 300 to process data, especially when the data crosses the clock domain Delay improves the efficiency of data transmission.

As shown in FIG. 4, a specific implementation manner of the above-mentioned phase alignment circuit 330 is shown. The phase alignment circuit 330 includes a phase detector (Phase Detector, PD) 332, a digital filter (Digital) Filter 334, and a phase interpolator (Phase Interpolator, PI) 336. The phase discriminator 332 is used to discriminate the output data clock and the input data clock, that is, discriminate the phase relationship between the two clocks, and output the phase discrimination result. The digital filter 334 is used to filter and shake the phase discrimination result and the first control signal, and output the filtered result to the phase interpolator 336 as the second control signal. The digital filter 334 may first superimpose the phase discrimination result and the first control signal, perform filtering and dithering, and output it as a second control signal; or it may first filter and dither the phase discrimination result and the first control signal, Then superimpose and output as the second control signal. In one embodiment, the digital filter 334 does not respond to high-frequency jitter, but only responds to low-frequency jitter, that is, filters out only high-frequency jitter, while retaining low-frequency jitter, which can carry the frequency of the input data clock or Phase change information. The phase interpolator 336 is used to adjust the phase of the first working clock according to the second control signal, so that the first working clock and the input data clock are phase aligned, and output the adjusted first working clock as the output data clock to the synchronization Circuit 340 and phase detector 332.

Specifically, the phase interpolator 336 first generates a second intermediate clock according to the phase of the first working clock, and the phase difference between the second intermediate clock and the first working clock is a preset fixed phase difference; The above-mentioned output data clock, second intermediate clock and input data clock perform phase discrimination to determine the phase relationship between the three clock signals, and output the result of phase discrimination, and the digital filter 334 filters the phase discrimination result. At the same time, the first control signal is filtered, and the above two filtered results are superimposed, and the superimposed signal is output as the second control signal to the phase interpolator 336, and the filtering is to filter out jitter in the signal; the phase interpolator 336 Adjust the phases of the first working clock and the second intermediate clock according to the second control signal so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock, and adjust The first working clock after that is output as the output data clock to the synchronization circuit 340 and the phase detector 332.

The first control signal is the control signal recovered by the clock recovery circuit 312. Specifically, the clock recovery circuit 312 recovers the above-mentioned first control signal while clock-recovering the input data, the first control signal includes phase change information corresponding to the jitter contained in the above-mentioned input data clock, that is, That is to say, the first control signal can indicate the phase change of the input data clock. In one embodiment, the first control signal includes low-frequency jitter information of the input data clock. The low-frequency jitter is also called low-frequency offset (wander), which is usually spread-spectrum clock (Spread Spectrum Clock) information. Or called non-homologous clock (Separated Clock) information, such as independent clock spread spectrum information, it can also be independent clock non-spread spectrum information; the above-mentioned low frequency jitter can also be homogenous clock (Common) Reference Clock information; at the same time A control signal also includes high-frequency jitter information of the input data clock, which usually comes from high-frequency noise (or high-frequency jitter) generated by the clock recovery circuit 312 and generated by the link. Therefore, the digital filter 334 is also used to perform high-frequency filtering and dithering on the first control signal and the phase discrimination result to filter out high-frequency noise, and retain phase change information corresponding to the low-frequency jitter of the input data clock.

As shown in FIG. 4, the retimer 300 further includes a second clock circuit 318 and a first clock circuit 335, wherein the second clock circuit 318 is used to generate a second working clock according to the reference clock and output the second working clock To the clock recovery circuit 312, so that the clock recovery circuit 312 recovers the clock signal from the input data; the first clock circuit 335 is used to generate a first working clock according to the reference clock, and output the first working clock to the phase alignment circuit 330, To generate the output data clock. The first working clock is the working clock generated by the first clock circuit 335 in the sending circuit 320, and the frequency of the first working clock generated by the first clock circuit 335 is equal to the frequency of the input data clock. It should be noted that the second clock circuit 318 and the first clock circuit 335 in this embodiment are independent clock circuits, and the above two clock circuits may be phase locked loops (Phase Locked Loop, PLL), etc. The second clock circuit 318 and the first clock circuit 335 may use the same clock source as the reference clock, or two independent clock sources as the reference clock.

Since the clock signal is usually a rectangular pulse with the same pulse width, its spectrum component contains higher harmonics, and the clock signal and these higher harmonics together produce electromagnetic interference in a certain circuit or between different circuits. In order to reduce the above-mentioned electromagnetic interference, a method of spreading the clock may be used, that is, a preset modulation waveform (for example, a lower frequency) is used to frequency modulate the above-mentioned clock signal within a certain frequency range, so that the base of the clock signal The peak energy contained in the frequency and harmonics is reduced. For example, in the above-mentioned high-speed serial link, the above-mentioned input data clock may be a clock carrying the SSC information of the spread spectrum clock. In the frequency domain, SSC information appears as a clock signal producing a spectrum with sideband harmonics. While performing high-frequency filtering and jittering on the first intermediate clock, the digital filter 334 can retain complete low-frequency jitter, so that certain clock information contained in the first intermediate clock or certain clocks included in the input data clock can be retained Information, such as SSC information. At the same time, the digital filter 334 filters out high-frequency jitter from the link and clock recovery circuit 312 and the like. Therefore, when the SRIS function (Separate-Reference-Independent SSC) of the high-speed serial link is enabled, both the input data clock and the output data clock in the retimer 300 can retain the clock signal. SSC information, while filtering out high frequency jitter.

Since the input data clock contains low frequency jitter, the phase of the rising edge of the input data clock is usually not fixed, but drifts back and forth. As shown in Figure 5, the input data clock drifts within a certain clock offset range. The specific function of the phase interpolator 336 is explained by the timing chart shown in FIG. First, the phase interpolator 336 is used to receive the first working clock, take the phase of the first working clock as a reference, and generate a second intermediate clock according to a preset phase difference and a second control signal, the first working clock and the second The second phase difference of the intermediate clock is a preset fixed value, and the second phase difference is the alignment window in the figure. The above phase difference can also be understood as the phase difference between two rising edges adjacent to the first working clock and the second intermediate clock. Next, the phase detector 332 performs phase detection on the first working clock, the second intermediate clock, and the input data clock to determine the phase relationship between the three clocks.

Taking FIG. 5(a) as an example, the phase detector 332 may use the rising edge of the input data clock to sample the first working clock and the second intermediate clock, that is, the phase detector, to determine the phase relationship between the above three clocks. If the sample value is 2'b10 (two binary digits, the low bit 0 indicates that the sample value of the second intermediate clock is 0, and the high bit 1 indicates that the sample value of the first working clock is 1), that is, when the input data clock is on the rising edge , The first working clock is high level (1), and the second intermediate clock is low level (0), which means that the sampling value of 2'b10 corresponds to the input data clock in the above alignment window, input The phase of the data clock leads the phase of the first working clock and lags the phase of the second intermediate clock. The phase discriminator 332 filters and dithers the sampling result through the digital filter 334, and then outputs it as the second control signal to the phase interpolator 336, so the phase interpolator 336 can determine whether the input data clock is aligned according to the second control signal The window is between the first working clock and the second intermediate clock.

In FIG. 5(b), the input data clock deviates from the above alignment window, the phase of the input data clock lags behind the phase of the first working clock and the phase of the second intermediate clock, at this time the sampling of the rising edge of the input data clock The value is 2'b00. The phase interpolator 336 receives the above-mentioned second control signal generated by the digital filter 334 (that is, contains the sample value 2′b00 generated by the phase discriminator 332), and adjusts the phase of the first working clock by using a phase interpolation method, and The phase of the second intermediate clock is also adjusted so that the input data clock is within the alignment window formed after the adjustment, that is, the adjusted sample value becomes 2'b10 again.

In FIG. 5(c), the input data clock also deviates from the above alignment window. The phase of the input data clock leads the phase of the first working clock and the phase of the second intermediate clock. At this time, the rising edge of the input data clock The sampled value is 2'b11 or 2'b01. Taking the sample value of 2'b11 as an example, after the phase interpolator 336 receives the above-mentioned second control signal generated by the digital filter 334 (that is, includes the sample value 2'b11 generated by the phase discriminator 332), the phase interpolation method is used to The phase of the first working clock is adjusted, and the phase of the second intermediate clock is also adjusted so that the input data clock is within the alignment window formed after the adjustment, that is, the adjusted sample value becomes 2'b10 again.

When the SRIS function is enabled on the high-speed serial link, the input clock signal carries SSC information, that is, low-frequency jitter, and its phase will always change periodically, that is, periodically drift within a certain range. The phase interpolator 336 adjusts the phase of the first working clock according to the period of the phase change of the input data clock, and the adjusted period is the period of the phase change of the input data clock, that is, the SSC change period. Therefore, the phase of the output data clock (that is, the adjusted first working clock) always changes with the phase of the input data clock, thereby achieving the purpose of retaining low-frequency jitter and filtering out high-frequency jitter.

In one embodiment, the phase interpolator 336 adjusts the first working clock and the second intermediate clock so that the rising edge of the input data clock is always at the center of the alignment window, that is, the phase difference between the second intermediate clock and the input data clock is equal to The phase difference between the input data clock and the first working clock. Therefore, when the alignment window is small, the first working clock generated by the phase interpolator 336 can be better phase aligned with the input data clock.

As shown in FIG. 6, a specific implementation of the synchronization circuit 340 is shown. The synchronization circuit 340 includes a first sub-synchronization circuit 342 and a second sub-synchronization circuit 344, where the first sub-synchronization circuit 342 is used to synchronize the received input data for the first time according to the input data clock to obtain first temporary data; The two-sub-synchronization circuit 344 is used to perform the second synchronization on the first temporary data according to the first working clock (ie, the output data clock) to obtain the synchronized data. Synchronizing the input data twice through the two clocks respectively enables the synchronous data to be transmitted at the frequency of the output data clock, and can prevent the occurrence of the metastable state and prevent the retimer 300 from being affected by the propagation of the metastable state.

In one embodiment, the first sub-synchronization circuit 342 and the second sub-synchronization circuit 344 in the synchronization circuit 340 are both registers, and the clock used by the first sub-synchronization circuit 342 is the above input data clock, and the second sub-synchronization The clock used for the operation of the circuit is the above-mentioned first operating clock (ie, the output data clock). The above register may include multiple D flip-flops connected in parallel. According to the above two clocks, it can be ensured that the second sub-synchronous circuit 344 can correctly sample the data.

It should be noted that the combination of any one or more of the above-mentioned phase alignment circuit 330, synchronization circuit 340, and clock recovery circuit 312 included in the retimer 300 in this application can also be used to implement other circuits that process across clock domains Or scenarios, the retimer 300 in this application is only an example of a scenario. In addition, the input data and the synchronization data in the embodiments of the present application may be parallel data or serial data. For example, an embodiment of the present application further provides a cross-clock domain processing circuit, including the above-mentioned phase alignment circuit 330, synchronization circuit 340, and clock recovery circuit 312, wherein the input data received by the cross-clock domain processing circuit and the generated synchronization data may be both It can be parallel data or serial data.

The retimer 300 shown in FIG. 7 is a more specific implementation. The retimer 300 in FIG. 7 further includes an equalizer 316, a second clock circuit 318, a data processing circuit 350, and a data selector 360. Among them, the equalizer 316 is used to equalize the serial data received by the receiving circuit 310, such as continuous time linear equalization (Continuous Time Linear Equalizer, CTLE), to improve the high-speed serial link with large transmission loss The performance of the eye diagram (Eye Diagram) of the data receiving circuit 310, and outputs the equalized serial data to the clock recovery circuit 312. The second clock circuit 318 is used to provide a second working clock to the clock recovery circuit 312 according to the reference clock of the retimer 300.

The first device 210 relays data through the retimer 300, and sends the relayed data to the second device 220. In one embodiment, the first device 210 and the retimer 300 share the same reference clock, and the reference clock of the second device 220 is independent of the above-mentioned shared reference clock; in one embodiment, the second device 220 and The retimer 300 shares the same reference clock, and the reference clock of the first device 210 is independent of the above-mentioned shared reference clock; in another embodiment, the first device 210, the second device 220, and the retimer 300 are respectively Use an independent reference clock.

The data processing circuit 350 is used to perform processing such as encoding, decoding, scrambling, buffering, and synchronization on the data. The data processing circuit 350 can selectively perform processes such as decoding, descrambling, synchronization, scrambling, and encoding on the received data, and the order of the foregoing multiple processing procedures is variable. For example, the received data may be sequentially decoded, descrambled, synchronized, scrambled, and encoded, or may be sequentially decoded, synchronized, and encoded, or descrambled, synchronized, and scrambled. A specific implementation of the data processing circuit 350 is shown in FIG. 8. Specifically, the data processing circuit 350 includes a decoder (De-coder) 351, a descrambling circuit (De-Scrambler) 352, an elastic buffer (Elastic Buffer) 353, a link training state machine (Link Training) and Status Machine, LTSSM) 354, scrambling circuit (Scrambler) 355 and encoder (Encoder) 356. The decoder 351 is used to perform aligned decoding on the received data, for example, to find the feature words in the received data, and remove the synchronization header in the data according to the feature words. The descrambling circuit 352 is used for descrambling the data output from the decoder 351. The elastic buffer 353 is used to buffer the data output by the descrambling circuit 352 and output the buffered data to the link training state machine 354. The elastic buffer 353 is a variable data buffer. The amount of data buffering is determined by the reference clock of the retimer 300. The link training state machine 354 is used to receive the data output from the elastic buffer 353 and train the link. For example, before the link using the PCIe interface works normally, the link training state machine 354 needs to be trained to initialize the link and configure link information. When the link training is completed and the normal operation is performed, the data generated by the elastic buffer 353 can be directly output to the scrambling circuit 355 without going through the link training state machine 354. The scrambling circuit 355 is used to perform scrambling processing on the data output by the link training state machine 354, where the scrambling processing may adopt a method corresponding to descrambling. The decoder 356 is used to encode the scrambled data and output the encoded data.

The data selector 360 is used to simultaneously receive the data generated by the clock recovery circuit 312 and the data generated by the data processing circuit 350, and select one of the above two channels of data to output to the synchronization circuit 340. In one embodiment, the data selector 360 may output the data generated by the clock recovery circuit 312 or the data generated by the data processing circuit 350 through a control signal, and the control signal may be configured through a register. Since the data selector 360 has a function of selecting one of two channels of data, parallel data can pass from the data receiving circuit 310 to the data transmitting circuit 320 through two paths. First, the parallel data is first output from the clock recovery circuit 312 to the data processing circuit 350, and then from the data processing circuit 350 through the data selector 360 and input to the data transmission circuit 320. Under a specific transmission protocol, the above-mentioned parallel data is processed in the data processing circuit 350 such as codec, scrambling and descrambling. Second, parallel data is directly output from the clock recovery circuit 312, passes through the data selector 360, and is input to the data transmission circuit 320 without any data processing. This BSF (Bit Stream Forward) method can maximize Reduce the delay caused by data passing through the retimer 300. By adjusting the control signal of the data selector 360, the retimer 300 can be controlled to switch between the above two modes.

As shown in FIG. 9 is a multi-channel retimer 1000 provided by an embodiment of the present application. The retimer 1000 includes an upstream retiming circuit 1010 and a downstream retiming circuit 1020. Among them, the upstream retiming circuit 1010 is used to realize the relaying and filtering of multiple serial signals on the upstream high-speed serial transmission link of the first device 210 to the second device 220, and the downstream retiming circuit 1020 is used to Multiple downlink serial signals are relayed and filtered on the downlink high-speed serial transmission link from the second device 220 to the first device 210. It should be noted that the above concepts of uplink and downlink are relative. Taking four upstream channels and four downstream channels as examples to illustrate the circuit structure of the retimer 1000, but this application does not limit the number of upstream channels and downstream channels in the retimer 1000. Specifically, the upstream retiming circuit 1010 includes four upstream channels, where each upstream channel includes a data receiving circuit, a data processing circuit, a data selector, and a data sending circuit, and the direction of data flow is from the first Device 210 to the second device 220; the downlink retiming circuit 1020 also includes 4 downlink channels, where each downlink channel includes a data receiving circuit, a data processing circuit, a data selector 360, and a data sending circuit, and its data flow The direction is opposite to the upstream retiming circuit 1010, from the second device 220 to the first device 210. Similar to the retimer 300, for each upstream channel or downstream channel, serial data is converted into parallel data by the data receiving circuit n, data is processed by the data processing circuit n and output to the data selector 360, or does not pass data processing The circuit n directly outputs to the data selector 360, and finally synchronizes across clock domains through the data transmission circuit n, and converts the synchronized parallel data into serial data. In the retimer 1000, the aforementioned n may be 1, 2, ..., 8.

Data receiving circuit 1, data receiving circuit 2, data receiving circuit 3, data receiving circuit 4, data receiving circuit 5, data receiving circuit 6, data receiving circuit 7, data receiving circuit in the retimer 1000 shown in FIG. 9 All 8 may include some or all circuits in the data receiving circuit 310 provided in the embodiments of the present application, and some circuits in the common data receiving circuit 310. The data transmission circuit 1, the data transmission circuit 2, the data transmission circuit 3, the data transmission circuit 4, the data transmission circuit 5, the data transmission circuit 6, the data transmission circuit 7, and the data transmission circuit 8 in the retimer 1000 may all include this application Some or all of the circuits in the data transmission circuit 320 provided in the embodiment, and some of the circuits in the data transmission circuit 320 are shared.

In one embodiment, the four data receiving circuits in the upstream retiming circuit 1010 can share one clock processing circuit 1, and the four data receiving circuits in the downstream retiming circuit 1020 can also share one clock processing circuit 2. Both the processing circuit 1 and the clock processing circuit 2 may be the second clock circuit 318 in the embodiment of the present application. The four parallel data in the upstream retiming circuit 1010 are recovered by the clock processing circuit 1 to output four clock signals respectively, and one of the clock signals is selected to be output as the input clock signal to the synchronization circuit; the downstream retiming circuit 1020 is the same.

In one embodiment, the four data transmission circuits in the upstream retiming circuit 1010 may share one phase alignment circuit 330, and the four data receiving circuits in the downstream retiming circuit 1020 may also share one phase alignment circuit 330. Each data transmission circuit in the upstream retiming circuit 1010 includes a synchronization circuit 340, and each data transmission circuit in the downstream retiming circuit 1010 also includes a synchronization circuit 340 to synchronize the synchronization in each data transmission circuit. Input data. In addition, the data processing circuit 1, the data processing circuit 2, the data processing circuit 3, the data processing circuit 4, the data processing circuit 5, the data processing circuit 6, the data processing circuit 7, and the data processing circuit 8 in the retimer 1000 can all be The data processing circuit 320 provided by the embodiment of the present application.

In the above multi-channel retimer 1000, the multi-channel shares a clock processing circuit, a synchronization circuit 340 and a phase alignment circuit 330, so that the retimer 1000 further reduces the required buffer resources while ensuring low latency, Therefore, the hardware area of the retimer 1000 and the power consumption are reduced, and the performance of the retimer 1000 is improved.

A specific example is used to explain the specific structure of the multi-channel retimer 1000. The retimer is used to relay N input data in the transmission link. The retimer includes a phase alignment circuit and N synchronization circuits (N≥1 and N is a positive integer), wherein the phase alignment circuit is used to adjust the phase of the first working clock according to the first control signal, so that the above two clock phases Align, and output the input data clock and the adjusted first working clock to N synchronization circuits, so that N synchronization circuits can synchronize N channels of input data across clock domains according to the above two clocks to generate N channels of synchronized data That is, the N input data in the clock domain of the input data clock is synchronized to the clock domain of the output data clock. Wherein, the frequency of the first working clock is equal to the frequency of the input data clock, and the first working clock is the working clock of the retimer, or uses the same reference clock as the retimer, and the above input data clock is based on the N input One of the N recovered clock clocks recovered from the data, for example, N recovered data clocks are recovered from the N input data through a clock recovery circuit, and one of the recovered clocks is selected as the input data clock. The first control signal is also one of the N control signals recovered from the N input data, and the first control signal includes phase change information of the input data clock.

The above phase alignment circuit includes a phase discriminator, a digital filter and a phase interpolator, wherein the phase discriminator is used to discriminate the input data clock and the output data clock, and the digital filter is used to filter the result of the phase discrimination and the first control signal Jitter, and output the filtered result as a second control signal. The phase interpolator is used to adjust the phase of the first working clock according to the second control signal, so that the phase of the first working clock and the input data clock are aligned, and the adjusted The first working clock is output to the synchronization circuit as the output data clock.

When the phase interpolator adjusts the phases of the first operating clock and the second intermediate clock, the phase difference between the first operating clock and the input data clock is equal to the phase difference between the input data clock and the second intermediate clock.

The above phase interpolator is further used to: generate a second intermediate clock according to the first operating clock, and the phase difference between the first operating clock and the second intermediate clock is a preset phase difference; adjust the first operation according to the second control signal The phases of the clock and the second intermediate clock make the phase of the input data clock lead the phase of the first working clock and lag behind the phase of the second intermediate clock. Wherein, the phase detector is further used to phase-detect the input data clock, the output data clock (that is, the adjusted first working clock) and the second intermediate clock to determine the phase relationship of the three clocks, and output the phase detector result.

The above-mentioned phase interpolator is further used to: when the phase of the input data clock leads the phase of the first working clock and lags behind the phase of the second intermediate clock, the second control signal is in the first state (eg, binary number 10), Instruct the phase interpolator to maintain the phases of the first working clock and the second intermediate clock; when the phase of the input data clock lags the phase of the first working clock and the phase of the second intermediate clock, the second control signal is in the second state (Eg binary number 00) to instruct the phase interpolator to adjust the phase so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock; when the phase of the input data clock leads the first operation The phase of the clock is ahead of the phase of the second intermediate clock. The second control signal is in a third state (eg, binary number 01) to instruct the phase interpolator to adjust the phase so that the phase of the input data clock leads the first working clock And lag behind the phase of the second intermediate clock.

Each of the N synchronization circuits includes a first sub-synchronization circuit and a second sub-synchronization circuit, wherein the first sub-synchronization circuit is used to synchronize one of the N input data according to the input data clock, and The result is output to the second sub-synchronization circuit; the second sub-synchronization circuit synchronizes the above result according to the first working clock, and obtains one channel of synchronization data in the synchronization data.

The first sub-synchronous circuit and the second sub-synchronous circuit are both registers, and the two sub-synchronous circuits synchronize the input data through the input data clock and the first working clock, respectively.

The retimer further includes a first clock circuit for providing the first operating clock to the phase alignment circuit.

The filtering of the first control signal and the phase discrimination result by the above digital filter is high frequency filtering, wherein the filtered first control signal includes phase change information corresponding to the low frequency jitter of the input data clock.

The above phase change information includes independent clock spread spectrum information, independent clock non-spread spectrum information or homologous clock information.

The retimer also includes N clock recovery circuits, which are respectively driven by the first operating clock of the retimer, recover the received input data to obtain the N recovery data clocks and N control signals, and output the above Input data, N control signals and N recovery data clocks.

The N-channel input data is N-channel serial input data, and the retimer further includes N serial-parallel conversion circuits, wherein the N serial-parallel conversion circuits are respectively used for serial-to-parallel conversion of N channels of input data and output The converted result (ie, N parallel data) is sent to the above N synchronization circuits.

The retimer further includes N parallel-to-serial circuits, and the N-channel synchronous data is N-channel parallel data, wherein the N-parallel-to-serial circuits are used to perform parallel-to-serial conversion on the N synchronous data, and Output the converted result.

The above retimer also includes N data processing circuits and N data selectors, wherein the input terminals of the N data processing circuits are respectively coupled to the output terminals of the N clock recovery circuits, and the output terminals of the N data processing circuits are respectively connected to the N The input ends of the data selectors are coupled, and N data processing circuits are used to decode, descramble, synchronize, scramble, and encode the N input data received; for each coupled data processing circuit and clock recovery circuit And the data selector, the two input terminals of the data selector are respectively coupled with the output terminal of the clock recovery circuit and the output terminal of the data processing circuit, and the output terminal of the data selector is coupled with the output terminal of the synchronization circuit. The data selector can be controlled by an additional control signal to select one of the two data signals received at the two input terminals as an output.

The sending end sends input data to the retimer, and the synchronous data is output to the receiving end. There are three situations: First, the sending end and the retimer share a reference clock, and the clock used by the receiving end is the same as the above reference The clock is independent; second, the above-mentioned receiving end and the retimer share a reference clock, and the sending end's reference clock is independent of the above-mentioned common reference clock; third, the above-mentioned sending end, the receiving end and the retimer share a reference clock.

The above retimer is a multi-channel retimer, where N≥2, and N is a positive integer.

The retimer in the embodiment of the present application may be a retimer chip, which is used to relay the data signal on the high-speed serial transmission link and filter out jitter. The retimer chip may be an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or other types of integrated circuits. The aforementioned retimer chip includes any retimer provided according to the present application, wherein the circuit in the retimer is integrated on a die.

An embodiment of the present application further provides a retimer device, including one or more of the above retimer chips. In one embodiment, the one or more retimer chips are independently packaged and provided on a PCB (Printed Circuit Board); in one embodiment, the one or more retimer chips The retimer chip can also be packaged independently and separately set on multiple PCBs, and communicate through the connection ports or data connection lines between the PCBs; in another embodiment, the multiple retimers The chip can also be packaged in a package structure and placed on the PCB.

Claims

A cross-clock domain processing circuit for cross-clock domain processing of received input data, characterized in that the cross-clock domain processing circuit includes a phase alignment circuit and a synchronization circuit, wherein:

The phase alignment circuit is used for receiving an input data clock and a first working clock, adjusting the phase of the first working clock according to a first control signal, and outputting the phase adjusted first working clock as an output data clock to all In the synchronization circuit, the phase of the output data clock is aligned with the phase of the input data clock, the input data clock is a clock recovered from the input data, and the first working clock is the cross-clock domain processing An operating clock of the circuit, and the frequency of the first operating clock is equal to the frequency of the input data clock, the first control signal is a control signal recovered from the input data, and the first control signal includes all Describe the phase change information of the input data clock;

The synchronization circuit is configured to synchronize the input data across clock domains according to the input data clock and the output data clock to generate synchronized data, and the synchronized data is in a clock domain of the output data clock.
The cross-clock domain processing circuit according to claim 1, wherein the phase alignment circuit includes a phase discriminator, a digital filter, and a phase interpolator, wherein:

The phase discriminator is used to discriminate the input data clock and the output data clock, and output a phase discrimination result;

The digital filter is used to filter and shake the phase discrimination result and the first control signal, and output the filtered result as a second control signal to the phase interpolator;

The phase interpolator is used to adjust the phase of the first working clock according to the second control signal, so that the phase of the first working clock is aligned with the phase of the input data clock, and the phase adjusted The first operating clock is output as the output data clock to the synchronization circuit and the phase detector.
The cross-clock domain processing circuit according to claim 2, wherein the phase interpolator is further used for:

Generating a second intermediate clock according to the first working clock, and the phase difference between the first working clock and the second intermediate clock is a preset phase difference;

Adjusting the phases of the first working clock and the second intermediate clock according to the second control signal, so that the phase of the input data clock leads the phase of the first working clock and lags the second intermediate The phase of the clock.

The phase detector is further used for:

Phase-identify the output data clock, the second intermediate clock, and the input data clock, and determine the phase relationship of the output data clock, the second intermediate clock, and the input data clock to output the Phase comparison results.
The cross-clock domain processing circuit according to claim 3, wherein the phase interpolator is further used to:

When the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is used to instruct the phase interpolator to maintain the first The phase of the working clock and the second intermediate clock;

When the phase of the input data clock lags behind the phase of the first working clock and the phase of the second intermediate clock, the second control signal is used to instruct the phase interpolator to adjust the first operation The phase of the clock and the second intermediate clock, so that the phase of the input data clock leads the phase of the first working clock and lags the phase with the second intermediate clock;

When the phase of the input data clock leads the phase of the first working clock and the phase of the second intermediate clock, the second control signal is instructed to instruct the phase interpolator to adjust the first The phases of the working clock and the second intermediate clock, such that the phase of the input data clock leads the phase of the first working clock and lags the phase with the second intermediate clock.
The cross-clock domain processing circuit according to any one of claims 2 to 4, wherein the filtering of the first control signal and the phase discrimination result by the digital filter is high-frequency filtering, wherein The first control signal after filtering includes phase change information corresponding to the low frequency jitter of the input data clock.
The cross-clock domain processing circuit according to claim 5, wherein the phase change information includes independent clock spreading information, independent clock non-spreading information, or homologous clock information.
The cross-clock domain processing circuit according to any one of claims 1 to 6, wherein the cross-clock domain processing circuit further includes a first clock circuit, and the first clock circuit is used for the phase alignment circuit The first working clock is provided.
The cross-clock domain processing circuit according to claims 1 to 7, wherein the cross-clock domain processing circuit further comprises a clock recovery circuit, wherein:

The clock recovery circuit is used to receive the input data, recover the clock in the input data to obtain the input data clock and the first control signal, and output the input data, the input data clock and The first control signal.
The cross-clock domain processing circuit according to any one of claims 1 to 8, wherein the synchronization circuit includes a first sub-synchronization circuit and a second sub-synchronization circuit, wherein:

The first sub-synchronization circuit is used to synchronize the input data according to the input data clock to obtain first temporary data;

The second sub-synchronization circuit is used to synchronize the first temporary data according to the output data clock to obtain the synchronization data.
The cross-clock domain processing circuit according to claim 9, wherein the first sub-synchronous circuit and the second sub-synchronous circuit are registers, and the first operating clock of the first sub-synchronous circuit is The input data clock, the first working clock of the second sub-synchronous circuit is the output data clock.
The cross-clock domain processing circuit according to any one of claims 1 to 10, wherein the input data is serial data, wherein:

The cross-clock domain processing circuit further includes a serial-to-parallel circuit, which is used for serial-to-parallel conversion of the input data, and outputs the converted input data to the synchronization circuit.
A retimer is used to relay N input data in a transmission link. The retimer includes: a phase alignment circuit and N synchronization circuits, where N≥1 and N is Positive integer, where:

The phase alignment circuit is used for receiving an input data clock and a first working clock, adjusting the phase of the first working clock according to a first control signal, and outputting the phase adjusted first working clock as an output data clock to all In the N synchronization circuits, the phase of the output data clock is aligned with the phase of the input data clock, and the input data clock is one of the N recovered data clocks recovered from the N input data , The first working clock is the working clock of the retimer, and the frequency of the first working clock is equal to the frequency of the input data clock, and the first control signal is based on the N input data One of the recovered N control signals, the first control signal includes phase change information of the input data clock;

Each of the N synchronization circuits is used to synchronize each input data of the N input data according to the input data clock and the output data clock to generate N channels One channel of synchronous data in the synchronous data, the N channels of synchronous data are in the clock domain of the output data clock.
The retimer according to claim 12, wherein the phase alignment circuit includes a phase discriminator, a digital filter, and a phase interpolator, wherein:

The phase discriminator is used to discriminate the input data clock and the output data clock, and output a phase discrimination result;

The digital filter is used to filter and shake the phase discrimination result and the first control signal, and output the filtered result as a second control signal to the phase interpolator;

The phase interpolator is used to adjust the phase of the first working clock according to the second control signal, so that the phase of the first working clock is aligned with the phase of the input data clock, and the phase adjusted The first working clock is output as the output data clock to the N synchronization circuits and the phase detector.
The retimer according to claim 13, wherein the phase interpolator is further used to:

Generating a second intermediate clock according to the first working clock, and the phase difference between the first working clock and the second intermediate clock is a preset phase difference;

Adjusting the phases of the first working clock and the second intermediate clock according to the second control signal, so that the phase of the input data clock leads the phase of the first working clock and lags the second intermediate The phase of the clock.

The phase detector is further used for:

Phase-identify the output data clock, the second intermediate clock, and the input data clock, and determine the phase relationship of the output data clock, the second intermediate clock, and the input data clock to output the Phase comparison results.
The retimer of claim 14, wherein the phase interpolator is further used to:

When the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is used to instruct the phase interpolator to maintain the first The phase of the working clock and the second intermediate clock;

When the phase of the input data clock lags behind the phase of the first working clock and the phase of the second intermediate clock, the second control signal is used to instruct the phase interpolator to adjust the first operation The phase of the clock and the second intermediate clock, so that the phase of the input data clock leads the phase of the first working clock and lags the phase with the second intermediate clock;

When the phase of the input data clock leads the phase of the first working clock and the phase of the second intermediate clock, the second control signal is used to instruct the phase interpolator to adjust the first operation The phase of the clock and the second intermediate clock, such that the phase of the input data clock leads the phase of the first working clock and lags the phase with the second intermediate clock.
The retimer according to any one of claims 13 to 15, wherein the digital filter filters the first control signal and the phase discrimination result as high frequency filter jitter, where the filter jitter The subsequent first control signal includes phase change information corresponding to the low frequency jitter of the input data clock.
The retimer according to claim 16, wherein the phase change information includes independent clock spreading information, independent clock non-spreading information, or homologous clock information.
The retimer according to any one of claims 12 to 17, wherein the retimer further comprises a first clock circuit, and the first clock circuit is used to provide the phase alignment circuit with the first One working clock.
The retimer according to claims 12 to 18, wherein the retimer further comprises N clock recovery circuits, wherein:

The N clock recovery circuits are respectively used to receive the N input data and recover the clocks in the N input data to obtain the N recovered data clocks and the N first control signals, and Output the N input data, the N recovered data clocks, and the N control signals.
The retimer according to any one of claims 12 to 19, wherein the synchronization circuit includes a first sub-synchronization circuit and a second sub-synchronization circuit, wherein:

The first sub-synchronization circuit is used to synchronize the input data according to the input data clock to obtain first temporary data;

The second sub-synchronization circuit is used to synchronize the first temporary data according to the output data clock to obtain the synchronization data.
The retimer of claim 20, wherein the first sub-synchronization circuit and the second sub-synchronization circuit are registers, wherein the first operating clock of the first sub-synchronization circuit is the input The data clock, the first working clock of the second sub-synchronous circuit is the output data clock.
The retimer according to any one of claims 12 to 21, wherein the N-channel input data is N-channel serial data, wherein:

The retimer further includes N serial-to-parallel circuits, characterized in that the N serial-to-parallel circuits are used to serially and parallel convert the N input data, respectively, and output the converted N Input data to the N synchronization circuits.
The retimer according to any one of claims 12 to 22, wherein the N-channel synchronization data is N-channel parallel data, wherein:

The retimer also includes N parallel-to-serial circuits, characterized in that the N parallel-to-serial circuits are respectively used to convert the N channels of synchronous data into N channels of serial output data, and output the converted The N channels output data serially.
The retimer according to any one of claims 19 to 23, wherein the retimer further includes N data processing circuits and N data selectors, wherein:

The input terminals of the N data processing circuits are respectively coupled to the output terminals of the N clock recovery circuits, and the output terminals of the N data processing circuits are respectively coupled to the input terminals of the N data selectors. N data processing circuits are used for decoding, descrambling, synchronizing, scrambling and encoding the received N input data respectively;

For each of the data processing circuit, the clock recovery circuit, and the data selector coupled to each other, wherein:

The two input terminals of the data selector are respectively coupled to the output terminal of the clock recovery circuit and the output terminal of the data processing circuit, and the output terminal of the data selector is coupled to the output terminal of the synchronization circuit.
The retimer according to any one of claims 12 to 24, wherein the retimer is a multi-channel retimer, where N ≥ 2, and N is a positive integer.