CN109143907B - Synchronous sampling system and automatic phase selection method - Google Patents
Synchronous sampling system and automatic phase selection method Download PDFInfo
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Abstract
The present invention provides a kind of synchronous sampling system and automatic phase selection method, comprising: exports the sending module of synchronous data-signal to be received and clock signal to be received；The phase of data-signal to be received is determined based on clock signal to be received, and the clock data Phase synchronization module that the phase adjustment receiving end sampled clock signal based on clock signal to be received is synchronous with data-signal to be received；To the receiving module of data-signal synchronized sampling to be received.Obtain synchronous clock signal to be received and data-signal to be received；The phase of clock signal to be received is detected, and adjusts receiving end sampled clock signal, so that receiving end sampled clock signal is synchronous with data-signal to be received.The present invention is determined data signal phase, is kept receiving end sampled clock signal synchronous with data waiting, achieve the purpose that timing closure by the phase change of detection sampled clock signal, is greatly improved the accuracy of data transmission, is provided safeguard for high speed data transfer.
Description
Technical field
The present invention relates to chip design fields, more particularly to a kind of synchronous sampling system and automatic phase selection method.
Background technique
Data transmission needs to provide data-signal and the clock signal synchronous with data-signal, can realize accurate data
Transmission；Nonsynchronous data-signal and clock signal will lead to the data-signal inaccuracy sampled or mistake occur, influence to count
According to the quality of transmission.With the rapid development of information technology, the transmission rate of data is getting faster, high speed (such as 10GHz with
On) in data transmission, due to the uncertainty that clock signal and data-signal are delayed, lead to rear class synchronous circuit it is difficult to ensure that adopting
The phase relation of sample clock edge and data still meets timing closure condition, and then directly affects the accuracy of synchronized sampling, because
This, high-speed data synchronize middle data-signal and clock signal synchronize be particularly important.
As shown in Figure 1, existing high-speed data synchronous sampling system 1, comprising: the first d type flip flop 11 and the second d type flip flop
12.Clock signal sampling clock as first d type flip flop 11 after the first delay 13, data-signal is based on described the
One d type flip flop 11 is sampled in the rising edge of sampling clock, at this point, data-signal and clock signal synchronization；The first D triggering
The data-signal that device 11 exports is output to the data input pin of second d type flip flop 12, clock letter after third delay 15
The input end of clock of second d type flip flop 12 is output to via the second delay 14 number again, since the second delay 14 is prolonged with third
When 15 be difficult to match, therefore, the data-signal that the second d type flip flop 12 receives is asynchronous with sampling clock, as shown in Figure 1, adopting
The rising edge or failing edge of the rising edge corresponding data signal of sample clock, and in fact, the rising edge of sampling clock should correspond to number
It is believed that number center (i.e. the rising edge of sampling clock shown in dotted line)；When the rising edge corresponding data signal of sampling clock
When rising edge or failing edge, collected data are only edge, and are not real data, lead to the mistake of sampled result.
Therefore, how to realize that data-signal is synchronous with clock signal in high-speed data synchronous sampling system, guarantee sampling
The phase relation of clock edge and data meets timing closure condition, improves data sampling accuracy, it has also become those skilled in the art
One of member's urgent problem to be solved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of synchronous sampling system and automatically
Phase selection method, when for solution, high-speed data is synchronous in the prior art, clock signal and data-signal are asynchronous, influence to count
The problem of according to transmission quality.
In order to achieve the above objects and other related objects, the present invention provides a kind of synchronous sampling system, the synchronized sampling
System includes at least:
Sending module, exports data-signal to be received and clock signal to be received, the clock signal to be received and described
Data-signal to be received is synchronous；
Clock data Phase synchronization module is connected to the output end of the sending module, detects the clock letter to be received
Number phase, and the phase of the phase adjustment receiving end sampled clock signal based on the clock signal to be received, so that described
Receiving end sampled clock signal is synchronous with the data-signal to be received；
Receiving module receives the data-signal to be received and the receiving end sampled clock signal, to realize reception mould
The synchronized sampling of block end data signal；
Wherein, the clock data Phase synchronization module includes that multiphase clock generates unit, phase matching components, phase demodulation
Unit and phase selection unit；
Original clock signal obtains delay clock signal through the 4th path delay；
The multiphase clock generates unit and receives the delay clock signal, passes through phase based on the delay clock signal
Position interpolation generate multiple and different phases phase demodulation clock signal and sampled clock signal to be selected；
The phase matching components receive the clock signal to be received, carry out phase tune to the clock signal to be received
It is whole, so that the phase of the phase matched clock signal of phase matching components output and the sampled clock signal to be selected
Match；
The phase demodulation unit is connected to the phase matching components and the multiphase clock generates the output end of unit, base
Phase-detection, and output phase selection letter are carried out to the clock signal to be received in the phase demodulation clock signal of multiple and different phases
Number；
The phase selection unit is connected to the output end that the multiphase clock generates unit and the phase demodulation unit, root
According to the phase selection signal, selected from the sampled clock signal to be selected matched with the clock signal phase to be received
Signal is as the receiving end sampled clock signal.
Optionally, the sending module includes frequency unit, the first sampling unit and timelag matching unit；
Original clock signal inputs the frequency unit after first path is delayed, and transmitting terminal sampling is obtained after two divided-frequency
Clock signal；
The data input pin of first sampling unit receives to be sent described in data-signal to be sent, clock input
Sampled clock signal is held, and based on data-signal to be sent described in the transmitting terminal sampled clock signal synchronized sampling；
The output signal of first sampling unit obtains the data-signal to be received through the second path delay；
The timelag matching unit receives the transmitting terminal sampled clock signal, to the transmitting terminal sampled clock signal into
Line delay；
The output signal of the timelag matching unit obtains the clock signal to be received through third path delay.
More optionally, first sampling unit is d type flip flop.
Optionally, it includes frequency dividing circuit and phase interpolation circuit that the multiphase clock, which generates unit,；The frequency dividing circuit
The delay clock signal is received, two divided-frequency is carried out to the delay clock signal, obtains sampled clock signal to be selected；The phase
Position interpolating circuit is connected to the output end of the frequency dividing circuit, carries out phase interpolation to the output signal of the frequency dividing circuit and obtains
The phase demodulation clock signal.
Optionally, the phase demodulation unit includes sample circuit and phase detecting circuit；Wherein, the sample circuit is based on institute
Phase demodulation clock signal is stated to sample the phase matched clock signal；The phase detecting circuit is connected to the sampling electricity
The output end on road patrols the positive phase signals of previous position in adjacent two even level sampled signals and the inversion signal of latter position
Volume and operation, to obtain the phase selection signal.
More optionally, the phase selection unit includes multiple gating circuits, and the input signal of each gating circuit is respectively
The control signal of each sampled clock signal to be selected, each gating circuit connects the phase selection signal corresponding with input signal,
Output end of the output end of each gating circuit as the phase selection unit.
More optionally, the gating circuit includes:
Input terminal connects the first gated inverter and the second gated inverter of the sampled clock signal to be selected, and described
The control terminal of one gated inverter connects the positive output signal of the corresponding phase demodulation unit, second gated inverter
Control terminal connects the reversed-phase output signal of the corresponding phase demodulation unit；
Source electrode connects the first PMOS tube and the second PMOS tube of power supply, the first gate of grid connection of first PMOS tube
The control signal of phase inverter, drain electrode connect the output end of first gated inverter；The grid of second PMOS tube connects
Output end of the output end, drain electrode of first gated inverter as the gating circuit；
The first NMOS tube and the second NMOS tube of source electrode ground connection, grid connection the second gate reverse phase of first NMOS tube
The control signal of device, drain electrode connect the output end of second gated inverter；Described in the grid connection of second NMOS tube
Output end of the output end, drain electrode of second gated inverter as the gating circuit.
Optionally, the receiving module includes the second sampling unit, and the data input pin of second sampling unit receives
Receiving end sampled clock signal described in the data-signal to be received, clock input, and sampled based on the receiving end
Clock signal synchronization samples the data-signal to be received.
More optionally, second sampling unit is d type flip flop.
In order to achieve the above objects and other related objects, the present invention provides a kind of automatic phase of above-mentioned synchronous sampling system
Selection method, the automatic phase selection method include at least:
Obtain synchronous clock signal to be received and data-signal to be received；
The phase of the clock signal to be received is detected, with the phase of the determination data-signal to be received；
Based on the phase adjustment receiving end sampled clock signal of the clock letter to be received detected, so that the reception
Hold sampled clock signal synchronous with the data-signal to be received.
Optionally, transmitting terminal sampled clock signal and data-signal to be sent obtained after delay matching it is synchronous described in
Clock signal to be received and the data-signal to be received.
Optionally it is determined that the step of data signal phase to be received, includes:
The phase demodulation clock signal of multiple and different phases is generated based on the original clock signal by path delay and to be selected is adopted
Sample clock signal；
Phase demodulation clock signal pair and the phase demodulation clock signal phase that multiple and different phases are respectively adopted are matched described
Clock signal to be received is sampled, and the phase of the clock signal to be received, and then acquisition and institute are determined according to sampled result
State the phase of the data-signal to be received of clock signal synchronization to be received.
More optionally, the step of adjusting the receiving end sampled clock signal include:
According to the phase of the clock signal to be received, from the sampled clock signal to be selected of multiple and different phases selection with
The matched signal of clock signal phase to be received is as the receiving end sampled clock signal.
As described above, synchronous sampling system and automatic phase selection method of the invention, have the advantages that
Synchronous sampling system and automatic phase selection method of the invention passes through the phase change of detection sampled clock signal,
It determines data signal phase, keeps receiving end sampled clock signal synchronous with data waiting, achieve the purpose that timing closure, mention significantly
The accuracy of high data transmission, provides safeguard for high speed data transfer.
Detailed description of the invention
Fig. 1 is shown as the structural schematic diagram of high-speed data synchronous sampling system in the prior art.
Fig. 2 is shown as the structural schematic diagram of synchronous sampling system of the invention.
Fig. 3 is shown as the structural schematic diagram that multiphase clock of the invention generates unit.
Fig. 4 is shown as the structural schematic diagram of phase interpolation circuit of the invention.
Fig. 5 is shown as the structural schematic diagram of phase interpolation pre-regulator of the invention.
Fig. 6 is shown as the structural schematic diagram of phase interpolator of the invention.
Fig. 7 is shown as the structural schematic diagram of phase matching components of the invention.
Fig. 8 is shown as the structural schematic diagram of phase demodulation unit of the invention.
Fig. 9 is shown as the structural schematic diagram of phase selection unit of the invention.
Figure 10 is shown as the structural schematic diagram of gating circuit of the invention.
Figure 11 is shown as the structural schematic diagram of door control phase inverter of the invention.
Figure 12 is shown as the schematic illustration of automatic phase selection method of the invention.
Component label instructions
1, high-speed data synchronous sampling system
11, the first d type flip flop
12, the second d type flip flop
13, the first delay
14, the second delay
15, third delay
2, synchronous sampling system
21, sending module
211, frequency unit
212, the first sampling unit
213, timelag matching unit
214, first path delay
215, the second path delay
216, third path delay
22, clock data Phase synchronization module
221, multiphase clock generates unit
221a, frequency dividing circuit
221b, phase interpolation circuit
222, phase matching components
223, phase demodulation unit
223a, sample circuit
223b, phase detecting circuit
224, phase selection unit
224a ~ 224d, the first ~ the 4th gating circuit
225, the 4th path delay
23, receiving module
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 2 ~ Figure 12.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 2, the present invention provides a kind of synchronous sampling system 2, the synchronous sampling system 2 includes:
Sending module 21, clock data Phase synchronization module 22 and receiving module 23.
As shown in Fig. 2, the sending module 21 exports data-signal data_r to be received and clock signal ck_r to be received,
The clock signal ck_r to be received is synchronous with the data-signal data_r to be received.
Specifically, in the present embodiment, the sending module 21 includes frequency unit 211, the first sampling unit 212 and prolongs
When matching unit 213.More specifically, two speed clock signal of original clock signal ck() connect after first path delay 214
The input terminal for connecing the frequency unit 211 obtains transmitting terminal sampled clock signal ck_ after 211 two divided-frequency of frequency unit
samps.The phase of the transmitting terminal sampled clock signal ck_samps is with the 212 data input pin D's of the first sampling unit
Data-signal data_s to be sent is synchronous.
Refer to sampling clock along (rising edge or decline for sampling it should be noted that the signal in the present invention synchronizes
Edge) it is located at the central area of data-signal, data-signal can accurately be collected by being subject to；Under normal circumstances, sampling clock edge is got over
Center close to data-signal is better.
More specifically, in the present embodiment, first sampling unit 212 is d type flip flop, in practical applications, arbitrarily
The circuit structure that data sampling can be achieved is suitable for the present invention, will not repeat them here.The number of first sampling unit 212
The data-signal data_s to be sent is received according to input terminal D；The input end of clock CK of first sampling unit 212 receives institute
State transmitting terminal sampled clock signal ck_samps；And based on described in the transmitting terminal sampled clock signal ck_samps synchronized sampling
Data-signal data_s to be sent.Due to the data-signal data_s to be sent and the transmitting terminal sampled clock signal ck_
Samps is synchronous, and the sampling clock of the transmitting terminal sampled clock signal ck_samps is along positioned at the data-signal to be sent
The central area of data_s accurately acquires the data-signal data_s to be sent.
More specifically, the output signal of first sampling unit 212 by the second path delay 215 obtain it is described waiting
Receive data-signal data_r.
More specifically, the timelag matching unit 213 receives the transmitting terminal sampled clock signal ck_samps, to described
Transmitting terminal sampled clock signal ck_samps is delayed.
More specifically, the output signal of the timelag matching unit 213 by third path delay 216 obtain it is described waiting
Receive clock signal ck_r, based on the adjustment of the timelag matching unit 213, the clock signal ck_r to be received with it is described waiting
It receives data-signal data_r and still maintains synchronized relation.
It should be noted that first path is delayed, the 214, second path delay 215 and third path delay 216 are transmission road
The delay introduced on diameter, is not present specific structure in actual circuit, and the present embodiment indicates for ease of description.
As shown in Fig. 2, the clock data Phase synchronization module 22 is connected to the output end of the sending module 21, detection
The phase of the clock signal ck_r to be received, and the phase of receiving end sampled clock signal ck_sampr is adjusted, so that described
Receiving end sampled clock signal ck_sampr is synchronous with the data-signal data_r to be received.The clock data Phase synchronization
Module 22 includes that multiphase clock generates unit 221, phase matching components 222, phase demodulation unit 223 and phase selection unit 224.
Specifically, the original clock signal ck obtains delay clock signal ck_delay by the 4th path delay 225.
It should be noted that the 4th path delay 225 is the delay introduced in transmission path, it is not present in actual circuit
Specific structure, the present embodiment indicate for ease of description.
Specifically, the multiphase clock generates unit 221 and receives the delay clock signal ck_delay, based on described
Delay clock signal ck_delay generates the phase demodulation clock signal ph<7:0>and sampled clock signal to be selected of multiple and different phases
ck_ph<3:0>.As shown in figure 3, it includes frequency dividing circuit 221a and phase interpolation circuit that the multiphase clock, which generates unit 221,
221b。
More specifically, the frequency dividing circuit 221a receives the delay clock signal ck_delay, to the delay clock
Signal ck_delay carries out two divided-frequency, obtains sampled clock signal ck_ph<3:0>to be selected, in the present embodiment, described to be selected to adopt
Sample clock signal ck_ph<3:0>is one group of orthogonal signalling and its inverted signal, and totally 4, everybody successively differs 90 °.
More specifically, the phase interpolation circuit 221b is connected to the output end of the frequency dividing circuit 221a, to described point
The output signal of frequency circuit 221a carries out phase interpolation and obtains the phase demodulation clock signal ph<7:0>, in the present embodiment, described
Phase demodulation clock signal ph<7:0>is one group of 8 signal, everybody successively differs 45 °, and institute can be set as needed in actual use
State the digit of phase demodulation clock signal ph<7:0>.As shown in figure 4, the phase interpolation circuit 221b includes that multiple phase interpolations are pre-
Adjuster and multiple phase interpolators, in the present embodiment, including 4 phase interpolation pre-regulators and 8 phase interpolators, it can
Particular number is set as needed, wherein the input terminal of each phase interpolation pre-regulator is separately connected the sampling clock to be selected
Everybody in signal ck_ph<3:0>, controls for the time to rising edge and failing edge；The input of each phase interpolator
End is separately connected the output signal of each phase interpolation pre-regulator or the output signal of two neighboring phase interpolation pre-regulator,
For realizing phase interpolation.
As shown in figure 5, the first phase interpolation pre-regulator includes third by taking first phase interpolation pre-regulator as an example
PMOS tube P3, the 4th PMOS tube P4, the 5th PMOS tube group P5, third NMOS tube N3, the 4th NMOS tube N4 and the 5th NMOS tube group
N5.The third PMOS tube P3 connect to form inverter structure with the third NMOS tube N3, and input terminal connection first is to be selected to adopt
Sample clock signal ck_ph<0>；The 4th PMOS tube P4 connect the third PMOS tube with the grid of the 4th NMOS tube N4
The drain electrode of P3 and the third NMOS tube N3, the 5th PMOS tube group P5 are connected to the source electrode of the 4th PMOS tube P4, lead to
The conducting that control signal Enb<N:0>controls each PMOS tube in the 5th PMOS tube group P5 is crossed, and then adjusts the first phase
The pull-up ability of interpolation pre-regulator, the 5th NMOS tube group N5 are connected to the source electrode of the 4th NMOS tube N4, pass through control
Signal En<N:0>processed controls the conducting of each NMOS tube in the 5th NMOS tube group N5, and then adjusts the second phase interpolation
The pull-down capability of pre-regulator.The structure of second ~ the 4th phase interpolation pre-regulator is identical, will not repeat them here.
As shown in fig. 6, by taking first phase interpolater as an example, the first phase interpolater include the first phase inverter not1,
Second phase inverter not2 and third phase inverter not3.The input terminal of the first phase inverter not1 and the second phase inverter not2
Connect the output signal (ph1 and ph2) of the first phase interpolation pre-regulator and the second phase interpolation pre-regulator；Institute
The output end for stating the first phase inverter not1 and the second phase inverter not2 connects the input terminal of the third phase inverter not3, institute
State output end of the output end of third phase inverter not3 as the first phase interpolater, the first phase interpolater output
The phase of the first phase demodulation clock signal ph<0>be located between two input signals, if two input signals are identical, export letter
Number phase it is consistent with input signal.The structure of the second ~ the eight-phase interpolater is identical, will not repeat them here.
It should be noted that the phase intervals of the phase demodulation clock signal ph<7:0>of leggy are smaller, the phase demodulation list
The resolution ratio of member 223 is higher, but its power consumption and circuit area can also increase therewith, in actual use, can weigh as needed
Relationship between resolution ratio and power consumption, area, and then the quantity of the phase demodulation clock signal ph<7:0>is set, not with this implementation
Example is limited.The phase demodulation clock signal for generating leggy the present invention is based on the mode of phase interpolation (is not limited to 8, is equally applicable to
16 or more), it is greatly improved the resolution ratio of the clock of phase demodulation clock signal, is provided safeguard for high speed data transfer.
Specifically, the phase matching components 222 receive the clock signal ck_r to be received, to the clock to be received
Signal ck_r carry out phase adjustment so that the phase matching components 222 export phase matched clock signal ck_sync with
The phase matched of the sampled clock signal ck_ph<3:0>to be selected.
More specifically, as shown in fig. 7, the phase matching components 222 include the 5th phase interpolation pre-regulator and the 9th
The input terminal of phase interpolator, the 5th phase interpolation pre-regulator connects the clock signal ck_r to be received, output end
The input terminal of the 9th phase interpolator is connected, the 9th phase interpolator output phase matches clock signal ck_sync.
The structure of the 5th phase interpolation pre-regulator is identical as the structure of the first phase interpolation pre-regulator, the 9th phase
The structure of position interpolater is identical as the structure of the first phase interpolater, will not repeat them here.
Specifically, the phase demodulation unit 223 is connected to the phase matching components 222 and the multiphase clock generates list
The output end of member 221, the phase demodulation clock signal ph<7:0>based on multiple and different phases is to the phase matched clock signal ck_
Sync carries out phase-detection, and output phase selection signal ck_ph_sel<3:0>.
More specifically, as shown in figure 8, the phase demodulation unit 223 include sample circuit 223a and phase detecting circuit 223b,
Wherein, the sample circuit 223a is based on the phase demodulation clock signal ph<7:0>to the phase matched clock signal ck_sync
It is sampled；The phase detecting circuit 223b is connected to the output end of the sample circuit 223a, to adjacent two even levels
The inversion signal of the positive phase signals of previous position and latter position carries out logic and operation in sampled signal, to obtain the Selecting phasing
Signal ck_ph_sel<3:0>.
As shown in figure 8, the sample circuit 223a includes 4 groups of d type flip flops, wherein first group of d type flip flop DFF1, second
Group d type flip flop DFF2, third group d type flip flop DFF3 and the 4th group of d type flip flop DFF4 respectively include 8 d type flip flops.First group of D
The data terminal D connection phase matched clock signal ck_sync of trigger DFF1, when clock end CK is separately connected the phase demodulation
Everybody in clock signal ph<7:0>；The data terminal D of second group of d type flip flop DFF2 is separately connected first group of d type flip flop
The positive output end of DFF1, clock end CK are separately connected everybody in the phase demodulation clock signal ph<7:0>；The third group D
The data terminal D connection calibration signal cal_start(external start signal of trigger DFF3), clock end CK is separately connected the mirror
Everybody in clock signal ph<7:0>；The data terminal D of the 4th group of d type flip flop DFF4 is separately connected second group of D touching
The positive output end of device DFF2 is sent out, clock end CK is separately connected the positive output end of the third group d type flip flop DFF3, and described the
The positive output end output phase sampled signal ph_samp_pre<7:0>of four groups of d type flip flop DFF4, reversed-phase output output phase
Position sampling inverted signal ph_sampb_pre<7:0>；The third group d type flip flop DFF3's and the 4th group of d type flip flop DFF4
Reset terminal connects reset signal rstb.
As shown in figure 8, the phase detecting circuit 223b includes 4 logical AND gates (two input), wherein the first logical AND
Two input terminals of door and1 are separately connected eight-phase sampled signal ph_samp_pre<7>and second phase sampling inverted signal
Ph_sampb_pre<1>carries out the two and is exported after operation as a result, i.e. the two is 1 output high level, to judge the phase
The last time whether failing edge of position matching clock signal ck_sync is located at previous cycle samples second with current period
Between sampling.Similarly, the input terminal of the second logical AND gate and2 is separately connected second phase sampled signal ph_samp_pre<1>
And the 4th phase sample inverted signal ph_sampb_pre<3>；The input terminal of third logical AND gate and3 is separately connected the 4th phase
Sampled signal ph_samp_pre<3>and the 6th phase sample inverted signal ph_sampb_pre<5>；4th logical AND gate and4's
Input terminal be separately connected the 6th phase sample signal ph_samp_pre<6>and eight-phase sampling inverted signal ph_sampb_pre<
7>；Principle is identical to be will not repeat them here.
In the present embodiment, the phase demodulation unit 223 is based on the phase demodulation clock signal ph<7:0>of multiple and different phases to institute
It states clock signal ck_r to be received to be sampled, i.e., the clock signal ck_r to be received in each period adopt for eight times
Sample indicates the clock signal ck_r to be received of a cycle by eight continuous signals, and the level between continuous signal becomes
Change the rising edge or failing edge for having reacted the clock signal ck_r to be received, eight companies that the phase demodulation unit 223 samples
In continuous level, the failing edge that low level process corresponds to the clock signal ck_r to be received is jumped to from high level；From low
The process of level jump to high level is the rising edge of the corresponding clock signal ck_r to be received.
Specifically, the phase selection unit 224 is connected to the multiphase clock and generates unit 221 and the phase demodulation list
The output end of member 223, according to the phase selection signal ck_ph_sel<3:0>, from the sampling clock to be selected of multiple and different phases
It selects to sample with the signal of the clock signal ck_r phase matched to be received as the receiving end in signal ck_ph<3:0>
Clock signal ck_sampr.The rising edge or failing edge of the clock signal ck_r to be received is between jump level, it is assumed that
In the present embodiment, sampled signal is 11110000 in the phase demodulation unit 223, then it represents that in the 4th phase and the 6th phase
Detect the failing edge of the clock signal ck_r to be received between position, the phase selection unit 224 is from the sampling to be selected
Failing edge is selected in clock signal ck_ph<3:0>to be located between corresponding 4th phase ~ six phase of the sampled signal
For failing edge the sampled clock signal to be selected as the receiving end sampled clock signal ck_sampr, realized with this described
Clock signal ck_r to be received is consistent with the phase of the receiving end sampled clock signal ck_sampr, due to it is described to be received when
Clock signal ck_r is synchronous with the data-signal data_r to be received, therefore, the data-signal data_r to be received with it is described
Receiving end sampled clock signal ck_sampr is synchronous.
More specifically, the phase selection unit 224 includes multiple gating circuits, as shown in figure 9, in the present embodiment,
Including 4 gating circuits.The input signal of each gating circuit is separately connected the sampled clock signal ck_ph<3:0>to be selected, respectively
The control signal of gating circuit connects the phase selection signal ck_ph_sel<3:0>corresponding with input signal, each gating electricity
The output end on road connects same buffer circuit buf.The present embodiment is by taking the first gating circuit 224a as an example, first gating circuit
The input terminal of 224a connects the first sampled clock signal ck_ph<0>to be selected, and end is selected to connect first phase selection signal ck_ph_
Sel<0>, as shown in Figure 10, the first gating circuit 224a include the first gated inverter not4, the second gated inverter
Not5, the 4th phase inverter not6, the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2.It is described
The sampling clock letter to be selected of the input terminal of first gated inverter not4 and the second gated inverter not5 connection described first
The control terminal of number ck_ph<0>, the first gated inverter not4 connect the corresponding first phase selection signal ck_ph_
The control terminal of sel<0>, the second gated inverter not5 are selected through the 4th phase inverter not6 connection first phase
Signal ck_ph_sel<0>；The source electrode of the first PMOS tube P1 connects power supply, and grid connects the first phase selection signal
Ck_ph_sel<0>, drain electrode connect the output end of the first gated inverter not4；The source electrode of the second PMOS tube P2 connects
Power supply is connect, grid connects the output end of the first gated inverter not4, drains as the first gating circuit 224a's
Output end；The source electrode of the first NMOS tube N1 is grounded, and grid connects the first phase selection signal ck_ph_sel<0>
Inverted signal, drain electrode connect the output end of the second gated inverter not5；The source electrode of the second NMOS tube N2 is grounded, grid
The output end of the second gated inverter not5 is connected, the output end to drain as the first gating circuit 224a.Wherein,
The structure of the first gated inverter not4 and the second gated inverter not5 are as shown in figure 11, including what is be sequentially connected in series
6th PMOS tube P6, the 7th PMOS tube P7, the 6th NMOS tube N6 and the 7th NMOS tube N7, the 7th PMOS tube P7 and described
The grid connection input signal of six NMOS tube N6, drain electrode are used as output end, the grid connection selection letter of the 7th NMOS tube N7
Number, the grid of the 6th PMOS tube P6 is based on the hex inverter not6 connection selection signal.Second ~ the 4th gating circuit
Structure it is identical as the structure of first gating circuit, will not repeat them here.
As shown in Fig. 2, the receiving module 23 receives the data-signal data_r to be received and receiving end sampling
Clock signal ck_sampr, to realize the synchronized sampling of receiving module end data signal.
Specifically, the receiving module 23 includes the second sampling unit, and in the present embodiment, second sampling unit is
D type flip flop, in practical applications, the circuit structure of any achievable data sampling are suitable for the present invention, do not go to live in the household of one's in-laws on getting married one by one herein
It states.
More specifically, the data input pin D of second sampling unit receives the data-signal data_r to be received；Institute
The input end of clock CK for stating the second sampling unit connects the output end of the sending module 21, receives the receiving end sampling clock
Signal ck_sampr；And based on data-signal to be received described in the receiving end sampled clock signal ck_sampr synchronized sampling
data_r.It is described since the data-signal data_r to be received is synchronous with the receiving end sampled clock signal ck_sampr
The sampling clock edge of receiving end sampled clock signal ck_sampr is located at the central area of the data-signal data_r to be received,
Accurately acquire the data-signal data_r to be received.
The present invention also provides a kind of automatic phase selection methods, in the present embodiment, the automatic phase selection method base
It is realized in the synchronous sampling system 2, is not limited to physical circuit of the invention in actual use.The automatic phase selecting party
Method includes:
1) synchronous clock signal ck_r to be received and data-signal data_r to be received are obtained.
Specifically, transmitting terminal sampled clock signal ck_samps is with data-signal data_s to be sent after delay matches
The synchronous clock signal ck_r to be received and the data-signal data_r to be received is obtained, is based on this described to be received
Clock signal ck_r obtains the phase information of the data-signal data_r to be received.
2) phase of the clock signal ck_r to be received is detected, with the phase of the determination data-signal data_r to be received
Position.
Specifically the following steps are included:
21) based on the original clock signal ck by path delay generate the phase demodulation clock signal ph of multiple and different phases <
7:0>and sampled clock signal ck_ph to be selected<3:0>.As shown in figure 12, in the present embodiment, the sampled clock signal to be selected
Ck_ph<3:0>is obtained after the delay clock signal ck_delay two divided-frequency, and each sampled clock signal to be selected differs 45 °；Institute
The phase average for stating every signal in phase demodulation clock signal ph<7:0>was distributed in a clock cycle, i.e., with the delay when
On the basis of clock signal ck_delay, each phase demodulation clock signal ph<7:0>lags behind the delay clock signal ck_ respectively
delay45°,90°,135°,180°,225°,270°,315°,360°.In actual use, the mirror can be set as needed
The quantity and phase difference of clock signal ph<7:0>and the sampled clock signal ck_ph<3:0>to be selected.
22) be respectively adopted the phase demodulation clock signal ph<7:0>of multiple and different phases to phase demodulation clock signal ph<7:
The clock signal ck_r to be received of 0 > phase matched is sampled, and determines the clock signal to be received according to sampled result
The phase of ck_r, and then obtain the phase of the to be received data-signal data_r synchronous with the clock signal ck_r to be received.
In the present embodiment, second phase selection signal ck_ph_sel<1>jump that the phase demodulation unit 223 exports is high level, i.e.,
The failing edge of the clock signal ck_r to be received is located at the second phase demodulation clock signal ph<1>(45 °) and the 4th phase demodulation clock is believed
Between number ph<3>(135 °), and then determine the phase of the clock signal ck_r to be received.
3) the phase adjustment receiving end sampled clock signal ck_sampr based on the clock signal ck_r to be received, so that
The receiving end sampled clock signal ck_sampr is synchronous with the data-signal data_r to be received.
Specifically, according to the phase of the clock signal ck_r to be received, from the sampling clock to be selected of multiple and different phases
It selects to sample with the signal of the clock signal ck_r phase matched to be received as the receiving end in signal ck_ph<3:0>
Clock signal ck_sampr.In the present embodiment, by the second sampled clock signal ck_ph<1>(failing edge is located at 90 °) choosing to be selected
Out, as the receiving end sampled clock signal ck_sampr, so that the receiving end sampled clock signal ck_sampr
Sampling clock is along the central area for being located at the data-signal data_r to be received.
Synchronous sampling system and automatic phase selection method of the invention is based on synchronous with data-signal data_r to be received
Clock signal ck_r to be received detect the phase change of data-signal data_r to be received, receiving end sampling clock is believed automatically
Number ck_sampr is adjusted to synchronous with data-signal data_r to be received, achievees the purpose that timing closure with this.
In conclusion the present invention provides a kind of synchronous sampling system and automatic phase selection method, comprising: sending module,
Data-signal to be received and clock signal to be received are exported, the clock signal to be received and the data-signal to be received are same
Step；Clock data Phase synchronization module is connected to the output end of the sending module, detects the phase of the clock signal to be received
Position, and the phase of receiving end sampled clock signal is adjusted, so that the receiving end sampled clock signal and the data to be received
Signal is synchronous；Receiving module receives the data-signal to be received and the receiving end sampled clock signal, to realize reception mould
The synchronized sampling of block end data signal.Obtain synchronous clock signal to be received and data-signal to be received；It detects described waiting
The phase of clock signal is received, with the phase of the determination data-signal to be received；Based on the clock letter to be received detected
Number phase adjustment receiving end sampled clock signal so that the receiving end sampled clock signal and the data-signal to be received
It is synchronous.Synchronous sampling system and automatic phase selection method of the invention passes through the phase change of detection sampled clock signal, really
Determine data signal phase, keeps receiving end sampled clock signal synchronous with data waiting, achieve the purpose that timing closure, greatly improve
The accuracy of data transmission, provides safeguard for high speed data transfer.So the present invention effectively overcome it is in the prior art various
Disadvantage and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (13)
1. a kind of synchronous sampling system, which is characterized in that the synchronous sampling system includes at least:
Sending module, exports data-signal to be received and clock signal to be received, the clock signal to be received and described waiting
It is synchronous to receive data-signal；
Clock data Phase synchronization module is connected to the output end of the sending module, detects the clock signal to be received
Phase, and the phase of the phase adjustment receiving end sampled clock signal based on the clock signal to be received, so that the reception
Hold sampled clock signal synchronous with the data-signal to be received；
Receiving module receives the data-signal to be received and the receiving end sampled clock signal, to realize receiving module end
The synchronized sampling of data-signal；
Wherein, the clock data Phase synchronization module includes that multiphase clock generates unit, phase matching components, phase demodulation unit
And phase selection unit；
Original clock signal obtains delay clock signal through the 4th path delay, wherein the 4th path delay is transmission road
The delay introduced on diameter；
The multiphase clock generates unit and receives the delay clock signal, is passed through in phase based on the delay clock signal
Insert the phase demodulation clock signal for generating multiple and different phases and sampled clock signal to be selected；
The phase matching components receive the clock signal to be received, carry out phase adjustment to the clock signal to be received,
So that the phase matched clock signal of the phase matching components output and the phase matched of the sampled clock signal to be selected；
The phase demodulation unit is connected to the phase matching components and the multiphase clock generates the output end of unit, based on more
The phase demodulation clock signal of a out of phase carries out phase-detection, and output phase selection signal to the clock signal to be received；
The phase selection unit is connected to the output end that the multiphase clock generates unit and the phase demodulation unit, according to institute
Phase selection signal is stated, selection and the matched signal of clock signal phase to be received from the sampled clock signal to be selected
As the receiving end sampled clock signal.
2. synchronous sampling system according to claim 1, it is characterised in that: the sending module includes frequency unit,
One sampling unit and timelag matching unit；
Original clock signal inputs the frequency unit after first path is delayed, and transmitting terminal sampling clock is obtained after two divided-frequency
Signal；
The data input pin of first sampling unit receives transmitting terminal described in data-signal to be sent, clock input and adopts
Sample clock signal, and based on data-signal to be sent described in the transmitting terminal sampled clock signal synchronized sampling；
The output signal of first sampling unit obtains the data-signal to be received through the second path delay；
The timelag matching unit receives the transmitting terminal sampled clock signal, prolongs to the transmitting terminal sampled clock signal
When；
The output signal of the timelag matching unit obtains the clock signal to be received through third path delay；
Wherein, the first path delay, second path delay and the third path delay are to introduce in transmission path
Delay.
3. synchronous sampling system according to claim 2, it is characterised in that: first sampling unit is d type flip flop.
4. synchronous sampling system according to claim 1, it is characterised in that: it includes point that the multiphase clock, which generates unit,
Frequency circuit and phase interpolation circuit；The frequency dividing circuit receives the delay clock signal, carries out to the delay clock signal
Two divided-frequency obtains sampled clock signal to be selected；The phase interpolation circuit is connected to the output end of the frequency dividing circuit, to described
The output signal of frequency dividing circuit carries out phase interpolation and obtains the phase demodulation clock signal.
5. synchronous sampling system according to claim 1, it is characterised in that: the phase demodulation unit includes sample circuit and phase
Position detection circuit；Wherein, the sample circuit adopts the phase matched clock signal based on the phase demodulation clock signal
Sample；The phase detecting circuit is connected to the output end of the sample circuit, to previous in adjacent two even level sampled signals
The positive phase signals of position and the inversion signal of latter position carry out logic and operation, to obtain the phase selection signal.
6. synchronous sampling system according to claim 1 or 5, it is characterised in that: the phase selection unit includes multiple
Gating circuit, the input signal of each gating circuit are respectively each sampled clock signal to be selected, and the control signal of each gating circuit connects
The phase selection signal corresponding with input signal is connect, the output end of each gating circuit is as the defeated of the phase selection unit
Outlet.
7. synchronous sampling system according to claim 6, it is characterised in that: the gating circuit includes:
Input terminal connects the first gated inverter and the second gated inverter of the sampled clock signal to be selected, and described first
The control terminal of control phase inverter connects the positive output signal of the corresponding phase demodulation unit, the control of second gated inverter
End connects the reversed-phase output signal of the corresponding phase demodulation unit；
Source electrode connects the first PMOS tube and the second PMOS tube of power supply, grid connection the first gate reverse phase of first PMOS tube
The control signal of device, drain electrode connect the output end of first gated inverter；Described in the grid connection of second PMOS tube
Output end of the output end, drain electrode of first gated inverter as the gating circuit；
The grid of the first NMOS tube and the second NMOS tube of source electrode ground connection, first NMOS tube connects the second gated inverter
Control signal, drain electrode connects the output end of second gated inverter；The grid connection described second of second NMOS tube
Output end of the output end, drain electrode of gated inverter as the gating circuit.
8. synchronous sampling system according to claim 1, it is characterised in that: the receiving module includes that the second sampling is single
Member, the data input pin of second sampling unit receives to be received described in the data-signal to be received, clock input
Sampled clock signal is held, and based on data-signal to be received described in the receiving end sampled clock signal synchronized sampling.
9. synchronous sampling system according to claim 8, it is characterised in that: second sampling unit is d type flip flop.
10. a kind of automatic phase selection method of the synchronous sampling system as described in claim 1 ~ 9 any one, feature exist
In the automatic phase selection method includes at least:
Obtain synchronous clock signal to be received and data-signal to be received；
The phase of the clock signal to be received is detected, with the phase of the determination data-signal to be received；
Based on the phase adjustment receiving end sampled clock signal of the clock signal to be received detected, so that the receiving end
Sampled clock signal is synchronous with the data-signal to be received.
11. automatic phase selection method according to claim 10, it is characterised in that: transmitting terminal sampled clock signal with to
It sends data-signal and obtains the synchronous clock signal to be received and the data-signal to be received after delay matching.
12. automatic phase selection method according to claim 10, it is characterised in that: determine the data-signal to be received
The step of phase includes:
When based on generating the phase demodulation clock signal and sampling to be selected of multiple and different phases by the original clock signal of path delay
Clock signal；
Phase demodulation clock signal pair and the phase demodulation clock signal phase that multiple and different phases are respectively adopted are matched described waiting
Receive clock signal to be sampled, determine the phase of the clock signal to be received according to sampled result, so obtain with it is described to
Receive the phase of the data-signal to be received of clock signal synchronization.
13. automatic phase selection method according to claim 12, it is characterised in that: adjust the receiving end sampling clock
The step of signal includes:
According to the phase of the clock signal to be received, from the sampled clock signal to be selected of multiple and different phases selection with it is described
The matched signal of clock signal phase to be received is as the receiving end sampled clock signal.
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