CN110460505B - Parallel bus time sequence calibration method and device and receiving end equipment - Google Patents
Parallel bus time sequence calibration method and device and receiving end equipment Download PDFInfo
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- 238000012360 testing method Methods 0.000 claims abstract description 62
- 238000005070 sampling Methods 0.000 claims description 13
- 238000004590 computer program Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
Abstract
The invention discloses a time sequence calibration method, a time sequence calibration device and receiving end equipment of a parallel bus, wherein the method comprises the following steps: s101: the receiving end equipment acquires test data sent by the sending end equipment through the parallel bus according to a target clock signal corresponding to the current clock offset; wherein the clock signal corresponds to the parallel bus; s102: judging whether the test data is correct or not according to preset calibration data; if not, the step S103 is entered; s103: adjusting the current clock offset according to a preset offset adjustment rule, and entering S101; whether the time sequence relation of the data signal and the clock signal has deviation or not is determined by utilizing preset calibration data and test data received from the parallel bus, so that the time sequence relation of the clock signal and the data signal is automatically calibrated by adjusting the current clock deviation according to a preset offset adjustment rule when the deviation occurs, and the problem of data transmission errors caused by time delay difference in the transmission process is solved.
Description
Technical Field
The present invention relates to the field of parallel bus technologies, and in particular, to a method and an apparatus for calibrating a timing sequence of a parallel bus, and a receiving end device.
Background
The parallel bus technology has very wide application in the field of electronic products such as computers and embedded devices, and is one of the most common bus technologies for transmitting data between devices or modules. The parallel bus has the main characteristic that multi-bit data, namely a multi-bit data bus, can be transmitted at the same time.
In the prior art, a sending end (sending end device) and a receiving end (receiving end device) of most parallel buses adopt a common clock design to ensure the correctness of data sending and receiving. In order to ensure that the transmitting end and the receiving end have a common clock, the same crystal oscillator (or clock module) can be used for providing the clock in the design; the clock used in transmission and the data bus can also be transmitted to the receiving end by the transmitting end, and the receiving end uses the clock to sample the data bus, which is called a channel associated clock. With the increase of the transmission frequency, due to the limitation of physical devices or processes, a small difference between the transmission time delay of the data bus and the clock line on the board PCB or the cable may cause that the receiving end cannot correctly sample the data bus, resulting in a communication error, which is also a difficulty in limiting the transmission frequency of the parallel bus.
As shown in fig. 1, the transmitting end obtains a clock input through an external crystal oscillator, and generates a required clock for bus transmission through a clock generator internally, so as to be used as a channel associated clock. And transmitting the data to be transmitted to a data bus under the channel associated clock, and simultaneously directly transmitting the channel associated clock to a clock line. Ideally, the timing relationship between the data signal and the clock signal at the transmitting end is as shown in fig. 2. Due to the transmission medium characteristics and the manufacturing process limitation between the sending end and the receiving end, no matter the PCB or the transmission cable, the absolute equal length of the data bus and the clock line or the absolute consistency of the transmission time delay cannot be realized. This situation may cause a deviation in the timing relationship between the data signal and the clock signal when the signal reaches the receiving end, and the data bus is directly sampled by using the associated clock, so that correct data cannot be obtained, as shown in fig. 3, the rising edge of the clock signal cannot align with a stable position of the center of the data signal, which results in a sampling error.
Therefore, how to solve the problem of data transmission errors caused by the difference of time delay in the transmission process so that the receiving end device can receive correct data transmitted through the parallel bus is a problem which needs to be solved urgently nowadays.
Disclosure of Invention
The invention aims to provide a time sequence calibration method and device of a parallel bus and receiving end equipment, so that the receiving end equipment can automatically calibrate the time sequence relation between a clock and data, and the problem of data transmission errors caused by time delay difference in the transmission process is solved.
To solve the above technical problem, the present invention provides a method for calibrating a timing sequence of a parallel bus, comprising:
s101: the receiving end equipment acquires test data sent by the sending end equipment through the parallel bus according to a target clock signal corresponding to the current clock offset; wherein the target clock signal corresponds to the parallel bus;
s102: judging whether the test data is correct or not according to preset calibration data; if not, the step S103 is entered; if yes, entering S104;
s103: adjusting the current clock offset according to a preset offset adjustment rule, and entering S101;
s104: it is determined that the calibration is complete.
Optionally, the acquiring, by the receiving end device, the test data sent by the sending end device through the parallel bus according to the target clock signal of the current clock offset includes:
the receiving end equipment utilizes the current clock offset to carry out phase adjustment on an original clock signal transmitted by a clock line in the parallel bus to obtain the target clock signal;
and sampling the data signals transmitted by the data buses in the parallel buses by using the target clock signals to obtain the test data.
Optionally, the acquiring, by the receiving end device, the test data sent by the sending end device through the parallel bus according to the target clock signal of the current clock offset includes:
the receiving end equipment performs phase adjustment on an original clock signal transmitted by a clock generator by using current clock offset to acquire the target clock signal; wherein the clock generator is arranged in the receiving end device;
and sampling the data signals transmitted by the data buses in the parallel buses by using the target clock signals to obtain the test data.
Optionally, the adjusting the current clock offset according to the preset offset adjustment rule includes:
and adding the current clock offset and a preset offset to update the current clock offset.
Optionally, the method further includes:
the sending end equipment sends the preset calibration data to the receiving end equipment through the parallel bus according to a preset time interval; and sending the preset calibration data by a preset time.
The invention also provides a time sequence calibration device of the parallel bus, which comprises:
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring test data sent by a sending end device through a parallel bus according to a target clock signal corresponding to current clock offset; wherein the target clock signal corresponds to the parallel bus;
the judging unit is used for judging whether the test data is correct or not according to preset calibration data; if the test data is correct, determining that the calibration is finished;
and the adjusting unit is used for adjusting the current clock offset according to a preset offset adjusting rule and sending a starting signal to the acquiring unit if the test data is incorrect.
Optionally, the obtaining unit includes:
the first clock signal acquisition subunit is configured to perform phase adjustment on an original clock signal transmitted by a clock line in the parallel bus by using current clock skew, and acquire the target clock signal;
and the first data acquisition subunit is used for sampling a data signal transmitted by a data bus in the parallel bus by using the target clock signal to obtain the test data.
Optionally, the obtaining unit includes:
the second clock signal acquisition subunit is used for performing phase adjustment on an original clock signal transmitted by a clock generator by using current clock skew to acquire the target clock signal; wherein the clock generator is arranged in the receiving end device;
and the second data acquisition subunit is configured to sample, by using the target clock signal, a data signal transmitted by a data bus in the parallel bus to obtain the test data.
Optionally, the adjusting unit includes:
and the updating subunit is used for adding the current clock offset and the preset offset and updating the current clock offset.
In addition, the present invention also provides a receiving end device, including:
a memory for storing a computer program;
a processor for implementing the steps of the method for timing calibration of a parallel bus as described above when executing the computer program.
The invention provides a time sequence calibration method of a parallel bus, which utilizes preset calibration data and test data received from the parallel bus to determine whether the time sequence relation of a data signal and a clock signal has deviation, so that when the deviation occurs, the current clock deviation is adjusted according to a preset deviation adjustment rule, the time sequence relation of the clock signal and the data signal is automatically calibrated, and the problem of data transmission error caused by time delay difference in the transmission process is solved; and the invention adopts the design of self-adaptation and closed loop, and has wider application range and higher flexibility. In addition, the invention also provides a time sequence calibration device and receiving end equipment of the parallel bus, and the time sequence calibration device and the receiving end equipment also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a channel associated clock scheme for a parallel bus according to the prior art;
fig. 2 is a schematic diagram of a timing relationship between a clock signal and a data signal of a transmitting end device;
FIG. 3 is a schematic diagram illustrating a timing relationship between a clock signal and a data signal of a receiving device;
FIG. 4 is a flowchart illustrating a timing calibration method for a parallel bus according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a channel associated clock scheme for a parallel bus according to an embodiment of the present invention;
fig. 6 is a block diagram of a timing calibration apparatus for a parallel bus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 4, fig. 4 is a flowchart illustrating a timing calibration method for a parallel bus according to an embodiment of the present invention, where the method includes:
step 101: the receiving end equipment acquires test data sent by the sending end equipment through the parallel bus according to a target clock signal corresponding to the current clock offset; wherein the target clock signal corresponds to the parallel bus.
It can be understood that, in this step, the target clock signal corresponding to the current clock offset may be a clock signal used for sampling a data bus in the parallel bus, that is, a clock signal obtained by performing phase adjustment on an original clock signal corresponding to the parallel bus by using the current clock offset.
Correspondingly, the step can also include a step of acquiring a target clock signal by the receiving end device, and the specific mode of acquiring the target clock signal by the receiving end device can be set by a designer, for example, the receiving end device can perform phase adjustment on the received original clock signal corresponding to the parallel bus by using the current clock offset to obtain the target clock signal; for example, when the sending end device transmits the clock signal used in sending to the receiving end device together with the data bus, that is, when the parallel bus includes the clock line and the data bus, the receiving end device may perform phase adjustment on the original clock signal transmitted by the clock line in the parallel bus by using the current clock skew to obtain a target clock signal; as shown in fig. 5, the phase adjustment module in the receiving end device may perform phase adjustment on the original clock signal transmitted by the clock line in the parallel bus by using the current clock offset; when the sending end device does not transmit the clock signal used in sending to the receiving end device together with the data bus, if clock generators are arranged in the sending end device and the receiving end device to generate clock signals corresponding to the same crystal oscillator, the receiving end device performs phase adjustment on the original clock signal transmitted by the clock generator arranged by the receiving end device by using current clock offset to obtain a target clock signal. The receiving end device may also directly receive a target clock signal output by another device, that is, the current clock offset of the other device performs phase adjustment on the received original clock signal corresponding to the parallel bus, so as to obtain the target clock signal and output the target clock signal to the receiving end device. The present embodiment does not set any limit to this.
Specifically, the current clock offset in this step may be an offset when the phase of the original clock signal is adjusted at the current time. The specific content of the current clock offset can be set by a designer or a user, for example, the initial time can set the current clock offset to 0.
It should be noted that, the purpose of this step may be to obtain, by the receiving end device, the test data sent by the sending end device through the parallel bus by using the target clock signal, that is, the receiving end device samples, by using the target clock signal, the data signal transmitted by the multi-bit wide data bus in the parallel bus, so as to obtain the test data.
Correspondingly, the specific manner in which the receiving end device acquires the test data sent by the sending end device through the parallel bus by using the target clock signal in this step may be set by a designer, and if the specific manner is the same as or similar to the manner in which the data signal of the parallel bus in the prior art is sampled, this embodiment does not limit this.
Step 102: judging whether the test data is correct or not according to preset calibration data; if not, go to step 103; if yes, go to step 104.
It can be understood that, in this embodiment, the sending-end device sends the preset calibration data to the receiving-end device through the parallel bus, and the receiving-end device compares the received test data with the preset calibration data stored in advance in this step to determine whether the received test data is correct, so as to determine whether the time sequence relationship between the target clock signal and the data signal is correct.
Specifically, the specific manner for judging whether the test data is correct or not according to the preset calibration data in this step may be set by the designer, for example, whether the received test data is the preset calibration data or not may be directly judged, for example, the sending end device sends the preset calibration data to the receiving end device at a preset time interval, and the receiving end device may directly judge whether the received test data is the preset calibration data each time before the calibration is completed; or it may be determined that the received test data is the same as part of the content in the preset calibration data, for example, the receiving end device determines whether the received test data is the same as part of the content in the preset calibration data within the time that the sending end device sends the preset calibration data; as shown in fig. 5, the data receiving module in the sending-end device samples the data bus by using the clock signal output by the phase adjusting module after the phase adjustment, and sends the test data obtained after the sampling to the sequence checking module, and the sequence checking module verifies whether the test data is correct after receiving a certain amount of test data. The present embodiment does not set any limit to this.
Step 103: and adjusting the current clock offset according to a preset offset adjustment rule, and entering step 101.
It can be understood that the purpose of this step may be that when the test data is incorrect, the receiving end device adjusts the current clock skew according to a preset offset adjustment rule, so as to adjust a target clock signal corresponding to the current clock skew, and implement adjustment and calibration of a timing relationship between the target clock signal and the data signal. In this embodiment, the receiving end device may adjust the target clock signal corresponding to the obtained current clock offset through this step, so that the timing relationship between the target clock signal for sampling the data signal and the data signal of the data bus is adjusted from the deviation state (as shown in fig. 3) to the required ideal state (as shown in fig. 2).
Specifically, the specific manner of adjusting the current clock offset according to the preset offset adjustment rule in this step can be set by a designer according to a practical scene and user requirements, and if the current clock offset can be added to the preset offset, the current clock offset is updated; for example, the offset amount (current clock offset) is set to 0 in the initial state, and the offset amount is increased by a fixed value (preset offset amount) every adjustment. The next offset can be selected from a preset offset set as the current clock offset, that is, the receiving end device can select one offset from a pre-stored offset set as the current clock offset during each adjustment, so as to realize the adjustment and update of the current clock offset; the method can also be used for analyzing the data of the test data and the preset calibration data to generate the offset of the original current clock offset to be adjusted, and then adding the offset and the original current clock offset to adjust the original current clock offset to obtain the new current clock offset. The present embodiment does not set any limit to this.
Step 104: it is determined that the calibration is complete.
It can be understood that the purpose of this step may be that when the test data is correct, the receiving end device determines that calibration is completed, that is, adjustment of the current clock offset is completed, so as to determine that the timing relationship between the target clock signal and the data signal corresponding to the current clock offset is correct.
Correspondingly, in this step, after the receiving end device determines that the calibration is completed, the calibration completion information may be displayed through a display device (such as an indicator light or a display) to inform a user that the calibration is completed; if the sending end device sends the preset calibration data to the receiving end device through the parallel bus according to the preset time interval, the user can control the sending end device to stop sending the preset calibration data after looking up the calibration completion information. And the calibration completion information can be sent to the sending end equipment through other communication connections with the sending end equipment so as to control the sending end equipment to stop sending the preset calibration data. And the normal receiving process can be directly entered, and the judgment of the received test data and the adjustment of the current clock offset are stopped.
Specifically, as shown in fig. 5, at the time of starting the parallel bus operation, both the sending end device and the receiving end device may first enter the bus link establishment mode; in a link establishment mode, a sending end starts a test sequence generator module and sends an appointed test sequence to a data bus; the receiving end equipment uses the phase-adjusted target clock signal to sample a data bus, and sends the sampled test data to the sequence check module, and the sequence check module verifies whether the test data is correct or not after receiving a certain amount of test data; if the sequence checking module judges that the test data is wrong, the feedback error is marked to the controller module, the controller module increases the offset of the phase adjusting module, and the re-sampling test data is returned; if the sequence checking module judges that the reading data is correct, the correct mark is fed back to the controller module, the controller module finishes the link establishment module state, a normal receiving process is entered, and the sequence checking module does not work any more.
In the embodiment, the preset calibration data and the test data received from the parallel bus are used for determining whether the time sequence relation between the data signal and the clock signal has deviation, so that the current clock deviation is adjusted according to the preset deviation adjustment rule when the deviation occurs, the time sequence relation between the clock signal and the data signal is automatically calibrated, and the problem of data transmission errors caused by time delay difference in the transmission process is solved; and the invention adopts the design of self-adaptation and closed loop, and has wider application range and higher flexibility.
Referring to fig. 6, fig. 6 is a block diagram illustrating a timing calibration apparatus for a parallel bus according to an embodiment of the present invention. The apparatus may include:
an obtaining unit 10, configured to obtain, according to a target clock signal corresponding to current clock skew, test data sent by a sending end device through a parallel bus; wherein the target clock signal corresponds to the parallel bus;
a judging unit 20, configured to judge whether the test data is correct according to preset calibration data; if the test data is correct, determining that the calibration is finished;
and the adjusting unit 30 is configured to, if the test data is incorrect, adjust the current clock offset according to a preset offset adjustment rule, and send a start signal to the obtaining unit 10.
Optionally, the obtaining unit 10 may include:
the first clock signal acquisition subunit is used for carrying out phase adjustment on an original clock signal transmitted by a clock line in the parallel bus by using the current clock offset to acquire a target clock signal;
and the first data acquisition subunit is used for sampling the data signals transmitted by the data buses in the parallel buses by using the target clock signals to obtain the test data.
Optionally, the obtaining unit 10 may include:
the second clock signal acquisition subunit is used for carrying out phase adjustment on an original clock signal transmitted by the clock generator by using the current clock skew to acquire a target clock signal; the clock generator is arranged in the receiving end equipment;
and the second data acquisition subunit is used for sampling the data signals transmitted by the data buses in the parallel buses by using the target clock signals to obtain the test data.
Optionally, the adjusting unit 30 may include:
and the updating subunit is used for adding the current clock offset and the preset offset and updating the current clock offset.
In the embodiment, the preset calibration data and the test data received from the parallel bus are used for determining whether the time sequence relation between the data signal and the clock signal has deviation, so that the current clock deviation is adjusted according to the preset deviation adjustment rule when the deviation occurs, the time sequence relation between the clock signal and the data signal is automatically calibrated, and the problem of data transmission errors caused by time delay difference in the transmission process is solved; and the invention adopts the design of self-adaptation and closed loop, and has wider application range and higher flexibility.
In addition, an embodiment of the present invention further provides a receiving end device, including: a memory for storing a computer program; a processor for implementing the steps of the parallel bus timing calibration method provided in the above embodiments when executing the computer program.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the apparatus and the receiving end device disclosed in the embodiments, since they correspond to the method disclosed in the embodiments, the description is relatively simple, and the relevant points can be referred to the description of the method.
Those of skill would further appreciate that the elements and algorithm steps of the various embodiments described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various example components and steps have been described above generally in terms of their functionality in order to clearly illustrate their interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The present invention provides a method and an apparatus for calibrating a timing sequence of a parallel bus, and a receiving end device. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A method for timing calibration of a parallel bus, comprising:
s101: the receiving end equipment acquires test data sent by the sending end equipment through the parallel bus according to a target clock signal corresponding to the current clock offset; the target clock signal corresponds to the parallel bus, and the target clock signal is a clock signal obtained by performing phase adjustment on an original clock signal corresponding to the parallel bus through the current clock offset;
s102: judging whether the test data is correct or not according to preset calibration data; if not, the step S103 is entered; if yes, entering S104;
s103: adjusting the current clock offset according to a preset offset adjustment rule, and entering S101;
s104: it is determined that the calibration is complete.
2. The method according to claim 1, wherein the step of acquiring, by the receiving device, the test data sent by the sending device through the parallel bus according to the target clock signal of the current clock offset includes:
the receiving end equipment utilizes the current clock offset to carry out phase adjustment on an original clock signal transmitted by a clock line in the parallel bus to obtain the target clock signal;
and sampling the data signals transmitted by the data buses in the parallel buses by using the target clock signals to obtain the test data.
3. The method according to claim 1, wherein the step of acquiring, by the receiving device, the test data sent by the sending device through the parallel bus according to the target clock signal of the current clock offset includes:
the receiving end equipment performs phase adjustment on an original clock signal transmitted by a clock generator by using current clock offset to acquire the target clock signal; wherein the clock generator is arranged in the receiving end device;
and sampling the data signals transmitted by the data buses in the parallel buses by using the target clock signals to obtain the test data.
4. The method for calibrating the timing of a parallel bus according to claim 1, wherein said adjusting the current clock offset according to the preset offset adjustment rule comprises:
and adding the current clock offset and a preset offset to update the current clock offset.
5. The method for timing calibration of a parallel bus according to any of claims 1 to 4, further comprising:
the sending end equipment sends the preset calibration data to the receiving end equipment through the parallel bus according to a preset time interval; and sending the preset calibration data by a preset time.
6. An apparatus for calibrating a timing of a parallel bus, comprising:
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring test data sent by sending end equipment through a parallel bus according to a target clock signal corresponding to current clock offset; the target clock signal corresponds to the parallel bus, and the target clock signal is a clock signal obtained by performing phase adjustment on an original clock signal corresponding to the parallel bus through the current clock offset;
the judging unit is used for judging whether the test data is correct or not according to preset calibration data; if the test data is correct, determining that the calibration is finished;
and the adjusting unit is used for adjusting the current clock offset according to a preset offset adjusting rule and sending a starting signal to the acquiring unit if the test data is incorrect.
7. The apparatus for calibrating timing of a parallel bus according to claim 6, wherein said obtaining unit comprises:
the first clock signal acquisition subunit is configured to perform phase adjustment on an original clock signal transmitted by a clock line in the parallel bus by using current clock skew, and acquire the target clock signal;
and the first data acquisition subunit is used for sampling a data signal transmitted by a data bus in the parallel bus by using the target clock signal to obtain the test data.
8. The apparatus for calibrating timing of a parallel bus according to claim 6, wherein said obtaining unit comprises:
the second clock signal acquisition subunit is used for performing phase adjustment on an original clock signal transmitted by a clock generator by using current clock skew to acquire the target clock signal; wherein the clock generator is arranged in the receiving end device;
and the second data acquisition subunit is configured to sample, by using the target clock signal, a data signal transmitted by a data bus in the parallel bus to obtain the test data.
9. The apparatus of claim 6, wherein the adjusting unit comprises:
and the updating subunit is used for adding the current clock offset and the preset offset to update the current clock offset.
10. A receiving-end device, comprising:
a memory for storing a computer program;
processor for implementing the steps of the method for timing calibration of a parallel bus according to any of claims 1 to 4 when executing said computer program.
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| CN111949589B (en) * | 2020-07-22 | 2022-05-24 | 浪潮(北京)电子信息产业有限公司 | Clock control method, device, equipment and storage medium |
| CN113254084B (en) * | 2021-07-07 | 2021-09-24 | 航天中认软件测评科技（北京）有限责任公司 | Time and time sequence calibration method and device based on processor pipeline analysis |
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