CN114420043B

CN114420043B - Drive circuit, drive chip and display device

Info

Publication number: CN114420043B
Application number: CN202210101400.6A
Authority: CN
Inventors: 唐永生; 黄立; 芦世雄
Original assignee: Chengdu Lipson Microelectronics Co ltd
Current assignee: Chengdu Lipson Microelectronics Co ltd
Priority date: 2022-01-27
Filing date: 2022-01-27
Publication date: 2022-11-18
Anticipated expiration: 2042-01-27
Also published as: CN114420043A

Abstract

The application relates to a drive circuit comprising: a path matching module for eliminating unknown phase difference between the PWM broadening clock signal and the PWM generating clock signal; a PWM module that generates a PWM signal based on display data, the PWM generation clock signal, and the PWM stretching clock signal; and the channel current output module outputs constant current in the effective period of the PWM signal. The circuit can compensate the lighting time of the LED on one hand; on the other hand, through the way of path matching, the phase compensation with more accurate PWM can be finally realized.

Description

Drive circuit, drive chip and display device

Technical Field

The application relates to the field of LED display, in particular to a driving circuit, a driving chip and a display device.

Background

In the display of the LED display screen, a row driving chip and a column driving chip are usually used to light up the LED array. In one case, the anode of the LED array is connected to the output of the row driver chip via a row line and the cathode of the LED array is connected to the column driver chip via a column line. The column driving chip is usually realized by adopting a constant current source chip, and the constant current source chip controls the starting time of the constant current source according to the display data so as to determine the lighting time of the lamp beads on the corresponding column line. More specifically, the row driving chip controls the lighting of the corresponding LED of each row according to the display data, the column driving chip generates a corresponding PWM signal according to the display data, and controls the column driving chip to output a constant current to the corresponding column line within the effective time of the PWM signal, so as to light the LED lamp bead. Wherein, the lighting time of the LED corresponding to the column line can be changed by adjusting the width of the active time of the PWM signal.

In the prior art, in a constant current source driving chip of an LED display screen, a PWM generating module generates a PWM signal according to a control signal of a register and image data information received by an SRAM module, and controls to output a constant current within an effective time of the PWM signal. The ideal PWM signal is a square wave, however, in practical displays, the LED lighting time is lost due to the existence of non-ideal factors. The brightness of the LED is related to the time of lighting, and therefore, this inevitably results in a loss of brightness of the LED. In the prior art, on one hand, a relatively effective mode is lacked in brightness compensation, and on the other hand, relatively accurate compensation is difficult to achieve in the prior art.

How to solve the technical problems becomes a problem to be solved urgently.

Disclosure of Invention

The purpose of this application is to overcome prior art's not enough, provides a drive circuit, and this drive circuit can solve the luminance problem of disappearance that the display time loss that exists causes in the actual display, and can eliminate in luminance compensation because the unknown phase deviation between the clock phase that the different reasons such as the combinational logic circuit that each clock passes through caused, accomplishes comparatively accurate compensation.

The purpose of the application is realized by the following technical scheme:

in one aspect, the present application provides a display driving circuit comprising:

a path matching module for eliminating unknown phase difference between the PWM broadening clock signal and the PWM generating clock signal;

a PWM module that generates a PWM signal based on display data, the PWM generation clock signal, and the PWM stretching clock signal;

the channel current output module outputs constant current in the effective period of the PWM signal;

and the difference between the PWM broadening clock signal and the PWM generating clock signal is K complete clock cycles, wherein K is more than or equal to 0 and less than 1.

In the present application, the PWM stretched clock signal (CLKS) differs from the PWM generated clock signal by K complete clock cycles; the PWM module generates a final PWM signal according to the stretched clock signal, the generated clock signal, and the display data, wherein the final PWM signal stretches the PWM signal corresponding to the original display data, a fractional width (fractional clock cycles) for brightness compensation is added, and the stretched width is a phase difference between CLKS and CLKG, that is, K clock cycles, thereby compensating for a loss of display time. The path matching module can eliminate the unknown phase difference between CLKS and CLKG so that the phase difference between CLKS and CLKG that is ultimately input to the PWM module for generating the PWM signal is the desired fixed phase difference K.

Further, the path matching module includes:

the first logic circuit outputs the PWM to generate a clock signal after an initial clock signal passes through the first logic circuit;

a first device for outputting the PWM-stretched clock signal after the delayed clock signal passes through the first device;

the logic path of the initial clock signal through the first logic circuit is identical to the logic path of the delayed clock signal through the first device.

To achieve the stretching of the original PWM signal, an initial clock signal and a delayed clock signal with a certain phase difference (or delay) from the initial clock signal (e.g., P full clock cycles from the initial clock signal) are typically selected. An initial PWM signal is generated based on the display data and the initial clock signal, a PWM signal having the same width as the initial PWM signal but a certain delay, which is generally P complete clock cycles, is generated based on the initial PWM signal and the delayed clock signal, and then the two PWM signals are subjected to logic operation (for example, logical OR) to obtain a final PWM signal. It will be appreciated that the magnitude of the phase difference (delay) between the delayed clock signal, which is used to generate the initial PWM signal, and the initial clock signal, which is used to generate the PWM generated clock signal, and the delayed clock signal, which is used to stretch, determines the width of the stretch. However, in practice, the two clock signals are selected to pass through different logic circuits. For example, typically, the initial clock signal is directly input into the PWM generation module (e.g., D flip-flop); the delayed clock signal is selected from a plurality of delayed clock signals through a multiplexer and is output and then input into the PWM generating module. Due to the fact that a combinational logic circuit actually exists in the multiplexer, the difference between the initial clock signal and the delayed clock signal which are finally input to the PWM generation module is not P complete clock cycles, and unknown phase deviation or phase difference exists. It will be appreciated that this part of the unknown phase deviation is caused by different logic paths or combinational logic circuits through which the initial clock signal and the delayed clock signal pass, and it can also be considered that the different paths through which the signals pass cause different delays.

As described above, in order to realize the luminance compensation, means may be provided for selecting one of the delayed clock signals having a different phase difference (or delay time) from the initial clock signal and outputting the selected one as the clock signal (delayed clock signal) for finally generating the PWM signal, and for selecting a different delayed clock signal, the magnitude of the luminance compensation or the width of the final PWM spread may be determined. In the present application, the delayed clock signal is selected by the first means, and since the selection logic circuit device (or circuit device) on the circuit path formed by the first means when selecting the delayed clock signal causes a delay, not only a desired delay or phase difference but also an unknown phase deviation or delay will exist between the selected delayed clock signal and the original clock signal. In this regard, the present application further includes a first logic circuit for compensating for the unknown phase offset or delay by applying the same unknown amount to the initial clock signal to offset the unknown phase offset or delay. Specifically, the logic circuit through which the initial clock signal passes and the logic circuit through which the delayed clock signal (which may also be considered as the selected delayed clock signal) passes in the first device are identical, that is, the first logic circuit is configured such that the electronic components and processing logic on the first logic circuit and the processing logic of the first device on the delayed clock signal are completely matched or identical. The exact match or identity may include exact identity in the type, number, combination, etc. of the electronic components. With this arrangement, the delays caused by the two hardware circuits to the clock signals passing through the respective circuits (the delay caused by the first logic circuit to the initial clock signal and the delay caused by the first means to the selected delayed clock signal) are the same, and the two hardware circuits cancel each other out, so that the delay or skew between the initial clock signal processed by the first logic circuit (PWM generated clock signal) and the selected delayed clock signal processed by the first means (PWM stretched clock signal) is accurate and controllable, i.e. the desired phase skew required for stretching, e.g. P complete clock cycles, i.e. the unknown phase difference between the initial clock signal (PWM generated clock signal) and the selected delayed clock signal (PWM stretched clock signal) is cancelled, and the phase difference between the two clock signals input to the PWM module for generating the PWM signals is the desired phase difference.

Further, the driving circuit further includes a multi-phase clock generating module for generating N clock signals with the same phase difference, where the N clock signals with the same phase difference are used as the initial clock signal and the delayed clock signal. The N clock signals with the same phase difference in the present application refer to N clock signals generated by the multi-phase clock generation module, which have a phase difference of 1/N clock cycles in sequence, that is, the phase differences between the clock signals are arranged according to an arithmetic progression. For example, the second clock signal differs from the first clock signal by 1/N clock cycles, and the third clock signal differs from the second clock signal by 1/N clock cycles; the third clock signal differs from the first clock signal by 2/N clock cycles. It is understood that, on the other hand, the second clock signal is different from the first clock signal by 1/N clock cycles, or the second clock signal is delayed by 1/N clock cycles from the first clock signal (for convenience of understanding, the first rising edge of the subsequent clock signal is delayed by 1/N,2/N, 8978 xft 8978, (N-1)/N) from the rising edge of the first clock signal in sequence after the time point, for example, from the time point of a certain rising edge of the first clock signal on the time axis).

Further, the first means is a multiplexer for selecting one of the N delayed clock signals to output as the PWM stretched clock signal. By selecting different delay clock signals, the initial PWM signal can be stretched differently, thereby compensating the display differently.

Further, the PWM module includes:

the first PWM generating module generates a first PWM signal based on the display data and the PWM generating clock signal;

a second PWM generation module that generates a second PWM signal based on the PWM stretched clock signal and the first PWM signal;

a logic module to generate a PWM signal based on the first PWM signal and the second PWM signal.

In the present application, an initial PWM signal is first generated according to display data and a PWM generation clock (where the display data determines the width of the PWM signal (the width of the active period), the clock signal determines the start and end of the PWM signal, such as the start and end of the active time, i.e., the rising and falling edges of the PWM), and if the control is performed according to the PWM signal, the switching tube is turned on and off slowly without jumping like a PWM waveform diagram, so there is a loss of LED lighting time. The initial PWM signal may be stretched using a stretched clock signal that is out of phase (delayed) with the clock signal that generated the initial PWM signal. Specifically, a stretched clock signal is used, an intermediate PWM signal is obtained from the stretched clock and the initial PWM signal, and a logical operation is performed based on the intermediate PWM signal and the initial PWM signal, thereby obtaining a final PWM signal. For example, a stretched clock signal with a certain delay is used to perform corresponding delay on the initial PWM to obtain a PWM signal with a certain delay and the same width as the initial PWM signal, and then the initial PWM signal and the delayed PWM signal are subjected to logic operation to obtain a final stretched PWM signal. That is, by widening the width corresponding to the original display data to a certain extent, it is possible to compensate for the luminance loss caused by using only the original PWM.

Further, the first PWM generating module and the second PWM generating module are D triggers. The flip-flop receives the display data and the clock signal to generate the display data (PWM signal) having a width corresponding to the display data and aligned with an edge (e.g., a rising edge) of the clock signal, so that any flip-flop suitable for the application can be used in the present application.

Further, the logic module performs a logical or operation. By logical or operation, a broadened PWM signal can be obtained.

Furthermore, the number of the PWM modules and the number of the channel current output modules are M; the PWM modules are connected with the channel current output modules in a one-to-one corresponding mode; the path matching module is connected with each PWM module and outputs the PWM broadening clock signal and the PWM generation clock signal to each PWM module; wherein M is an integer greater than or equal to 4. M is the number of channels (constant current output channels) of the driving circuit or the driving chip, two clock signals output by the path matching module are simultaneously input into each PWM module, and each channel can be compensated, so that the deficiency of display time caused by non-ideal factors is made up, and the brightness of the LED is compensated.

In another aspect, the present application also provides a driving chip including the driving circuit.

In another aspect, the present application further provides a display apparatus, which includes a display device and the driving chip, wherein the driving chip generates a driving signal to drive the display device to display.

The beneficial effect of this application is:

compared with the prior art, the driving circuit provided by the application adopts the PWM widening technology to compensate each channel, so that the problem of display time loss caused by non-ideal factors is solved, and brightness compensation can be performed;

the PWM broadening method provided by the application adopts the PWM to generate the clock and the broadening clock, the difference between the two clocks is a small number of complete clock cycles, and the difference can be adjusted in real time according to the display effect, so that the brightness compensation is flexible;

a special path matching module is adopted to eliminate unknown phase difference between a PWM (pulse-width modulation) generated clock and a spread clock, and the types and the characteristics of components on hardware paths respectively passed by the two clocks in the path matching module are completely consistent, so that the phase deviation or the time delay between the two clocks is accurate, and the precision of brightness compensation is improved.

Drawings

FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a path matching module according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a path matching module according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a multi-phase clock signal provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a decoder according to an embodiment of the present application;

FIG. 6 is a circuit diagram of a first logic circuit according to an embodiment of the present application;

FIG. 7 is a circuit diagram of a first apparatus according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a PWM module according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a PWM stretching process according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a driver circuit according to another embodiment of the present application;

1-a path matching module; 2-a PWM module; and 3-channel current output module.

Detailed Description

The technical solutions of the present application are further described in detail below with reference to specific examples, but the scope of protection of the present application is not limited to the following descriptions.

In one aspect, the present application provides a driving circuit, referring to a schematic diagram of the driving circuit shown in fig. 1, which includes:

the path matching module 1 is used for eliminating unknown phase difference between the PWM broadening clock signal and the PWM generating clock signal;

a PWM module 2 generating a PWM signal based on display data, the PWM generation clock signal, and the PWM stretched clock signal;

and the channel current output module 3 outputs constant current in the effective period of the PWM signal.

Optionally, a difference between the PWM stretched clock signal and the PWM generated clock signal is K complete clock cycles, where K is greater than or equal to 0 and less than 1.

K complete clock cycles can ensure that the compensation of a small number of clock cycles is carried out on the PWM signal corresponding to the display data, and the value of K is adjustable based on the size of compensation required. It is understood that the clock period of the PWM generated clock signal and the clock period of the PWM stretched clock signal are the same, i.e., the respective clock signals have the same frequency. The PWM stretched clock signal may be considered to have a phase difference relative to the PWM generated clock signal that differs by K full clock cycles. Optionally, the difference is K full clock cycles, referring to a delay of the PWM stretched clock signal with K full clock cycles relative to the PWM generated clock signal.

For example, assuming a clock period T, the PWM stretched clock signal differs from the PWM generated clock signal by K × T. It is assumed that the PWM stretched clock signal has a delay of K x T with respect to said PWM generated clock signal, i.e. the PWM stretched clock signal has a lag or delay of a few clock periods T with respect to the PWM generated clock. This delay can be used to stretch the original PWM signal by exactly the width K x T. The PWM module 2 is configured to generate a broadened PWM signal, where the broadened PWM signal is input to the channel current output module 3, and the channel current output module 3 can control whether to output a constant current according to the PWM signal. Specifically, the channel current output module 3 outputs a constant current during the active period of the PWM signal (e.g., during the period in which the PWM signal is at a high level). It will be appreciated that when the channel outputs a constant current, the LED can be turned on (lit) via the column line, ideally for the duration of the PWM active period, e.g. the width occupied by the PWM at high level.

And the path matching module 1 is used for eliminating unknown phase difference between the PWM broadening clock signal and the PWM generating clock signal. It will be appreciated that the formation of the PWM signal is determined by a clock signal and a data signal, e.g., a D flip-flop as the PWM generation module, the data signal determining the width of the PWM, the clock signal determining the start and end of the PWM, e.g., the start and end of the active time, i.e., the rising and falling edges of the PWM. Since the paths (combinational logic circuits) of the clock signal for generating the initial PWM signal and the clock signal for generating the delayed PWM signal to the respective PWM generating modules (e.g., D flip-flops) are different (e.g., the multiphase generating module generates a plurality of clock signals CLK1 to CLKN having a fixed phase difference, CLK1 is directly input to the first PWM generating module to generate the first PWM signal, and CLK1 to CLKN are selected by the selector and then alternatively input to the second PWM module, which is assumed to be CLK5, since the selector is composed of different combinational logic circuits or electronic components, the paths through which CLK1 and CLK5 pass are different, and in order to achieve precise compensation, a fixed phase deviation between CLK1 and CLK5 is required, but an unknown phase difference is introduced between CLK1 and CLK5 due to the different paths), which results in that the two clock signals are not the desired fixed phase difference, but an unknown phase difference exists. The path matching module 1 of the present application is for eliminating unknown phase differences of clock signals input to the respective PWM generating modules, that is, a plurality of clock signals are input to the path matching module 1, and two clock signals (PWM stretched clock signals and PWM generated clock signals) having desired phase differences are output to the PWM generating module after being selected by the path matching module 1. In other words, the path matching module 1 may eliminate the unknown phase difference between the PWM stretched clock signal and the PWM generated clock signal, so that there is a desired phase difference or delay between the PWM stretched clock signal and the PWM generated clock signal.

Referring to fig. 1, the PWM module 2 receives display data and a PWM generation clock signal and a PWM stretching clock signal, which are selected and output by the path matching module 1, and generates a PWM signal, i.e., a signal after stretching an initial PWM signal, based on the data. Optionally, the driving circuit includes an SRAM module, which receives image data information transmitted from outside and sends display data to the PWM module; the driving circuit may further include a register, which receives a control command transmitted from the outside and generates a control signal required for image display to the PWM module 2. Optionally, as shown in fig. 1, the input terminal of the channel current output module 3 further receives a reference current, and the reference current may be implemented as in fig. 10, that is, a Bandgap is used to provide a reference voltage, the reference voltage is input to the bias module and the current generation module, the bias module outputs a bias current to the current generation module, the current generation module is connected to an external resistor (R _ EXT) on the chip, and the external resistor (R _ EXT) may be used to adjust the magnitude of the reference current. The current generation module generates accurate reference current to the channel current output module 3 by using the reference voltage and the bias current. The Bandgap reference may be a voltage reference independent of temperature by using a sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient, and the temperature coefficients of the two are offset with each other. In the present application, it is preferable to use the circuit shown in fig. 10 to provide the reference current to the channel current output module 3, and of course, there are many ways to implement the reference current, and the present application is not limited specifically, and any circuit capable of generating the reference current may be used to provide the reference current for the channel current output module 3.

Optionally, the path matching module 1 includes:

Referring to fig. 2-3, the path matching module 1 receives clock signals (multi-phase clock signals) including a delayed clock signal and an initial clock signal. In one embodiment, one of the multi-phase clock signals is selected as an initial clock signal and input to a first logic circuit (generally, CLK [0 ]), the initial clock signal is output after passing through the first logic circuit (after output, PWM generating clock signals), one, a plurality of or all of the multi-phase clock signals can be used as delayed clock signals (generally, all), and the first device selects one of the delayed clock signals and outputs the selected delayed clock signal (after output, PWM spreading clock signals). The difference between the delayed clock signal (any one) and the initial clock signal is H complete clock cycles, and H is more than or equal to 0 and less than 1. For ease of understanding, the delayed clock signal (either) may also be considered to have a delay of H complete clock cycles relative to the initial clock signal. It will be appreciated that the PWM generated clock signal is actually the initial clock signal, and is not the initial clock signal that is output after passing through the first logic circuit of the path matching block 1, i.e. with a delay applied. Similarly, the PWM stretched clock signal is actually one of delayed clock signals, which is output after being selected by the first device of the path matching module 1, and also applied with a certain delay. Since the logic path of the initial clock signal through the first logic circuit is identical to the logic path of the delayed clock signal through the first device, the phase difference between the PWM generated clock and the PWM stretched clock is equal to the phase difference between the initial clock signal and the selected delayed clock signal. It will be appreciated that the value ranges for K and H are the same.

In addition, the first device refers to a specific module, apparatus, or device, which has a fixed internal logic circuit, and the internal logic circuit refers to a circuit generic term of the process of processing the corresponding signal. Because the fixed internal logic circuit is provided, the circuit cannot be adjusted or changed, so that the application designs the first logic circuit which can be matched with the circuit inside the first device. Thus, the first logic circuit is tunable, in other words, the first logic circuit can adapt itself to the circuitry inside the first device, as needed, so that the first logic circuit is completely identical to the circuitry (circuit path) through which the delayed clock signal (selected delayed clock signal) passes within the first device. It is to be understood that the circuit (circuit path) through which the first logic circuit passes is the above-described logic path. That is, the first logic circuit may be arranged to "copy" circuitry (logic paths) through which the delayed clock signal (selected delayed clock signal) passes within the first device. Therefore, the first logic circuit is arranged to match with the corresponding logic path in the first device, so that unknown phase deviation or time delay between the PWM generating clock signal and the PWM broadening clock signal is eliminated, the PWM generating clock signal and the PWM broadening clock signal with accurate fixed phase difference are obtained, and controllable and accurate broadening and brightness compensation are achieved. In other words, by providing the path matching block 1 including the first logic circuit and the first means, an unknown phase difference between the initial clock signal directly input to the PWM generating block and the delayed clock signal selected by the selector can be eliminated.

Optionally, the driving circuit further includes a multi-phase clock generation module for generating N clock signals CLK [0] to CLK [ N-1] with the same phase difference, where N is an integer greater than 1, and preferably N is greater than or equal to 4, as the initial clock signal and the delayed clock signal. The N clock signals with the same phase difference in the application refer to N clock signals generated by the multi-phase clock generation module, which are sequentially different by 1/N clock cycles (CLK [0] -CLK [ N-1] are sequentially different by 1/N clock cycles), that is, the phase differences among the clock signals are arranged according to an arithmetic progression. For example, the second clock signal differs from the first clock signal by 1/N clock cycles, and the third clock signal differs from the second clock signal by 1/N clock cycles; the third clock signal differs from the first clock signal by 2/N clock cycles. The latter clock signal may also be considered to be delayed by 1/N clock cycles from the previous clock signal. Taking 8-phase clock signals as an example, as shown in FIG. 4, 8 clock signals CLK [0] CLK [7] with the same phase difference generated by the multi-phase clock generation module have the same frequency, wherein the difference between CLK [1] and CLK [0] is 1/8 clock cycles, and the difference between CLK [2] and CLK [1] is 1/8 clock cycles, … ….

Any one of the N clock signals may be selected as the initial clock signal, typically CLK [0] is selected, and the N clock signals are used as the delayed clock signals. The N clock signals have the same frequency (i.e., the clock cycles are the same), and the phase difference between two adjacent signals is the same, and the phase difference is 1/N clock cycles (it can also be understood that the latter clock signal is delayed by 1/N clock cycles relative to the former clock signal). In this case, H = i/N, where i is an integer of 0 to (N-1), and theoretically, K = H. Assuming that CLK [0] is selected as the initial clock signal, determining which of the N delayed clock signals is selected to be output as the final PWM stretched clock signal by the first device determines i, which is the clock period, and determines the width of stretching the PWM signal corresponding to the display data (K × T, ideally, K = H = i/N).

Specifically, as shown in FIG. 3, multi-phase clock signals, such as N clock signals CLK [0] CLK [ N-1], are generated by the multi-phase clock generation module and have the same phase difference. The difference between two adjacent clock signals is 1/N clock cycles, the difference between CLK1 and CLK 0 is 1/N clock cycles, and the difference between CLK2 and CLK1 is 1/N clock cycles, … …. CLK [0] is selected as the initial clock signal, and there is no phase difference for the delayed clock signal CLK [0], while for the delayed clock signals CLK [1] -CLK [ N-1], there is a phase difference of 1/N,2/N, … …, (N-1)/N clock cycles (or so much delay) relative to the initial clock signal CLK [0], respectively. In this case, as shown in FIG. 3, when CLK [0] is selected as the initial clock signal and CLK [0] -CLK [ N-1] are selected as the delayed clock signals, H is 0, 1/N,2/N, … …, (N-1)/N, respectively. It will be appreciated that when CLK [0] is selected to generate the final stretched clock signal, it will not actually stretch, which is rare, but does not preclude its use in certain applications.

Of course, any one of the N clock signals may be selected as the initial clock signal, for example, CLK [1], and in this case, CLK [0], CLK [2] -CLK [ N-1] are different from CLK [1] by (N-1)/N (or-1/N), 1/N,2/N, … …, and (N-2)/N clock cycles, respectively. In other words, the initial clock signal may not only be CLK [0] selected, but also CLK [0] -CLK [ N-1] which is different from CLK [0] by 0, 1/N,2/N, … …, (N-1)/N clock cycles in this order may be used as the delayed clock signal, as shown in FIG. 3. Any one of the N clock signals may be selected as an initial clock signal, and all of the N clock signals may be selected as delayed clock signals. Regardless of how selected, the phase or delay time (H = i/N, where i is an integer between 0 and (N-1), i.e., 0, 1/N,2/N, … …, (N-1)/N clock cycles) by which the delayed clock signal is eventually different from the initial clock signal determines the final width of the spread, which can be selected between 0, 1/N,2/N, … …, (N-1)/N clock cycles by the first means. It will be appreciated that the greater N, the greater the accuracy with which compensation can be made.

Alternatively, the multi-phase clock generation module may be selected as one of a phase interpolator, a phase locked loop DLL, a phase locked loop PLL.

Optionally, the first means is a multiplexer for selecting one of N delayed clock signals (e.g., CLK [0] -CLK [ N-1 ]) to output as the PWM stretched clock signal. The first device selects a certain delayed clock signal according to the selection signal and outputs it as a PWM stretched clock signal.

In some alternative embodiments, as shown in fig. 3, the logic matching module 1 further includes a selection module. The selection module may be a decoder, which obtains a selection signal by decoding according to an input control word, and inputs the selection signal to the first device to select the delayed clock signal. Fig. 5 shows an embodiment of a decoder, which is a 3-8 decoder, which outputs 8 cs signals (select signals) in accordance with input three-bit signals sel1-sel3 (control words). Of course, the 3-8 decoder is only one embodiment of the present application, and the present application may select different decoders as needed.

Fig. 6-7 show an embodiment of a first logic circuit and a specific circuit of a first apparatus according to the present application. Taking the 8-phase clock signal as an example, referring to fig. 6, the first logic circuit sequentially includes a nand gate, a nor gate, a nand gate, and a buffer circuit. The buffer circuit may alternatively be an inverter. The embodiment shown in FIG. 6 selects CLK [0] as the initial clock signal and the output of the first logic circuit generates the clock signal (CLKG) for PWM. Of course, in the present application, instead of selecting CLK [0] as the initial clock signal, any one of the multi-phase clock signals, for example, the 3 rd of the 8 phase clock signals, may be selected. Fig. 7 shows an internal circuit diagram of the first device in an embodiment. Also taking an 8-phase clock signal as an example, the 8-phase clock signal is input to the first device, and the first device selects one of the 8-phase clock signals to output as the PWM stretched clock signal (CLKS) based on the selection signals (cs 1-cs 8). For example, when CLK [1] is selected, CLK [1] is now passed through the NAND gate with inputs CLK [1] and cs2, followed by the NAND gate, NOR gate, NAND gate and buffer output CLKS. It can be seen that by selecting the signal, any one of the 8 clocks can be selected as CLKS, thereby determining the broadening width, i.e., how much brightness compensation is to be performed. It will be appreciated that whichever of CLK [0] -CLK [ N-1], the path (logic path) through which it flows in the first device is a NAND gate, a NOR gate, a NAND gate, and a buffer circuit. It can be seen that no matter which clock signal is output as a stretched signal, the circuit path or logic path (which may include the type, number, connection order, etc.) that it traverses is the same as the logic path when the initial clock signal passes through the first logic circuit, and is a nand gate, a nor gate, a nand gate, and a buffer circuit. Of course, fig. 6-7 take an 8-phase clock signal as an example, and in practice, the clock signal may be N-phase, where N is an integer greater than 1. Of course, an integer of 4 or more is preferable. At this time, the internal circuits of the first logic circuit and the first device are changed, which is different from the circuits of fig. 6 to 7, but the logic path of the initial clock signal through the first logic circuit is identical to the logic path of the delayed clock signal through the first device. Therefore, the delays caused by the two logic paths to the two clock signals are the same, so that the finally generated PWM generation clock signal and the PWM broadening clock signal have accurate and fixed phase difference, and the purpose of eliminating unknown phase difference between the clock signal input to the PWM generation module generating the initial PWM and the clock signal input to the PWM generation module generating the second PWM is achieved.

In some embodiments, the buffer circuit is optional, not required. When not provided, for example, in fig. 6-7, there is no buffer circuit, but the output of the last nand gate is used as the final CLKS or CLKG.

Optionally, in some embodiments, as shown in fig. 8, the PWM module includes:

Specifically, after receiving externally transmitted image data, the memory, for example, the SRAM, receives and stores the display data, and transmits the display data to the PWM module 2, specifically, the first PWM generation module of the PWM module 2, which also receives the PWM generation clock signal at the same time, thereby generating the first PWM signal based on the display data and the PWM generation clock signal. It should be noted that the first PWM signal is actually a PWM signal corresponding to display data, and may also be considered as the aforementioned initial PWM signal, where a width of the first PWM signal corresponds to a time period during which the LED should be turned on, that is, a time period during which the switching tube or the MOS tube is closed and the channel current output module outputs the constant current. Due to the existence of non-ideal factors in the circuit, the time loss of the actual output constant current is caused, and the brightness loss is caused. Therefore, in the present application, a PWM stretching module as shown in fig. 8 is used to stretch the initial PWM signal, i.e. to extend a certain width, so as to compensate the above loss in time. Specifically, as shown in fig. 8, the PWM stretching module is connected to the first PWM generating module, and receives an initial PWM signal (a first PWM signal) output by the first PWM generating module, and also receives a PWM stretching clock signal output by the path matching module 1, where the PWM stretching clock signal differs from the PWM generating clock signal by K complete clock cycles, where K is greater than or equal to 0 and less than 1. The PWM stretching module may generate a final PWM signal, i.e., a stretched PWM signal, based on the received two signals, and the PWM signal stretches the initial PWM signal. Specifically, the PWM stretching module is actually composed of a second PWM generating module and a logic module. A second PWM generation module that receives a first PWM signal and a PWM stretching clock signal and generates a second PWM signal based on the PWM stretching clock signal and the first PWM signal; the logic module receives the second PWM signal and the first PWM signal and generates a final stretched PWM signal.

Optionally, the logic module performs a logical or operation, or a logical and operation.

The following explains the operation principle of the PWM module in this application in detail. Referring to fig. 8-9, the multiphase clock signals include CLK1, CLK2, CLK3 … … having the same phase difference, which are input to the logic matching block 1, and are selected by the logic matching block 1 to output two clock signals, i.e., a PWM generated clock signal (CLKG) and a PWM stretched Clock Signal (CLKs), as can be seen in fig. 9, there is a phase difference between CLKs and CLKG, which can also be considered as a delay, the initial PWM signal is generated by the first PWM generation block based on the display data and CLKG, and the stretched PWM signal is generated by the second PWM generation block based on the initial PWM signal and CLKs. If the width of the initial PWM is L, after widening, the width of the finally obtained PWM signal is L + K T; t is the clock period. When the clock period T is constant, the size of K determines the width of widening the initial PWM signal, and also determines the width of the final PWM signal, thereby determining the time for turning on the constant current source, that is, the time for lighting the LED. We can choose the value of K (also can be considered as the value of H) according to the actual display effect, i.e. choose which delayed clock signal to output as the PWM stretched clock signal via the first device under the condition of choosing the initial clock signal. It will be appreciated that by this broadening of the K x T width, the aforementioned loss of LED turn-on time due to non-idealities can be compensated for. Of course, the logic module of the present application may also be an and gate, an or gate, a nand gate, a nor gate, an exclusive or, or a logic circuit composed of these logic gates, and the logic circuit is used to perform the logic operation of the first PWM wave and the second PWM wave. It is understood that, in addition to widening the first PWM signal and the second PWM signal by performing an or operation, other logic operations are actually used to perform corresponding processing, and widening of the PWM can also be implemented. In particular, when using and gates, the original display data may be processed first, for example, by adding a width of one clock cycle, for example, changing 3.4T to 4.4T, so that the width of the PWM signal output by the and gate is actually the original width corresponding to 3.4T. Of course, regardless of the logic circuitry employed, the above-described operations may be performed on the raw display data to accommodate all types of display data. In this case, however, appropriate selection of logic is required to ensure that appropriate display data is ultimately obtained.

Optionally, the first PWM generating module and the second PWM module are flip-flops, preferably D flip-flops. For example, the flip-flop has two input terminals, a D terminal receives display data (a first PWM generating module) or a first PWM signal (a second PWM generating module), a CK terminal (i.e., a CLK terminal) receives a PWM generating clock signal (the first PWM generating module) or a PWM stretching clock signal (the second PWM generating module), and when the D terminal inputs 0, the output terminal Q outputs 0 at a clock rising edge, and when the D terminal inputs 1, the output terminal Q outputs 1 at the clock rising edge. The present application generates the first PWM signal and the second PWM signal based on this principle. Therefore, when a PWM signal of a certain width is input to the D terminal, the Q terminal outputs a PWM signal of the same width after a clock rising edge.

In some embodiments, referring to fig. 10, the number of the PWM modules and the number of the channel current output modules are M; the PWM modules are connected with the channel current output modules in a one-to-one corresponding mode; the path matching module is connected with each PWM module and outputs the PWM broadening clock signal and the PWM generation clock signal to each PWM module; wherein M is an integer greater than or equal to 4. M represents the number of channels in the driving circuit, and the same brightness compensation is performed on each channel by sending the two clock signals output by the path matching module 1 to the PWM module of each channel. It will be appreciated that since the PWM stretched clock signal received by each channel and the PWM generated clock signal are the same, the compensation for the time or brightness of each channel is the same.

Specifically, the multi-phase clock generation module generates N clock signals CLK [0] -CLK [ N-1], selects CLK [0] to input into the first logic circuit of the path matching module 1, and outputs the final PWM generated clock to the PWM module after passing through the first logic circuit; the first device outputs one of CLK [0] -CLK [ N-1] corresponding to the cs signal as a final PWM stretched clock signal to the PWM module through a circuit inside the first device based on a corresponding selection signal (cs signal) output by a decoder or other selection module according to a received control word. The two clock signals (PWM generated clock signal and PWM stretched clock signal) pass through the same path and circuit from the input to the path matching block 1 to the output path matching block 1. The two clock signal output path matching modules 1 are input into M PWM modules, that is, into PWM modules of each channel, each PWM module generates a broadened PWM signal based on the clock signal and the display data received by each PWM module, and then inputs the broadened PWM signal into a channel current output module corresponding to the channel, so that a constant current can be output through the module to drive an LED to light. By the method, each channel can be compensated for a small number of clock cycles, namely the LED lighting time, so that the brightness loss caused by non-ideal factors is avoided; on the other hand, the compensation can be more accurate through a special path matching module.

In another aspect, the present application further provides a driving chip, which includes the foregoing display driving circuit.

In another aspect, the present application further provides a display apparatus, which includes a display device and the above driving chip, where the driving chip generates a driving signal to drive the display device to display. The display device in this embodiment should be interpreted as an advertisement screen, a television, or the like, and can independently perform display of a signal or a picture.

The foregoing is illustrative of the preferred embodiments of the present application, and it is to be understood that the invention is not limited to the precise forms disclosed herein and that various other combinations, modifications, and environments may be used, which are within the scope of the invention as expressed herein, and which are intended to be modified by the teachings herein or by the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.

Claims

1. A driver circuit, comprising:

the path matching module is used for eliminating unknown phase difference between the PWM broadening clock signal and the PWM generation clock signal;

the difference between the PWM broadening clock signal and the PWM generating clock signal is K complete clock cycles, wherein K is more than or equal to 0 and less than 1;

the path matching module includes:

a first means for outputting said PWM stretched clock signal after a plurality of delayed clock signals pass through said first means;

the logic path of the initial clock signal through the first logic circuit is identical to the logic path of the delayed clock signal through the first device;

the PWM module includes:

the first PWM generating module is used for generating a first PWM signal based on the display data and the PWM generating clock signal;

2. A driving circuit according to claim 1, further comprising a multi-phase clock generation module for generating N clock signals with the same phase difference as the initial clock signal and the delayed clock signal.

3. A driver circuit according to claim 2, wherein the first means is a multiplexer for selecting one of the N delayed clock signals to be output as the PWM stretched clock signal.

4. The driving circuit according to claim 1, wherein the first PWM generation module and the second PWM generation module are D flip-flops.

5. A driver circuit according to any of claims 1-4, wherein the logic block performs a logical OR operation, or a logical AND operation.

6. The driving circuit according to any one of claims 1 to 4, wherein the number of the PWM modules and the number of the channel current output modules are M; the PWM modules are connected with the channel current output modules in a one-to-one corresponding mode; the path matching module is connected with each PWM module and outputs the PWM broadening clock signal and the PWM generation clock signal to each PWM module; wherein M is an integer greater than or equal to 4.

7. A driver chip comprising the driver circuit according to any one of claims 1 to 6.

8. A display apparatus comprising a display device and the driver chip of claim 7, wherein the driver chip generates a driving signal to drive the display device to display.