CN116360235A - TDC realizing device based on SerDes - Google Patents

Abstract

The invention belongs to the field of time interval measurement, and particularly relates to a TDC (time-dependent digital converter) realization device based on SerDes, which comprises a clock module, a gate signal generation module, a SerDes sampling and receiving module and a data decoding module. Based on the characteristics that the SerDes resource in the FPGA can achieve ultra-high data rate and the SerDes sampling output is lower-speed parallel data which can be processed by the FPGA in real time, the device enables the time interval measuring range to be increased to the second level by matching the SerDes sampling module with the data decoding module. In addition, by utilizing the unified standard delay characteristics of the high-performance phase-locked loop and the shift register in the SerDes sampling receiving module, the TDC realizing device has better linear performance, meanwhile, a complex clock circuit in a clock multipath phase shift method is omitted, the design of an FPGA peripheral circuit is simplified, the number of IO ports and the complexity of a system required by the FPGA are reduced, and the application range of the device is widened.

Description

TDC realizing device based on SerDes

Technical Field

The invention belongs to the field of time interval measurement, and particularly relates to a TDC implementation device based on SerDes.

Background

In many working scenarios of modern science and industry, it is often necessary to make accurate measurements of the time interval between two or more physical events. Such as measuring the difference between the loop and the reference clock in a phase locked loop to avoid clock drift or measuring the time between transmission and reception to find out about the object reflected by the signal or the environmental information through which the signal passes, and in addition, have wide application in the fields of nuclear physics, quantum experiments, medical imaging, etc.

Currently, a number of digital converters (Time-to-Digital Convertor, TDC) are used to measure Time intervals, and the digital converters are deployed in a special TDC chip, a TDC circuit based on a field programmable gate array (Field Programmable Gate Array, FPGA), etc., where the TDC implementation based on the FPGA is the most mainstream, and can also be better adapted to various application scenarios. The traditional FPGA-based TDC mainly realizes high-precision measurement through a data delay chain or clock multipath phase shifting, the data delay chain has extremely high requirements on internal layout and wiring of the FPGA, the delay time of data passing through various delay units is not stable enough, the linearity of the TDC is affected, and meanwhile, the length of the delay chain is wired, so that the measurement range is smaller, and the method is not suitable for large-time interval measurement. The clock multipath phase shift mode is that multipath phase shift is carried out on a sampling clock outside the FPGA through a clock management and clock phase shift module, and the data are sampled by a plurality of clocks after phase shift, so that the sampling rate is equivalently improved, the measurement accuracy is further improved, and the nanosecond level can be achieved generally. The method has a larger measurement range, but a complex clock module is added outside the FPGA, so that the cost is higher.

Disclosure of Invention

The invention aims at: the device for achieving the TDC based on the SerDes solves the problems that an existing TDC is complex in structure, measurement accuracy and measurement range cannot be considered, and therefore the application range is narrow.

A SerDes-based TDC implementation apparatus comprising: the system comprises a clock module, a gate signal generation module, a SerDes sampling receiving module and a data decoding module;

the clock module provides synchronous reference clock signals for the SerDes sampling receiving module and the data decoding module respectively; the gate signal generating module receives the time starting signal and the time ending signal, converts time interval information contained in the two signals into a gate signal with the same gate width as the measured time interval, and outputs the gate signal to the SerDes sampling receiving module;

the SerDes sampling receiving module comprises a phase-locked loop module and a receiver, wherein the phase-locked loop is connected with the clock module and is used for receiving a reference clock signal and performing frequency multiplication and frequency division on the reference clock signal to obtain a working clock signal and sending the working clock signal to the receiver; the receiver is connected with the gate signal generating module and is used for sampling the gate signal, converting the sampled gate signal from high-speed serial data into low-speed parallel data according to the received working clock signal and transmitting the low-speed parallel data to the data decoding module;

the data decoding module is connected with the SerDes sampling receiving module, and performs operation decoding on the received low-speed parallel data output by the SerDes based on the reference clock provided by the clock module to obtain the duration of the gate signal, thereby completing the measurement of the time interval.

Further, the gate signal generating module consists of a start pulse signal receiving circuit, an end pulse signal receiving circuit and a gate signal synthesizing circuit; the start pulse signal receiving circuit receives a time start signal, the end pulse signal receiving circuit receives a time end signal, and the gate signal synthesizing module synthesizes the time start signal and the time end signal according to the width of the gate signal to obtain gate signal output; the time starting signal is the rising edge of the circuit detection starting pulse signal, the time ending signal is the rising edge of the circuit detection ending pulse signal, and the width of the gate signal is the time interval between the rising edges of the starting pulse signal and the ending pulse signal; the gate signal may be considered high-speed serial data.

Further, the decoding method of the data decoding module comprises the following steps:

s1, identifying and counting '0' and '1' in received low-speed parallel data, and counting '1' in the data when '1' starts to appear in the identified low-speed parallel data; stopping counting and outputting a count value when '0' appears in the identified low-speed parallel data; the count value indicates the number of '1's in the received low-speed parallel data, and one '1' indicates that the gate signal lasts for one SerDes sampling clock period;

s2, calculating an input time interval delta t according to the count value obtained in the S1 and a reference clock signal provided by the clock module, and completing measurement of the time interval.

The TDC implementation device based on the SerDes provided by the invention is based on the characteristic that the SerDes resource in the FPGA can reach the ultra-high data rate, the working clock can reach tens of gigahertz, the picosecond time resolution is realized, and the SerDes sampling output is parallel data which can be processed in real time by the lower-speed FPGA, and the time interval measuring range is increased to the second level by matching with a data decoding module insensitive to the storage depth. In addition, due to the unified standard delay characteristics of the high-performance phase-locked loop and the shift register in the SerDes sampling receiving module, the TDC based on SerDes has better linear performance, meanwhile, a complex clock circuit in a clock multipath phase shift method is omitted, the design of an FPGA peripheral circuit is simplified, the number of IO ports and the complexity of a system required by the FPGA are reduced, and the application range of the FPGA is widened.

Compared with the prior art, the invention has the characteristics of simple structure, lower cost, better linear performance and the like, realizes high precision, has a larger measurement range, can greatly simplify the deployment requirement of the TDC, and is beneficial to expanding the application range of the TDC.

Drawings

FIG. 1 is a schematic diagram of a TDC device according to an embodiment;

FIG. 2 is a schematic diagram of a SerDes sampling receiving module in a TDC device according to an embodiment;

FIG. 3 is a flow chart of a data decoding module in the TDC device according to an embodiment;

fig. 4 is a schematic diagram of a time interval measurement process in the TDC apparatus according to the embodiment.

Detailed Description

The following description of the embodiments of the invention is presented in conjunction with the accompanying drawings to facilitate a better understanding of the invention to those skilled in the art. It is to be expressly noted that in the description below, detailed descriptions of known functions and designs are omitted here as perhaps obscuring the present invention.

Fig. 1 is a schematic diagram of a TDC apparatus according to an embodiment. As shown in fig. 1, the TDC implementation device based on SerDes provided in this embodiment includes: the system comprises a clock module, a gate signal generation module, a SerDes sampling receiving module and a data decoding module. The clock module is respectively connected with the SerDes sampling receiving module and the data decoding module and is used for providing synchronous reference clock signals for the SerDes sampling receiving module and the data decoding module. The gate signal generating module, the SerDes sampling receiving module and the data decoding module are sequentially connected in series.

Fig. 2 is a schematic diagram of a SerDes sampling receiving module structure. As shown in fig. 2, the SerDes sampling reception mode includes a phase-locked loop module and a receiver. The phase-locked loop is connected with the clock module and is used for receiving the reference clock signal, performing frequency multiplication and frequency division on the reference clock signal to obtain a working clock signal, and then transmitting the working clock signal to the receiver; the receiver is connected with the gate signal generating module and is used for sampling the gate signal, converting the sampled gate signal from high-speed serial data into low-speed parallel data according to the received working clock signal and sending the low-speed parallel data to the data decoding module. Because the working frequency of the internal clock of the FPGA is limited, usually hundreds of megahertz, serDes is used as a high-speed transmission resource in the FPGA, and a high-speed serial data signal input by an input pin of the FPGA can be converted into a low-speed (less than or equal to 500 MHz) parallel data signal which can be processed in real time in the FPGA, so that the internal processing of the FPGA is facilitated. The sample value is "1" when the input signal is digital high level, and "0" when the input signal is digital low level. The internal clock resource has ultrahigh stability, and the internal shift register has unified standard delay, so that the TDC device based on SerDes has better linear performance. The internal sampling rate of the SerDes sampling receiving module can reach tens of gigahertz, the corresponding time resolution reaches picosecond order, and higher measurement accuracy is realized.

Fig. 3 is a flow chart of the data decoding module in the present invention. As shown in fig. 3, when the low-speed parallel data output by the SerDes sampling receiving module is sent to the data decoding module, the data decoding module identifies the cases of "0" and "1" in the received low-speed parallel data. Counting "1" in the data when it is detected that "1" starts to appear in the data; in the counting process, when '0' appears in the identified low-speed parallel data, the counting is stopped and a count value is output. The count value represents the number of "1" s in the data, and one "1" represents that the gate signal continues for one SerDes sampling clock period, so that the input time interval Δt can be conveniently calculated.

Wherein n is a count value of "1" in the data, T ₀ Sampling clock period, f for SerDes _s For the SerDes sampling clock frequency,

the error of the measurement result mainly comes from the + -1 error of the counter, the corresponding measurement result has the measurement error of + -T, and the error does not exceed one sampling period of SerDes. Because the number of '1' is only counted, the bit width of the counter can reach hundreds of bits, and the time interval measuring range of the device can be conveniently expanded. The invention realizes picosecond measurement precision by utilizing the SerDes ultra-high sampling frequency, and ensures an ultra-long measurement range by adopting a data decoding mode.

Claims (3)

1. A method and device for realizing TDC based on SerDes comprises the following steps: the system comprises a clock module, a gate signal generation module, a SerDes sampling receiving module and a data decoding module, and is characterized in that:

the clock module provides synchronous reference clock signals for the SerDes sampling receiving module and the data decoding module respectively; the gate signal generating module receives the time starting signal and the time ending signal, converts time interval information contained in the two signals into a gate signal with the same gate width as the measured time interval, and outputs the gate signal to the SerDes sampling receiving module;

the SerDes sampling receiving module comprises a phase-locked loop module and a receiver, wherein the phase-locked loop is connected with the clock module and is used for receiving a reference clock signal and performing frequency multiplication and frequency division on the reference clock signal to obtain a working clock signal and sending the working clock signal to the receiver; the receiver is connected with the gate signal generating module and is used for sampling the gate signal, converting the sampled gate signal from high-speed serial data into low-speed parallel data according to the received working clock signal and transmitting the low-speed parallel data to the data decoding module;

the data decoding module is connected with the SerDes sampling receiving module, and performs operation decoding on the received low-speed parallel data output by the SerDes based on the reference clock provided by the clock module to obtain the duration of the gate signal, thereby completing the measurement of the time interval.

2. The SerDes-based TDC implementation method apparatus according to claim 1, wherein: the gate signal generating module consists of a start pulse signal receiving circuit, an end pulse signal receiving circuit and a gate signal synthesizing circuit; the start pulse signal receiving circuit receives a time start signal, the end pulse signal receiving circuit receives a time end signal, and the gate signal synthesizing module synthesizes the time start signal and the time end signal according to the width of the gate signal to obtain gate signal output; the time starting signal is the rising edge of the circuit detection starting pulse signal, the time ending signal is the rising edge of the circuit detection ending pulse signal, and the width of the gate signal is the time interval between the rising edges of the starting pulse signal and the ending pulse signal; the gate signal may be considered high-speed serial data.

3. The SerDes-based TDC implementation method device according to any one of claims 1-2, wherein: the decoding method of the data decoding module comprises the following steps:

s1, identifying and counting '0' and '1' in received low-speed parallel data, and counting '1' in the data when '1' starts to appear in the identified low-speed parallel data; stopping counting and outputting a count value when '0' appears in the identified low-speed parallel data; the count value indicates the number of '1's in the received low-speed parallel data, and one '1' indicates that the gate signal lasts for one SerDes sampling clock period;

s2, calculating an input time interval delta t according to the count value obtained in the S1 and a reference clock signal provided by the clock module, and completing measurement of the time interval.

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