JP5666813B2 - Time width measuring device - Google Patents

Description

  The present invention relates to a time width measuring apparatus, and more particularly to a time width measuring apparatus for measuring a pulse time width of a signal under measurement.

  In the inspection of a digital circuit, it is desired to measure the time width with the highest possible accuracy such as the width of a pulse included in the signal under measurement and the delay time.

  In the prior art, for example, in order to measure the pulse width of a signal under measurement having a time width T, the time between rising / falling edges of the signal under measurement is a reference having a predetermined clock frequency as shown in FIG. Counting using the clock.

  Further, since the signal under measurement and the reference clock are asynchronous, a “fractional time” shorter than the cycle of the reference clock occurs at the measurement start and end edges. The fractional time is measured by performing A / D conversion after performing T / V (time / voltage) conversion.

  Therefore, the pulse width of the signal under test is T, the clock frequency of the reference clock is t0, the number of counted reference clocks is n, and one clock period is added to the fractional time generated at the start and end of measurement. Assuming that the time (fraction pulse time) is Ta and Tb, respectively, T can be obtained by the following equation.

  T = n · t0 + (Ta−Tb)

Sano, Katano, Iwatsubo, Shinmen, “Time Interval Analyzer TA320”, Yokogawa Technical Report Vol. 41 no. 1 (1997)

  With the recent increase in the speed of digital circuits, the inspection of semiconductor devices has been required to have a resolution of nsec to several tens of psec. In order to improve the resolution, it is only necessary to increase the clock frequency of the reference clock in the conventional technique described above.

However, at present, the clock frequency of a high-speed processing IC used for time width measurement is several hundred MHz at most, so there is a limit to increasing the resolution by increasing the clock frequency of the reference clock.
Therefore, an object of the present invention is to improve the resolution in time width measurement.

  In order to achieve the above-described object, a time width measuring apparatus according to the present invention includes a reference clock generating means for generating a clock signal at a known clock frequency, a digital signal obtained by sampling the signal under measurement based on the clock signal. A sampling means for outputting the digital signal, a conversion means for serial / parallel conversion of the digital signal sampled by the sampling means to output a parallel signal having a predetermined number of bits, and the parallel signal output by the conversion means are stored. Storing means for calculating the time width included in the signal under measurement based on the parallel signal stored in the storage means.

  Here, all the values of the counting means for counting the number of the parallel signals output from the converting means and the parallel signals output from the converting means are the same, and the values are output last time. Control means for preventing the storage means from storing a parallel signal that is the same as the last value of the parallel signals, and the storage means includes the number of parallel signals output from the conversion means, 1 and 0, The parallel signal having the conversion point is stored, and the calculating means includes the number of the parallel signals output from the conversion means, the number of 1 or 0 counted from the parallel signal having the conversion points, A time width included in the signal under measurement may be calculated from the clock frequency and the length of the parallel signal.

  In the present invention, a digital signal obtained by sampling a signal under measurement based on a clock signal having a known clock frequency is serial / parallel converted into a parallel signal, and a time width included in the signal under measurement is calculated based on the parallel signal. Therefore, while increasing the clock frequency used for sampling, the clock frequency of the storage means and the calculation means for calculating the time width based on the parallel signal can be kept lower than the sampling clock frequency. In other words, the reference clock generation means, sampling means, and conversion means related to sampling and serial / parallel conversion can achieve ultra-high speed compared with calculation means related to the calculation of the time width of the subsequent stage. The resolution in time width measurement can be improved by increasing the clock frequency used for sampling.

  Further, the storage means stores the number of the parallel signals output from the conversion means and a parallel signal having conversion points of 1 and 0, and the time width included in the signal under measurement is based on the information. As a result, the data processing can be further accelerated compared to the case where all parallel signals are stored and processed.

It is a figure which shows the structure of the time width measuring apparatus which concerns on embodiment of this invention. It is a figure explaining the example of the time width which can become a measuring object. It is a figure explaining the signal processing in the time width measuring device which concerns on embodiment of this invention. It is a figure explaining an example of the data structure of the memory in the time width measuring device which concerns on embodiment of this invention. It is a figure explaining an example of FPGA with which the ultrahigh-speed communication function utilized for the time width measuring apparatus which concerns on embodiment of this invention was added. It is a figure explaining the prior art.

Embodiments of the present invention will be described below with reference to the drawings.
A time width measuring apparatus according to an embodiment of the present invention is an apparatus for measuring a pulse width (time width of a pulse), and one configuration example is shown in FIG.

<Configuration of time width measuring device>
The time width measuring apparatus according to the present embodiment generates a clock signal at a known clock frequency (f _clock ) and an input circuit 1 that inputs a signal under measurement (pulse signal) a to a serial input terminal of a deserializer 3 to be described later. Then, the reference clock generation source 2 input to the clock input of the deserializer 3 and the signal to be measured a are sampled based on the clock signal from the reference clock generation source 2, and the sampled digital signal is serial / parallel converted. A deserializer 3 that outputs a parallel signal c of n bits (where n is an integer equal to or greater than 2), a memory 4 that stores the parallel signal c output by the deserializer 3, and a parallel stored in the memory 4 An arithmetic circuit (MPU) 5 for calculating the pulse width (time width) of the signal under measurement a based on the signal; By controlling the memory 4, all the values of the parallel signal c output from the deserializer 3 are the same, and the value (for example, the head c _{01 of the} parallel signal output this time) was output last time. A control circuit 6 that does not store in the memory 4 a parallel signal that is the same as the last value c ₁₀ of the parallel signal, and a counter 7 that counts a clock obtained by dividing the clock signal from the reference clock generation source 2 by 1 / n. Is done.

Here, as an example of the time width measurement, it is assumed that the delay time between two pulse signals is measured. The input circuit 1 in this embodiment is a delay between two pulse signals (INPUT 1 and INPUT 2). This circuit outputs a signal having a pulse width corresponding to time (t _delay ) (see FIG. 2A) as a signal under measurement. Specifically, as shown in FIG. 1, the input circuit 1 corresponds to two comparators 11 a and 11 b, an edge selector 12 that detects edges of the outputs of these comparators, and an interval between the detected edges. The flip-flop circuit 13 outputs a pulse signal having a time width.

In the present embodiment, an example of the input circuit 1 for measuring the delay time is shown. However, by appropriately selecting an appropriate input circuit, as shown in FIG. also, the rise time (t _r) and the fall time (t _f) (FIG. 2 (b)), ON time (t _on), OFF time (t _off), the duty ratio _{(duty ration = t on / (} t on + T _off ) × 100 (%)) (FIG. 2C), period (T _period ), frequency (F = 1 / T _period ) can be measured.

The reference clock generation source 2 has an extremely fast clock frequency (f _clock ). The resolution of the time width measurement is the reciprocal of this clock frequency (f _clock ).
Note that the clock frequency (f _clock ) of the reference clock generation source 2 may be arbitrarily determined according to a desired resolution. Therefore, for example, in order to obtain a resolution of 1 ns, it is necessary to set the clock frequency (f _clock ) of the reference clock to 1 GHz or more. For example, when used for inspection of a semiconductor element, it is desirable to set a clock frequency of 3 GHz or more.

  The deserializer 3 performs serial / parallel conversion on a digital signal obtained by sampling the signal under measurement based on the clock signal from the reference clock generation source 2 and outputs an n-bit parallel signal.

FIG. 3 is a diagram for explaining signal processing in the time width measuring apparatus when n = 10, more specifically, in the deserializer 3 as an example. This figure shows a state in which a serial digital signal b obtained by sampling the signal under measurement a in synchronization with the clock signal from the reference clock generation source 2 is serial / parallel converted into a 10-bit parallel signal. .
As shown in FIG. 3, the signal under measurement a (FIG. 3A) is first sampled by the deserializer 3 based on the clock signal from the reference clock generation source 2. As a result, “1” (or “H”, hereinafter referred to as “H”) or “0” (or “L”, depending on the state (“H” or “L”) of the signal under measurement a. , “L”) is obtained as a digital signal (see FIG. 3B), and serial / parallel conversion is performed to obtain an n-bit (n = 10) parallel signal c (FIG. 3C). )) Get.
These parallel signals c are sequentially input to the memory 4 and the control circuit 6.

Further, the deserializer 3 divides the clock signal from the reference clock source 2 by 1 / n, and a clock signal having a clock frequency of f _clock / n synchronized with the parallel signal is a _subsequent circuit, that is, a memory 4 and an arithmetic circuit. (MPU) 5, control circuit 6, counter 7, etc. Therefore, the circuit subsequent to the deserializer 3 operates at a clock frequency of f _clock / n that is slower than the clock frequency of the clock signal supplied from the reference clock generation source 2.

  In the present embodiment, the counter 7 counts the number of clocks obtained by dividing the clock signal from the reference clock source 2 by 1 / n, so that the number d of parallel signals output from the deserializer 3 (FIG. 3 (d)). Count.) The number of parallel signals counted in this way is stored in the memory 4 in association with the parallel signal.

The control circuit 6 has the same value for all of the parallel signals output from the deserializer 3, and the value (for example, the top c _{01 of the} parallel signal output this time) of the parallel signal output last time. a control means is not stored in the parallel signal memory 4 is the same as the last value c _10. In the present embodiment, as shown in FIG. 1, the control circuit 6 includes an n-bit latch circuit 61 and various logic gates, and converts “H” to “L” or “L” to “H”. A parallel signal having a point is stored in the memory 4, while appearing between two parallel signals having a conversion point, and all values are the same (that is, consisting of only “H” or “L”). Is not stored in the memory 4.
Here, “a parallel signal having a conversion point” means that a part of n bits constituting the parallel signal is 1 (“H”) and the remaining is 0 (“L”). Even when all n bits constituting the parallel signal have the same value, even when there is a conversion point between the parallel signal and the immediately preceding parallel signal, it falls under “parallel signal having conversion point” And

In the present embodiment, as shown in FIG. 1, of the two parallel signals continuous in time series, the last bit at the last time is “H” and the first bit at this time is “L”. In this case (STATE A), and when the last bit of the previous time is “L” and the first bit of this time is “H” (STATE B), all the parallel signals of this time are “H”. If not (STATE C), and if all of the current parallel signals are not “L” (STATE D), the current parallel signals are stored in the memory 4.
In short, a parallel signal is a parallel signal up to that point only when there is a conversion point at the transition of the parallel signal (STATE A and STATE B) and when there is a conversion point in the middle of the parallel signal (state C and STATE D). Are stored in the memory 4 together with the number of the signals, while appearing between two parallel signals having a conversion point, all the values are the same, that is, a parallel signal consisting of only “H” or “L” is stored in the memory 4 Is not remembered.

The memory 4 stores the parallel signal having the conversion point in association with the number of parallel signals counted by the counter 7 so far.
An example of the data structure of such a memory 4 is shown in FIG. In FIG. 4, the “c” column represents parallel signals, and the “d” column represents the number of parallel signals output by the deserializer 3 after the start of measurement (START). Therefore, it can be understood that the number of parallel signals represents the order in which the parallel signals are generated after the start of measurement.
For example, when the digital signal c shown in FIG. 3 is output by the deserializer 3, the memory 4 has d = 0th, 1 including the H / L conversion point in the parallel signal c, as shown in FIG. The second and third parallel signals are stored in association with the number d, while the second parallel signal of d = 2 is the same as the parallel signal of d = 1 with all bits being “L”. Since both d = 3 parallel signals include conversion points, they are not stored in the memory 4.

As described above, by storing the number of parallel signals output after the start of measurement (START) in association with the parallel signal having the conversion point, it appears between the two parallel signals having the conversion point, and It is possible to calculate the number of parallel signals in which all the values are only 1 or 0.
For example, in the example shown in FIG. 4, d = 3rd parallel signal is stored next to d = 1st parallel signal, and the value of d is discontinuous. Therefore, it can be seen that there is one parallel signal of which all the values are only 0 (“L”) between the d = 1st parallel signal and the d = 3rd parallel signal.

The arithmetic circuit (MPU) 5 counts the number (x) of “H” contained in the parallel signal having the conversion point stored in the memory 4, and information d regarding the number of parallel signals stored in the memory 4. The number (y) of parallel signals that appear between two parallel signals having conversion points and that all consist of only 1 or 0 is counted.
Then, from the known clock frequency (f _clock ) and the length (n bits) of the parallel signal, the time width T of the pulse included in the signal under measurement is calculated by the following arithmetic expression and output.

T = (x + n · y) · ( 1 / f _clock ) (1)

<Use of communication FPGA for time width measuring device>
In order to realize the above-described time width measuring apparatus, a dedicated integrated circuit (IC) may be created for time width measurement. However, the reference clock generation source 2 and the deserializer 3 are commercially available for communication. A field programmable gate array (FPGA) may be used. At present, 3 GHz is practically used as the clock frequency of the reference clock generation source 2. In the future, if the FPGA with a serial interface can be further increased in speed, the resolution of time width measurement can be further improved.
The case where the communication FPGA is used for time width measurement will be described below.

  The FPGA is a highly integrated logic circuit in which a large number of general-purpose logic elements are integrated and connection information between the elements can be set from the outside. In recent years, FPGAs to which an ultrahigh-speed serial communication function is added are also commercially available. Such an FPGA has a function of serial / parallel conversion of serial data into, for example, a parallel signal of about 10 bits. The serial communication function unit transmits or receives communication data as serial data, while the general-purpose logic of the FPGA. The circuit unit is configured to process this parallel signal. Therefore, for example, even in ultra-high-speed communication using the GHz band such as optical communication, only the serial communication function unit needs to operate at ultra-high speed, and the FPGA general-purpose logic circuit unit performs parallel signal processing. Therefore, the operation speed is less than 1/10 of the serial communication function unit.

FIG. 5 is a block diagram showing a configuration example of a communication FPGA having an ultrahigh-speed serial interface. In FIG. 5, the communication FPGA includes a communication FPGA reception channel 100 and an FPGA fabric 200 corresponding to a reception (Rx) path.
Among them, the communication FPGA reception channel 100 is connected in cascade with a reception PMA (Rx physical medium attachment, hereinafter referred to as “RxPMA”) 110 and a reception PCS (Rx physical coding sublayer, hereinafter referred to as “RxPCS”). ) 120 and a parallel interface 130.
Of the communication FPGAs equipped with such an ultrahigh-speed serial interface, the RxPMA 110 can be used as the deserializer 3 in the time width measuring apparatus according to the present embodiment. The remaining configuration merely allows the signal to pass therethrough and has no particular effect on the time width measurement, and therefore the description thereof is omitted.
Note that the communication FPGA having an ultra-high-speed serial interface is described in detail in, for example, “Cyclone IV Device Handbook, Volume 2”, Altera Corp., November 2009, and the like.

  The RxPMA 110 includes a CDR (Clock Data Recovery) unit 111 and a deserializer unit 112, which function as the reference clock generation source 2 and the deserializer 3 according to the present embodiment, respectively.

  In so-called ultrahigh-speed serial communication, a data transmission side transmits a data with a clock superimposed, and a reception side separates the data and the clock. The CDR unit 111 is a circuit for establishing a clock on the receiving side. The CDR unit 111 can select whether the data read clock source for serial communication is an internal clock of the FPGA or an external clock regenerated from the received signal. When used as a time width measuring device, an internal clock is selected.

The deserializer unit 112 has a function of converting serial data into a parallel signal in units of a fixed number of bits (for example, 10 bits or 18 bits) and transferring the parallel signal to a general-purpose logic circuit unit at a subsequent stage. By using parallel signals, the transfer data rate can be reduced by the number of parallelized bits, and the operation speed of the subsequent circuit can be reduced by that amount.
For example, even if the transfer rate of serial data is 3 GHz, if the deserializer unit 112 converts it to an 18-bit parallel signal, the subsequent stage operates at 166 MHz. This speed is sufficient for today's FPGA general-purpose logic circuits.

<Operation of the time width measuring apparatus according to the present embodiment>
The operation of the time width measuring apparatus according to the present embodiment having the configuration shown in FIG. 1 is as follows.
First, when two pulse signals as shown in FIG. 2A are input to the two input terminals (INPUT 1 and INPUT 2) of the input circuit 1, respectively, the delay time between these input pulse signals is determined. A signal under measurement a (see FIG. 3A) having a pulse width is obtained. This signal under measurement a is input to a serial input terminal (SERIAL INPUT) of the deserializer 3.

The signal under measurement a is sampled in the deserializer 3 based on the clock signal from the reference clock generation source 2. The sampling frequency at this time is equal to the clock frequency (f _clock ) of the reference clock generation source 2. As a result, a digital signal of “1” (or “H”) or “0” (or “L”) depends on the state of the signal under measurement a (“H” or “L”, FIG. 3A). can get. This digital signal is a serial signal synchronized with the clock signal from the reference clock generation source 2 (see FIG. 3B). This serial digital signal is serial / parallel converted by the deserializer 3, and an n-bit parallel signal c is output (FIG. 3C).
The parallel signal c is input to the “DATA IN” terminal of the memory 4, but is not written to the memory 4 until the START terminal is set to the “H” level.

  When the START terminal is set to the “H” level and the measurement is started, a write control signal is given to the “WRITE ENABLE” terminal of the memory 4 according to the output of the control circuit 6, and only the parallel signal having the conversion point is given. Is stored in the memory 4. At this time, the number of parallel signals generated from the start of measurement until the parallel signal (the order in which the parallel signals are generated) is stored in association with the parallel signal (see FIG. 4).

The arithmetic circuit (MPU) 5 analyzes the parallel signal stored in the memory 4, and if there is a pair (two) of parallel signals having conversion points, as described above, the arithmetic circuit (MPU) 5 converts the parallel signals having conversion points. The number of included 1 (“H”) (x) and the number of parallel signals (y) appearing between the two parallel signals having these conversion points are counted, and the known clock frequency (f _clock ) Then, the time width T of the pulse included in the signal under measurement is calculated from the length (n bits) of the parallel signal by the equation (1) and output.

  As described above, the pulse width of the signal under measurement can be measured. By increasing the clock frequency of the reference clock generation source 2, the resolution of the time width measurement can be increased. Moreover, since the digital signal obtained by sampling the signal under measurement is converted into a parallel signal by serial / parallel conversion, processing such as counting can be performed with a clock of 1 / n of the clock frequency of the reference clock source 2. it can.

  In the present embodiment, a control circuit 6 is provided to store a parallel signal having a conversion point from 1 to 0 or 0 to 1, in the memory 4, while between two parallel signals having a conversion point. Parallel signals that appear and all have the same value (that is, only 1 (“H”) or 0 (“L”)) are not stored in the memory 4. Furthermore, the number of parallel signals output from the deserializer 3 and the parallel signals having conversion points of 1 and 0 are stored in association with each other. By providing such a configuration, it is possible to speed up data processing as compared with the case where all parallel signals are stored in the memory 4 and processed.

  Furthermore, in the prior art, the time / voltage conversion circuit used for the fractional time measurement is expensive, and there is a problem that a space for mounting these circuit components is required. Since a time / voltage conversion circuit is not required, the time width measuring device can be reduced in cost, space-saving and downsized.

  The present invention can be used for inspections and evaluations involving time width measurement.

  DESCRIPTION OF SYMBOLS 1 ... Input circuit, 2 ... Reference clock generation source, 3 ... Deserializer, 4 ... Memory, 5 ... Arithmetic unit, 6 ... Control circuit, 7 ... Counter

Claims (1)

A reference clock generating means for generating a clock signal at a known clock frequency;
Sampling means for sampling the signal under measurement based on the clock signal and outputting a digital signal;
Conversion means for serial / parallel conversion of the digital signal sampled by the sampling means to output a parallel signal having a predetermined number of bits;
Storage means for storing the parallel signal output by the conversion means;
Calculation means for calculating a time width included in the signal under measurement based on the parallel signal stored in the storage means ;
Counting means for counting the number of the parallel signals output from the conversion means;
Control means that does not store in the storage means a parallel signal in which all values of the parallel signal output from the conversion means are the same and the same value as the last value of the parallel signal output last time When
With
The storage means stores the number of the parallel signals output from the conversion means and a parallel signal having a conversion point of 1 and 0,
The calculation means includes the number of the parallel signals output from the conversion means, the number of 1 or 0 counted from the parallel signal having the conversion point, the clock frequency, and the length of the parallel signal. Calculate the time width included in the signal under measurement
A time width measuring apparatus characterized by that .

Images